mirror of
https://github.com/DrHo1y/orangepi-build.git
synced 2026-10-09 20:06:39 +07:00
Update dts for OrangePi Zero2 LTS/B
This commit is contained in:
@@ -3478,7 +3478,7 @@
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//sd-uhs-ddr50;
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//sd-uhs-sdr104;
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ctl-spec-caps = <0x8>;
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vdmmc-supply = <®_dcdc5>;
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//vdmmc-supply = <®_dcdc5>;
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};
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sdmmc@04021000 {
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@@ -1371,7 +1371,7 @@
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};
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uart2@0 {
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allwinner,pins = "PG15", "PG16", "PG17", "PG18";
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allwinner,pins = "PH5", "PH6", "PH7", "PH8";
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allwinner,pname = "uart2_tx", "uart2_rx", "uart2_rts", "uart2_cts";
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allwinner,function = "uart2";
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allwinner,muxsel = <0x2>;
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@@ -1382,7 +1382,7 @@
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};
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uart2@1 {
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allwinner,pins = "PG15", "PG16", "PG17", "PG18";
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allwinner,pins = "PH5", "PH6", "PH7", "PH8";
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allwinner,function = "io_disabled";
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allwinner,muxsel = <0x7>;
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allwinner,drive = <0x1>;
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@@ -1539,7 +1539,7 @@
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};
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twi4@0 {
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allwinner,pins = "PG15", "PG16";
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allwinner,pins = "PH6", "PH7";
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allwinner,pname = "twi4_scl", "twi4_sda";
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allwinner,function = "twi4";
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allwinner,muxsel = <0x5>;
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@@ -1550,7 +1550,7 @@
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};
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twi4@1 {
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allwinner,pins = "PG15", "PG16";
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allwinner,pins = "PH6", "PH7";
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allwinner,function = "io_disabled";
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allwinner,muxsel = <0x7>;
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allwinner,drive = <0x1>;
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@@ -2565,7 +2565,7 @@
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phandle = <0x11a>;
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};
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uart@05000000 {
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uart0: uart@05000000 {
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compatible = "allwinner,sun50i-uart";
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device_type = "uart0";
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reg = <0x0 0x5000000 0x0 0x400>;
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@@ -2581,7 +2581,7 @@
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pinctrl-0 = <0x187>;
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};
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uart@05000400 {
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uart1: uart@05000400 {
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compatible = "allwinner,sun50i-uart";
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device_type = "uart1";
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reg = <0x0 0x5000400 0x0 0x400>;
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@@ -2597,7 +2597,7 @@
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phandle = <0x11c>;
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};
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uart@05000800 {
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uart2: uart@05000800 {
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compatible = "allwinner,sun50i-uart";
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device_type = "uart2";
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reg = <0x0 0x5000800 0x0 0x400>;
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@@ -2607,13 +2607,11 @@
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pinctrl-0 = <0x30>;
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pinctrl-1 = <0x31>;
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uart2_port = <0x2>;
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uart2_type = <0x4>;
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uart2_type = <0x2>;
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status = "disabled";
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linux,phandle = <0x11d>;
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phandle = <0x11d>;
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};
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uart@05000c00 {
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uart3: uart@05000c00 {
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compatible = "allwinner,sun50i-uart";
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device_type = "uart3";
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reg = <0x0 0x5000c00 0x0 0x400>;
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@@ -2629,7 +2627,7 @@
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phandle = <0x11e>;
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};
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uart@05001000 {
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uart4: uart@05001000 {
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compatible = "allwinner,sun50i-uart";
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device_type = "uart4";
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reg = <0x0 0x5001000 0x0 0x400>;
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@@ -2645,7 +2643,7 @@
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phandle = <0x11f>;
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};
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uart@05001400 {
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uart5: uart@05001400 {
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compatible = "allwinner,sun50i-uart";
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device_type = "uart5";
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reg = <0x0 0x5001400 0x0 0x400>;
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@@ -2661,7 +2659,7 @@
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phandle = <0x120>;
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};
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twi@0x05002000 {
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i2c0: twi@0x05002000 {
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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compatible = "allwinner,sun50i-twi";
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@@ -2678,7 +2676,7 @@
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phandle = <0x121>;
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};
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twi@0x05002400 {
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i2c1: twi@0x05002400 {
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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compatible = "allwinner,sun50i-twi";
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@@ -2695,7 +2693,7 @@
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phandle = <0x122>;
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};
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twi@0x05002800 {
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i2c2: twi@0x05002800 {
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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compatible = "allwinner,sun50i-twi";
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@@ -2712,7 +2710,7 @@
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phandle = <0x123>;
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};
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twi@0x05002c00 {
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i2c3: twi@0x05002c00 {
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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compatible = "allwinner,sun50i-twi";
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@@ -2729,7 +2727,7 @@
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phandle = <0x124>;
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};
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twi@0x05003000 {
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i2c4: twi@0x05003000 {
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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compatible = "allwinner,sun50i-twi";
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@@ -2742,11 +2740,9 @@
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pinctrl-0 = <0x48>;
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pinctrl-1 = <0x49>;
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status = "disabled";
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linux,phandle = <0x125>;
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phandle = <0x125>;
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};
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twi@0x07081400 {
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i2c5: twi@0x07081400 {
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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compatible = "allwinner,sun50i-twi";
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@@ -2760,78 +2756,149 @@
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pinctrl-1 = <0x4c>;
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status = "okay";
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no_suspend = <0x1>;
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linux,phandle = <0x126>;
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phandle = <0x126>;
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pmu {
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compatible = "x-powers,axp1530";
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pmu0: pmu {
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compatible = "x-powers,axp806";
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reg = <0x36>;
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wakeup-source;
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linux,phandle = <0x127>;
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phandle = <0x127>;
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standby_param {
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vcc-dram = <0x4>;
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linux,phandle = <0x128>;
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phandle = <0x128>;
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vcc-dram = <0x8>;
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};
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regulators {
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dcdc1 {
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regulator-name = "axp1530-dcdc1";
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regulator-min-microvolt = <0x7a120>;
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regulator-max-microvolt = <0x33e140>;
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regulator-step-delay-us = <0x19>;
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regulator-final-delay-us = <0x32>;
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reg_dcdc1: dcdca {
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regulator-name = "axp806-dcdca";
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <1520000>;
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regulator-step-delay-us = <25>;
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regulator-final-delay-us = <50>;
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regulator-always-on;
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linux,phandle = <0x129>;
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phandle = <0x129>;
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};
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dcdc2 {
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regulator-name = "axp1530-dcdc2";
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regulator-min-microvolt = <0x7a120>;
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regulator-max-microvolt = <0x177fa0>;
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regulator-step-delay-us = <0x19>;
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regulator-final-delay-us = <0x32>;
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regulator-ramp-delay = <0xc8>;
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regulator-always-on;
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linux,phandle = <0xd6>;
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phandle = <0xd6>;
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reg_dcdc2: dcdcb {
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regulator-name = "axp806-dcdcb";
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <2550000>;
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regulator-step-delay-us = <25>;
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regulator-final-delay-us = <50>;
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};
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dcdc3 {
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regulator-name = "axp1530-dcdc3";
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regulator-min-microvolt = <0x16e360>;
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regulator-max-microvolt = <0x16e360>;
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regulator-step-delay-us = <0x19>;
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regulator-final-delay-us = <0x32>;
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reg_dcdc3: dcdcc {
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regulator-name = "axp806-dcdcc";
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <1520000>;
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regulator-step-delay-us = <25>;
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regulator-final-delay-us = <50>;
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regulator-always-on;
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linux,phandle = <0x12a>;
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phandle = <0x12a>;
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};
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ldo1 {
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regulator-name = "axp1530-aldo1";
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regulator-min-microvolt = <0x1b7740>;
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regulator-max-microvolt = <0x1b7740>;
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regulator-step-delay-us = <0x19>;
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regulator-final-delay-us = <0x32>;
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reg_dcdc4: dcdcd {
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regulator-name = "axp806-dcdcd";
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <3300000>;
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regulator-step-delay-us = <25>;
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regulator-final-delay-us = <50>;
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regulator-always-on;
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linux,phandle = <0x68>;
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phandle = <0x68>;
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};
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ldo2 {
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regulator-name = "axp1530-dldo1";
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regulator-min-microvolt = <0x325aa0>;
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regulator-max-microvolt = <0x325aa0>;
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regulator-step-delay-us = <0x19>;
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regulator-final-delay-us = <0x32>;
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reg_dcdc5: dcdce {
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regulator-name = "axp806-dcdce";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-step-delay-us = <25>;
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regulator-final-delay-us = <50>;
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regulator-always-on;
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linux,phandle = <0x69>;
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phandle = <0x69>;
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};
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reg_aldo1: aldo1 {
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regulator-name = "axp806-aldo1";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-step-delay-us = <25>;
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regulator-final-delay-us = <50>;
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regulator-always-on;
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};
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reg_aldo2: aldo2 {
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regulator-name = "axp806-aldo2";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-step-delay-us = <25>;
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regulator-final-delay-us = <50>;
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regulator-always-on;
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};
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reg_aldo3: aldo3 {
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regulator-name = "axp806-aldo3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-step-delay-us = <25>;
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regulator-final-delay-us = <50>;
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regulator-always-on;
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};
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reg_bldo1: bldo1 {
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regulator-name = "axp806-bldo1";
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regulator-min-microvolt = <180000>;
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regulator-max-microvolt = <1800000>;
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regulator-step-delay-us = <25>;
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regulator-final-delay-us = <50>;
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regulator-always-on;
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};
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reg_bldo2: bldo2 {
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regulator-name = "axp806-bldo2";
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1900000>;
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regulator-step-delay-us = <25>;
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regulator-final-delay-us = <50>;
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regulator-always-on;
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};
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||||
reg_bldo3: bldo3 {
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regulator-name = "axp806-bldo3";
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regulator-min-microvolt = <700000>;
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||||
regulator-max-microvolt = <1900000>;
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regulator-step-delay-us = <25>;
|
||||
regulator-final-delay-us = <50>;
|
||||
};
|
||||
|
||||
reg_bldo4: bldo4 {
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||||
regulator-name = "axp806-bldo4";
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||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1900000>;
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||||
regulator-step-delay-us = <25>;
|
||||
regulator-final-delay-us = <50>;
|
||||
};
|
||||
|
||||
reg_cldo1: cldo1 {
|
||||
regulator-name = "axp806-cldo1";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-step-delay-us = <25>;
|
||||
regulator-final-delay-us = <50>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_cldo2: cldo2 {
|
||||
regulator-name = "axp806-cldo2";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <4200000>;
|
||||
regulator-step-delay-us = <25>;
|
||||
regulator-final-delay-us = <50>;
|
||||
};
|
||||
|
||||
reg_cldo3: cldo3 {
|
||||
regulator-name = "axp806-cldo3";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-step-delay-us = <25>;
|
||||
regulator-final-delay-us = <50>;
|
||||
};
|
||||
|
||||
reg_sw: sw {
|
||||
regulator-name = "axp806-sw";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -3384,8 +3451,6 @@
|
||||
ctl-spec-caps = <0x8>;
|
||||
vmmc-supply = <0x69>;
|
||||
vqmmc-supply = <0x68>;
|
||||
linux,phandle = <0x145>;
|
||||
phandle = <0x145>;
|
||||
};
|
||||
|
||||
sdmmc@04020000 {
|
||||
@@ -3402,24 +3467,18 @@
|
||||
max-frequency = <0x8f0d180>;
|
||||
bus-width = <0x4>;
|
||||
cd-gpios = <0x53 0x5 0x6 0x6 0x1 0x3 0xffffffff>;
|
||||
cap-sd-highspeed;
|
||||
//cap-sd-highspeed;
|
||||
cap-wait-while-busy;
|
||||
no-sdio;
|
||||
no-mmc;
|
||||
sunxi-power-save-mode;
|
||||
status = "okay";
|
||||
cd-used-24M;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-ddr50;
|
||||
sd-uhs-sdr104;
|
||||
//sd-uhs-sdr50;
|
||||
//sd-uhs-ddr50;
|
||||
//sd-uhs-sdr104;
|
||||
ctl-spec-caps = <0x8>;
|
||||
vmmc-supply = <0x69>;
|
||||
vqmmc33sw-supply = <0x69>;
|
||||
vdmmc33sw-supply = <0x69>;
|
||||
vqmmc18sw-supply = <0x68>;
|
||||
vdmmc18sw-supply = <0x68>;
|
||||
linux,phandle = <0x146>;
|
||||
phandle = <0x146>;
|
||||
//vdmmc-supply = <®_dcdc5>;
|
||||
};
|
||||
|
||||
sdmmc@04021000 {
|
||||
@@ -4434,13 +4493,6 @@
|
||||
dldo1_vol = <0xf4f24>;
|
||||
};
|
||||
|
||||
axp1530_power_sply {
|
||||
device_type = "axp1530_power_sply";
|
||||
dcdc2_vol = <0xf4628>;
|
||||
aldo1_vol = <0xf4948>;
|
||||
dldo1_vol = <0xf4f24>;
|
||||
};
|
||||
|
||||
axp806_power_sply {
|
||||
device_type = "axp806_power_sply";
|
||||
dcdce_vol = <0xf4f24>;
|
||||
@@ -4448,6 +4500,7 @@
|
||||
aldo1_vol = <0xf4f24>;
|
||||
bldo1_vol = <0xf4948>;
|
||||
bldo2_vol = <0xf4948>;
|
||||
cldo1_vol = <0xf4948>;
|
||||
};
|
||||
|
||||
card_boot {
|
||||
|
||||
@@ -223,39 +223,37 @@ select_gpio3 =
|
||||
;
|
||||
;*****************************************************************************
|
||||
[dram_para]
|
||||
|
||||
dram_clk = 720
|
||||
dram_type = 3
|
||||
dram_dx_odt = 0x08080808
|
||||
dram_dx_dri = 0x0e0e0e0e
|
||||
dram_ca_dri = 0x0e0e
|
||||
dram_odt_en = 1
|
||||
dram_para1 = 0x30FA
|
||||
dram_para2 = 0x1000
|
||||
dram_mr0 = 0x840
|
||||
dram_mr1 = 0x4
|
||||
dram_mr2 = 0x8
|
||||
dram_mr3 = 0x0
|
||||
dram_mr4 = 0x0
|
||||
dram_mr5 = 0x0
|
||||
dram_mr6 = 0x0
|
||||
dram_mr11 = 0x0
|
||||
dram_mr12 = 0x0
|
||||
dram_mr13 = 0x0
|
||||
dram_mr14 = 0x0
|
||||
dram_mr16 = 0x0
|
||||
dram_mr17 = 0x0
|
||||
dram_mr22 = 0x0
|
||||
dram_tpr0 = 0x0
|
||||
dram_tpr1 = 0x0
|
||||
dram_tpr2 = 0x0
|
||||
dram_tpr3 = 0x0
|
||||
dram_tpr6 = 0x33808080
|
||||
dram_tpr10 = 0x00f83438
|
||||
dram_tpr11 = 0x0
|
||||
dram_tpr12 = 0x0
|
||||
dram_tpr13 = 0x40
|
||||
|
||||
dram_clk = 672
|
||||
dram_type = 7
|
||||
dram_dx_odt = 0x06060606
|
||||
dram_dx_dri = 0x0d0d0d0d
|
||||
dram_ca_dri = 0x0d0d
|
||||
dram_odt_en = 0x9988eeee
|
||||
dram_para1 = 0x30fa
|
||||
dram_para2 = 0x1000
|
||||
dram_mr0 = 0x0
|
||||
dram_mr1 = 0xc3
|
||||
dram_mr2 = 0x6
|
||||
dram_mr3 = 0x1
|
||||
dram_mr4 = 0x0
|
||||
dram_mr5 = 0x0
|
||||
dram_mr6 = 0x0
|
||||
dram_mr11 = 0x0
|
||||
dram_mr12 = 0x0
|
||||
dram_mr13 = 0x0
|
||||
dram_mr14 = 0x0
|
||||
dram_mr16 = 0x0
|
||||
dram_mr17 = 0x0
|
||||
dram_mr22 = 0x0
|
||||
dram_tpr0 = 0x0
|
||||
dram_tpr1 = 0x0
|
||||
dram_tpr2 = 0x0
|
||||
dram_tpr3 = 0x0
|
||||
dram_tpr6 = 0x2fb28080
|
||||
dram_tpr10 = 0x402f4429
|
||||
dram_tpr11 = 0x0d0e0a09
|
||||
dram_tpr12 = 0x0c0d0a0b
|
||||
dram_tpr13 = 0xc60
|
||||
|
||||
[dram_para1]
|
||||
|
||||
|
||||
@@ -37,11 +37,13 @@ dragonboard_test= 0
|
||||
dcdc2_vol = 1001000
|
||||
aldo1_vol = 1001800
|
||||
dldo1_vol = 1003300
|
||||
cldo1_vol = 1001800
|
||||
|
||||
[axp1530_power_sply]
|
||||
dcdc2_vol = 1001000
|
||||
aldo1_vol = 1001800
|
||||
dldo1_vol = 1003300
|
||||
cldo1_vol = 1001800
|
||||
|
||||
[axp806_power_sply]
|
||||
dcdce_vol = 1003300
|
||||
@@ -49,6 +51,7 @@ dcdce_vol = 1003300
|
||||
aldo1_vol = 1003300
|
||||
bldo1_vol = 1001800
|
||||
bldo2_vol = 1001800
|
||||
cldo1_vol = 1001800
|
||||
|
||||
[card_boot]
|
||||
logical_start = 40960
|
||||
@@ -220,39 +223,37 @@ select_gpio3 =
|
||||
;
|
||||
;*****************************************************************************
|
||||
[dram_para]
|
||||
|
||||
dram_clk = 720
|
||||
dram_type = 3
|
||||
dram_dx_odt = 0x08080808
|
||||
dram_dx_dri = 0x0e0e0e0e
|
||||
dram_ca_dri = 0x0e0e
|
||||
dram_odt_en = 1
|
||||
dram_para1 = 0x30FA
|
||||
dram_para2 = 0x1000
|
||||
dram_mr0 = 0x840
|
||||
dram_mr1 = 0x4
|
||||
dram_mr2 = 0x8
|
||||
dram_mr3 = 0x0
|
||||
dram_mr4 = 0x0
|
||||
dram_mr5 = 0x0
|
||||
dram_mr6 = 0x0
|
||||
dram_mr11 = 0x0
|
||||
dram_mr12 = 0x0
|
||||
dram_mr13 = 0x0
|
||||
dram_mr14 = 0x0
|
||||
dram_mr16 = 0x0
|
||||
dram_mr17 = 0x0
|
||||
dram_mr22 = 0x0
|
||||
dram_tpr0 = 0x0
|
||||
dram_tpr1 = 0x0
|
||||
dram_tpr2 = 0x0
|
||||
dram_tpr3 = 0x0
|
||||
dram_tpr6 = 0x33808080
|
||||
dram_tpr10 = 0x00f83438
|
||||
dram_tpr11 = 0x0
|
||||
dram_tpr12 = 0x0
|
||||
dram_tpr13 = 0x40
|
||||
|
||||
dram_clk = 792
|
||||
dram_type = 8
|
||||
dram_dx_odt = 0x07070707
|
||||
dram_dx_dri = 0x0e0e0e0e
|
||||
dram_ca_dri = 0x0e0e
|
||||
dram_odt_en = 0xaaaaeeee
|
||||
dram_para1 = 0x30fa
|
||||
dram_para2 = 0x0000
|
||||
dram_mr0 = 0x0
|
||||
dram_mr1 = 0x34
|
||||
dram_mr2 = 0x1b
|
||||
dram_mr3 = 0x33
|
||||
dram_mr4 = 0x3
|
||||
dram_mr5 = 0x0
|
||||
dram_mr6 = 0x0
|
||||
dram_mr11 = 0x4
|
||||
dram_mr12 = 0x72
|
||||
dram_mr13 = 0x0
|
||||
dram_mr14 = 0x9
|
||||
dram_mr16 = 0x0
|
||||
dram_mr17 = 0x0
|
||||
dram_mr22 = 0x24
|
||||
dram_tpr0 = 0x0
|
||||
dram_tpr1 = 0x0
|
||||
dram_tpr2 = 0x0
|
||||
dram_tpr3 = 0x0
|
||||
dram_tpr6 = 0x35808080
|
||||
dram_tpr10 = 0x402f6663
|
||||
dram_tpr11 = 0x36363535
|
||||
dram_tpr12 = 0x10101110
|
||||
dram_tpr13 = 0x2080C60
|
||||
|
||||
[dram_para1]
|
||||
|
||||
|
||||
Reference in New Issue
Block a user