Add linuxpg

2026-11-05 15:27:21 +07:00 · 2023-04-10 09:19:18 +08:00
parent e9c639fc9e
commit 4b897b01ff
139 changed files with 6557 additions and 0 deletions
--- a/external/cache/sources/linuxpg/8117EF.cfg
+++ b/external/cache/sources/linuxpg/8117EF.cfg
@@ -0,0 +1,82 @@
+NODEID = 00 E0 4C 68 00 01
+;ENDID = 00 E0 4C 68 FF FF
+;VID = 10 EC
+;DID = 81 68
+SVID = 10 EC
+SMID = 01 23
+
+;Do not change following parameters without Realtek approval
+;CONFIG0 = 00
+;CONFIG1 = CF
+CONFIGx = 3C
+;CONFIG3 = 60
+;CONFIG4 = 14
+;CONFIG5 = 02
+;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1
+;CONFIG5 = 0A
+;CONFIG7 = 07
+;PMC = C3 FF
+;ROMBAR = 00
+;LEDCFG = High-Byte(19H) Low-Byte(18H)
+;LEDCFG = 0C A9
+;ROMCONF = 3F
+;Bit 7-6    Boot Protocol
+;           00 ==> PXE protocol
+;           01 ==> RPL protocol
+;Bit 5-4    Boot order (method)
+;           00 ==> ROM disable
+;           01 ==> Int 18h
+;           10 ==> Int 19h
+;           11 ==> PnP/BEV(BBS)
+;Bit 3      Show Config Message
+;           0 ==> Enable
+;           1 ==> Disable
+;Bit 2      Shift+F10 Menu Entry
+;           0 ==> Enable
+;           1 ==> Disable
+;Bit 1-0    Show Config Time
+;           00 ==> 3 Seconds
+;           01 ==> 5 Seconds
+;           10 ==> 1 Seconds
+;           11 ==> 0 Second
+
+;Serial Number in PCI Config Space
+SN = 00 E0 4C 68 00 00 00 01
+
+;LANCFG
+;BIT 0:LAN Disable     BIT 1:PHY Disable    BIT 2:Link OK
+;BIT 31:Clear LANCFG
+;LANCFG = 00 00 00 00
+
+;Link Capability
+;PHYGBCR = 02 00
+;PHYANAR = 01 E1
+
+;LEDSUBCFG
+;Please make sure CONFIGX LED low power bit enabled
+;(IO reg offset 0x53 bit 2 set to 0) before modifying LEDSUBCFG
+;BIT 0:LED0 Low Power Enable in D3cold    BIT 1:LED1 Low Power Enable in D3cold
+;BIT 2:LED2 Low Power Enable in D3cold
+;BIT 3:LED0 Preboot Enable    BIT 4: LED1 Preboot Enable
+;BIT 5:LED2 Preboot Enable
+;LEDSUBCFG = 00
+
+;Disable: 00, Enable: 01
+;UPHY Reset USB Bypass mode
+;USBBYPASSMODE = 00
+;UPS mode power saving
+;UPSMODEPWRSAVING = 00
+;Secure boot
+;SECUREBOOT = 01
+
+;EHCI PMC
+;Enable EHCI PME_D3cold & PME_D3hot support in PMC
+EHCIPMC = C3 FF
+
+;PCIE Link Capability
+;LINKPCIEGEN = 11
+
+;Disable multi-function X
+;DISABLEFUNCX = 00
+VERSION = 1.031
+