diff --git a/external/cache/sources/linuxpg/68DPSPI.cfg b/external/cache/sources/linuxpg/68DPSPI.cfg new file mode 100644 index 0000000..b9210e2 --- /dev/null +++ b/external/cache/sources/linuxpg/68DPSPI.cfg @@ -0,0 +1,39 @@ +; RTL8168DP Configuration file +; 2009/04/01 +; +; Out of band MAC ID +NODEID = 00 E0 4C 68 00 20 +; +; user login name +USERNAME = Administrator +; user password, password length has to be 16 bytes +; default password 'Realtek' + PASSWORD = 52 65 61 6c 74 65 6b 00 00 00 00 00 00 00 00 00 +; operation role +; Administrator : 01 +; Operator: 02 +; Guest : 03 +ROLE = 01 +; OOB IP address +IP = 192.168.0.10 +; OOB subnet mask +SUBNET = 255.255.255.0 +; OOB gateway IP address +GATEWAY = 192.168.0.254 +; OOB DNS server ip address +DNS = 192.168.0.1 +; ASP console IP address +ASFIP = 192.168.0.3 +; ASF function setting +; enable : ON +; disable : OFF +ASFON = ON +; IPV4 DHCP setting +; enable : ON +; disable : OFF +DHCPIPV4 = OFF +HOSTNAME = hostnameho +; hostname suffix +; enable : ON +; disable : OFF +HN_SUFFIX = ON diff --git a/external/cache/sources/linuxpg/68EPSPI.cfg b/external/cache/sources/linuxpg/68EPSPI.cfg new file mode 100644 index 0000000..1ac9c28 --- /dev/null +++ b/external/cache/sources/linuxpg/68EPSPI.cfg @@ -0,0 +1,36 @@ +; RTL8168EP Configuration file +; 2018/03/30 +; +; user login name +USERNAME = Administrator +; user password, password length has to be 16 bytes +; default password 'Realtek' +PASSWORD = 52 65 61 6c 74 65 6b 00 00 00 00 00 00 00 00 00 +; operation role +; Administrator : 01 +; Operator: 02 +; Guest : 03 +; ROLE = 01 +; OOB IP address +IP = 192.168.0.10 +; OOB subnet mask +SUBNET = 255.255.255.0 +; OOB gateway IP address +GATEWAY = 192.168.0.254 +; OOB DNS server ip address +; DNS = 192.168.0.1 +; ASP console IP address +; ASFIP = 192.168.0.3 +; ASF function setting +; enable : ON +; disable : OFF +; ASFON = ON +; IPV4 DHCP setting +; enable : ON +; disable : OFF +; DHCPIPV4 = OFF +HOSTNAME = DASHOOB +HN_SUFFIX = ON +;SARP_ADDR = C8 +;USB_OTG = OFF +;WEBPAGE = OFF \ No newline at end of file diff --git a/external/cache/sources/linuxpg/68EPSPIK.bin b/external/cache/sources/linuxpg/68EPSPIK.bin new file mode 100644 index 0000000..92acd73 Binary files /dev/null and b/external/cache/sources/linuxpg/68EPSPIK.bin differ diff --git a/external/cache/sources/linuxpg/68FPHSPI.cfg b/external/cache/sources/linuxpg/68FPHSPI.cfg new file mode 100644 index 0000000..89a73bd --- /dev/null +++ b/external/cache/sources/linuxpg/68FPHSPI.cfg @@ -0,0 +1,36 @@ +; RTL8168FPH Configuration file +; 2009/04/01 +; +; user login name +USERNAME = Administrator +; user password, password length has to be 16 bytes +; default password 'Realtek' +PASSWORD = 52 65 61 6c 74 65 6b 00 00 00 00 00 00 00 00 00 +; operation role +; Administrator : 01 +; Operator: 02 +; Guest : 03 +;ROLE = 01 +; OOB IP address +IP = 192.168.0.10 +; OOB subnet mask +SUBNET = 255.255.255.0 +; OOB gateway IP address +GATEWAY = 192.168.0.254 +; OOB DNS server ip address +;DNS = 192.168.0.1 +; ASP console IP address +;ASFIP = 192.168.0.3 +; ASF function setting +; enable : ON +; disable : OFF +;ASFON = ON +; IPV4 DHCP setting +; enable : ON +; disable : OFF +; DHCPIPV4 = OFF +HOSTNAME = DASHOOB +HN_SUFFIX = ON +;SARP_ADDR = C8 +;USB_OTG = OFF +;VNC_CONFIG = ORIGIN/PINCODE diff --git a/external/cache/sources/linuxpg/68FPSPI.cfg b/external/cache/sources/linuxpg/68FPSPI.cfg new file mode 100644 index 0000000..17d4947 --- /dev/null +++ b/external/cache/sources/linuxpg/68FPSPI.cfg @@ -0,0 +1,37 @@ +; RTL8168FP Configuration file +; 2009/04/01 +; +; user login name +USERNAME = Administrator +; user password, password length has to be 16 bytes +; default password 'Realtek' +PASSWORD = 52 65 61 6c 74 65 6b 00 00 00 00 00 00 00 00 00 +; operation role +; Administrator : 01 +; Operator: 02 +; Guest : 03 +;ROLE = 01 +; OOB IP address +IP = 192.168.0.10 +; OOB subnet mask +SUBNET = 255.255.255.0 +; OOB gateway IP address +GATEWAY = 192.168.0.254 +; OOB DNS server ip address +;DNS = 192.168.0.1 +; ASP console IP address +;ASFIP = 192.168.0.3 +; ASF function setting +; enable : ON +; disable : OFF +;ASFON = ON +; IPV4 DHCP setting +; enable : ON +; disable : OFF +;DHCPIPV4 = OFF +HOSTNAME = DASHOOB +HN_SUFFIX = ON +;SARP_ADDR = C8 +;USB_OTG = OFF +;VNC_CONFIG = ORIGIN/PINCODE +;WEBPAGE = OFF \ No newline at end of file diff --git a/external/cache/sources/linuxpg/8100E.cfg b/external/cache/sources/linuxpg/8100E.cfg new file mode 100644 index 0000000..94c9d05 --- /dev/null +++ b/external/cache/sources/linuxpg/8100E.cfg @@ -0,0 +1,29 @@ +NODEID = 00 E0 4C 36 00 01 +;ENDID = 00 E0 4C 36 FF FF +VID = 10 EC +DID = 81 36 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +CONFIG0 = 00 +CONFIG1 = CF +CONFIGx = 00 +CONFIG3 = 60 +CONFIG4 = 00 +CONFIG5 = 03 +PMC = C2 F7 +ROMBAR = 00 +ROMCONF = 3F + +;Serial Number in PCI Config Space +SN = 00 E0 4C 36 00 00 00 01 + +;PCI-E Parameter +PCIE1= 04 01 42 63 7E 00 00 04 +PCIE2= FF FF FF FF FF FF 1F +PCIE3= 00 47 10 F0 F0 01 BF 01 00 00 60 00 00 +;0AH,0BH,18H,1A~1EH +;28H~2EH +;30H~31H, 34H~3EH +VERSION = 1.031 diff --git a/external/cache/sources/linuxpg/8100E.map b/external/cache/sources/linuxpg/8100E.map new file mode 100644 index 0000000..0b2d36a --- /dev/null +++ b/external/cache/sources/linuxpg/8100E.map @@ -0,0 +1,8 @@ +29 81 EC 10 23 01 EC 10 36 81 04 01 00 60 00 E0 +4C 36 00 00 00 CF C2 F7 42 00 63 7E 00 00 04 03 +00 E0 4C 36 00 00 00 01 FF FF FF FF FF FF 1F 00 +00 47 D5 B5 10 F0 F0 01 BF 01 00 00 60 00 00 3F +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ No newline at end of file diff --git a/external/cache/sources/linuxpg/8101E.cfg b/external/cache/sources/linuxpg/8101E.cfg new file mode 100644 index 0000000..cbd5efb --- /dev/null +++ b/external/cache/sources/linuxpg/8101E.cfg @@ -0,0 +1,29 @@ +NODEID = 00 E0 4C 36 00 01 +;ENDID = 00 E0 4C 36 FF FF +VID = 10 EC +DID = 81 36 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +CONFIG0 = 00 +CONFIG1 = CF +CONFIGx = 20 +CONFIG3 = 60 +CONFIG4 = 00 +CONFIG5 = 03 +PMC = C2 F7 +ROMBAR = 00 +ROMCONF = 3F + +;Serial Number in PCI Config Space +SN = 00 E0 4C 36 00 00 00 01 + +;PCI-E Parameter +PCIE1= 04 01 42 60 7E 00 00 04 +PCIE2= FF FF FF FF FF FF 1F +PCIE3= 00 47 30 F0 F0 00 2F 00 00 00 60 00 00 +;0AH,0BH,18H,1A~1E +;28H~2EH +;30H~31H, 34H~3EH +VERSION = 1.031 diff --git a/external/cache/sources/linuxpg/8101E.map b/external/cache/sources/linuxpg/8101E.map new file mode 100644 index 0000000..7c9e3f7 --- /dev/null +++ b/external/cache/sources/linuxpg/8101E.map @@ -0,0 +1,8 @@ +29 81 EC 10 36 81 EC 10 23 01 04 01 20 60 00 E0 +4C 36 00 00 00 CF C2 F7 42 00 60 7E 00 00 04 03 +00 E0 4C 36 00 00 00 01 FF FF FF FF FF FF 1F 00 +00 47 5A E1 30 F0 F0 00 2F 00 00 00 60 00 00 3F +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ No newline at end of file diff --git a/external/cache/sources/linuxpg/8102E.cfg b/external/cache/sources/linuxpg/8102E.cfg new file mode 100644 index 0000000..a582f6a --- /dev/null +++ b/external/cache/sources/linuxpg/8102E.cfg @@ -0,0 +1,56 @@ +NODEID = 00 E0 4C 36 00 01 +;ENDID = 00 E0 4C 36 FF FF +VID = 10 EC +DID = 81 36 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +CONFIG0 = 00 +CONFIG1 = 0F +CONFIGx = 3C +CONFIG3 = 62 +CONFIG4 = 14 +CONFIG5 = 02 +PMC = C3 FF +ROMBAR = 00 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 36 00 00 00 01 + +;PCI-E Parameter +C_PCIE0 = 04 01 +;0AH~0BH +C_PCIE1 = c1 86 80 02 00 00 11 3c 07 00 10 20 +;1AH~25H +C_PCIE2 = 76 00 63 01 01 FF 27 AA 03 02 20 +;26H~2BH 2DH~31H +C_PCIE3 = 80 02 00 20 10 00 21 00 10 00 21 00 00 80 +;34H~3EH 40H~42H +C_PCIE4 = 80 00 20 00 00 00 +;46H~49H 52~53H +C_EPHY = 70 22 1D AF 6B 35 00 +;43H~45H 54H~57H +VERSION = 1.031 + + diff --git a/external/cache/sources/linuxpg/8102E.map b/external/cache/sources/linuxpg/8102E.map new file mode 100644 index 0000000..b08e373 --- /dev/null +++ b/external/cache/sources/linuxpg/8102E.map @@ -0,0 +1,32 @@ +29 81 EC 10 36 81 EC 10 23 01 04 01 3C 62 00 E0 +4C 36 00 00 00 0F C3 FF 14 02 C1 86 80 02 00 00 +11 3C 07 00 10 20 76 00 63 01 01 FF 00 27 AA 03 +02 20 38 AC 80 02 00 20 10 00 21 00 10 00 21 3F +00 00 80 70 22 1D 80 00 20 00 E0 00 36 4C 00 00 +01 00 00 00 AF 6B 35 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/external/cache/sources/linuxpg/8102EF.cfg b/external/cache/sources/linuxpg/8102EF.cfg new file mode 100644 index 0000000..c4dc54a --- /dev/null +++ b/external/cache/sources/linuxpg/8102EF.cfg @@ -0,0 +1,44 @@ +NODEID = 00 E0 4C 36 00 01 +;ENDID = 00 E0 4C 36 FF FF +;VID = 10 EC +;DID = 81 36 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +CONFIG0 = 00 +CONFIG1 = 0F +;CONFIGx = 3C +CONFIG3 = 62 +CONFIG4 = 14 +;CONFIG5 = 02 +PMC = C3 FF +ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +LEDCFG = 00 00 +;Prefetchable memory access. Non-Prefetchable set to 04H, Prefetchable set to 0CH +PREFETCHABLE = 04 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 36 00 00 00 01 +VERSION = 1.031 diff --git a/external/cache/sources/linuxpg/8103E.cfg b/external/cache/sources/linuxpg/8103E.cfg new file mode 100644 index 0000000..462ab40 --- /dev/null +++ b/external/cache/sources/linuxpg/8103E.cfg @@ -0,0 +1,56 @@ +NODEID = 00 E0 4C 36 00 01 +;ENDID = 00 E0 4C 36 FF FF +VID = 10 EC +DID = 81 36 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +CONFIG0 = 00 +CONFIG1 = 0F +CONFIGx = 3C +CONFIG3 = 60 +CONFIG4 = 14 +CONFIG5 = 02 +PMC = C3 FF +ROMBAR = 00 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 36 00 00 00 01 + +;PCI-E Parameter +C_PCIE0 = 04 01 +;0AH~0BH +C_PCIE1 = c1 86 80 02 00 00 11 3c 07 00 10 20 +;1AH~25H +C_PCIE2 = 76 00 63 01 01 FF 27 AA 03 02 20 +;26H~2BH 2DH~31H +C_PCIE3 = 80 02 00 20 10 00 21 00 10 00 21 00 00 80 +;34H~3EH 40H~42H +C_PCIE4 = 80 00 20 00 00 00 +;46H~49H 52~53H +C_EPHY = 71 22 98 AF 6B 39 35 +;43H~45H 54H~57H +VERSION = 1.031 + + diff --git a/external/cache/sources/linuxpg/8103E.map b/external/cache/sources/linuxpg/8103E.map new file mode 100644 index 0000000..e366eac --- /dev/null +++ b/external/cache/sources/linuxpg/8103E.map @@ -0,0 +1,32 @@ +29 81 EC 10 36 81 EC 10 23 01 04 01 3C 60 00 E0 +4C 36 00 00 00 0F C3 FF 14 02 C1 86 80 02 00 00 +11 3C 07 00 10 20 76 00 63 01 01 FF 00 27 AA 03 +02 20 38 AC 80 02 00 20 10 00 21 00 10 00 21 3F +00 00 80 71 22 98 80 00 20 00 E0 00 36 4C 00 00 +01 00 00 00 AF 6B 39 35 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/external/cache/sources/linuxpg/8103EF.cfg b/external/cache/sources/linuxpg/8103EF.cfg new file mode 100644 index 0000000..4917442 --- /dev/null +++ b/external/cache/sources/linuxpg/8103EF.cfg @@ -0,0 +1,47 @@ +NODEID = 00 E0 4C 36 00 01 +;ENDID = 00 E0 4C 36 FF FF +;VID = 10 EC +;DID = 81 36 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +CONFIG0 = 00 +CONFIG1 = 0F +;CONFIGx = 3C +CONFIG3 = 60 +CONFIG4 = 14 +;CONFIG5 = 02 +PMC = C3 FF +ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +LEDCFG = 00 00 +;Prefetchable memory access. Non-Prefetchable set to 04H, Prefetchable set to 0CH +PREFETCHABLE = 04 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;EPHY = Address HIGH_BYTE LOW_BYTE ... +;EPHY = 03 00 FB + +;Serial Number in PCI Config Space +SN = 00 E0 4C 36 00 00 00 01 +VERSION = 1.031 diff --git a/external/cache/sources/linuxpg/8103EL.cfg b/external/cache/sources/linuxpg/8103EL.cfg new file mode 100644 index 0000000..a376d8d --- /dev/null +++ b/external/cache/sources/linuxpg/8103EL.cfg @@ -0,0 +1,56 @@ +NODEID = 00 E0 4C 36 00 01 +;EndID = 00 E0 4C 36 FF FF +VID = 10 EC +DID = 81 36 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +CONFIG0 = 00 +CONFIG1 = 0F +CONFIGx = 3C +CONFIG3 = 62 +CONFIG4 = 14 +CONFIG5 = 82 +PMC = C3 FF +ROMBAR = 00 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 36 00 00 00 01 + +;PCI-E Parameter +C_PCIE0 = 04 01 +;0AH~0BH +C_PCIE1 = c1 86 80 02 00 00 11 3c 07 00 10 20 +;1AH~25H +C_PCIE2 = 76 00 63 01 01 FF 27 AA 03 02 20 +;26H~2BH 2DH~31H +C_PCIE3 = 80 02 00 20 10 00 21 00 10 00 21 00 00 80 +;34H~3EH 40H~42H +C_PCIE4 = 80 00 20 00 00 00 +;46H~49H 52~53H +C_EPHY = 71 22 98 AF 6B 39 35 +;43H~45H 54H~57H +VERSION = 1.031 + + diff --git a/external/cache/sources/linuxpg/8103EL.map b/external/cache/sources/linuxpg/8103EL.map new file mode 100644 index 0000000..332ce77 --- /dev/null +++ b/external/cache/sources/linuxpg/8103EL.map @@ -0,0 +1,8 @@ +29 81 EC 10 36 81 EC 10 23 01 04 01 3C 62 00 E0 +4C 36 00 01 00 0F C3 FF 14 82 C1 86 80 02 00 00 +11 3C 07 00 10 20 76 00 63 01 01 FF 00 27 AA 03 +02 20 54 9E 80 02 00 20 10 00 21 00 10 00 21 3F +00 00 80 71 22 98 80 00 20 00 E0 00 36 4C 00 00 +01 00 00 00 AF 6B 39 35 FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF \ No newline at end of file diff --git a/external/cache/sources/linuxpg/8103ELEF.cfg b/external/cache/sources/linuxpg/8103ELEF.cfg new file mode 100644 index 0000000..945a775 --- /dev/null +++ b/external/cache/sources/linuxpg/8103ELEF.cfg @@ -0,0 +1,47 @@ +NODEID = 00 E0 4C 36 00 01 +;ENDID = 00 E0 4C 36 FF FF +;VID = 10 EC +;DID = 81 36 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +CONFIG0 = 00 +CONFIG1 = 0F +;CONFIGx = 3C +CONFIG3 = 62 +CONFIG4 = 14 +CONFIG5 = 82 +PMC = C3 FF +ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +LEDCFG = 00 00 +;Prefetchable memory access. Non-Prefetchable set to 04H, Prefetchable set to 0CH +PREFETCHABLE = 04 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;EPHY = Address HIGH_BYTE LOW_BYTE ... +;EPHY = 03 00 FB + +;Serial Number in PCI Config Space +SN = 00 E0 4C 36 00 00 00 01 +VERSION = 1.031 diff --git a/external/cache/sources/linuxpg/8104E.cfg b/external/cache/sources/linuxpg/8104E.cfg new file mode 100644 index 0000000..945f7cf --- /dev/null +++ b/external/cache/sources/linuxpg/8104E.cfg @@ -0,0 +1,60 @@ +NODEID = 00 E0 4C 37 00 01 +;ENDID = 00 E0 4C 37 FF FF +VID = 10 EC +DID = 81 37 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +CONFIG0 = 00 +CONFIG1 = CF +CONFIGx = 9C +CONFIG3 = 62 +CONFIG4 = 04 +CONFIG5 = 02 +PMC = C3 FF +ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +LEDCFG = 98 CA +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 37 00 00 00 01 + +;PCI-E Parameter (Do not change without Realtek approval) +C_PCIE0 = 04 01 +;0AH~0BH +C_PCIE1 = c0 8C 80 02 00 00 11 3c 07 00 10 20 +;1AH~25H +C_PCIE2 = 76 00 63 01 01 FF 27 AA 03 02 20 +;26H~2BH 2DH~31H +C_PCIE3 = 80 02 00 20 04 40 20 00 04 40 20 00 00 20 +;34H~3EH 40H~42H +C_PCIE4 = 60 00 0A 00 00 00 +;46H~49H 52~53H +C_EPHY = E1 22 B5 B2 73 75 EA +;43H~45H 54H~57H +D_EPHY = 87 75 7A 39 +;58H~5BH +VERSION = 1.031 + + diff --git a/external/cache/sources/linuxpg/8104E.map b/external/cache/sources/linuxpg/8104E.map new file mode 100644 index 0000000..05d65e7 --- /dev/null +++ b/external/cache/sources/linuxpg/8104E.map @@ -0,0 +1,32 @@ +29 81 EC 10 37 81 EC 10 23 01 04 01 9C 62 00 E0 +4C 37 00 01 00 CF C3 FF 04 02 C0 8C 80 02 00 00 +11 3C 07 00 10 20 76 00 63 01 01 FF 00 27 AA 03 +02 20 99 A5 80 02 00 20 04 40 20 00 04 40 20 3F +00 00 20 E1 22 B5 60 00 0A 00 E0 00 68 4C 00 00 +01 00 00 00 B2 73 75 EA 87 75 7A 39 CA 98 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/external/cache/sources/linuxpg/8104EF.cfg b/external/cache/sources/linuxpg/8104EF.cfg new file mode 100644 index 0000000..ba81998 --- /dev/null +++ b/external/cache/sources/linuxpg/8104EF.cfg @@ -0,0 +1,46 @@ +NODEID = 00 E0 4C 37 00 01 +;ENDID = 00 E0 4C 37 FF FF +VID = 10 EC +DID = 81 37 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +CONFIG0 = 00 +CONFIG1 = CF +CONFIGx = 9C +CONFIG3 = 62 +CONFIG4 = 04 +CONFIG5 = 02 +PMC = C3 FF +ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +LEDCFG = 98 CA +;Prefetchable memory access. Non-Prefetchable set to 04H, Prefetchable set to 0CH +PREFETCHABLE = 04 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 37 00 00 00 01 +VERSION = 1.031 + + diff --git a/external/cache/sources/linuxpg/8105E.cfg b/external/cache/sources/linuxpg/8105E.cfg new file mode 100644 index 0000000..f6a309e --- /dev/null +++ b/external/cache/sources/linuxpg/8105E.cfg @@ -0,0 +1,65 @@ +NODEID = 00 E0 4C 36 00 01 +;ENDID = 00 E0 4C 36 FF FF +VID = 10 EC +DID = 81 36 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +CONFIG0 = 00 +CONFIG1 = 0F +CONFIGx = 1C +CONFIG3 = 60 +CONFIG4 = 14 +CONFIG5 = 82 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 8A + +PMC = C3 FF +ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +LEDCFG = 98 CA +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 36 00 00 00 01 + +;PCI-E Parameter (Do not change without Realtek approval) +C_PCIE0 = 04 01 +;0AH~0BH +C_PCIE1 = C0 8C 80 02 00 00 11 3C 07 00 10 20 +;1AH~25H +C_PCIE2 = 76 00 63 01 01 FF 13 AA 03 02 20 +;26H~2BH 2DH~31H +C_PCIE3 = 80 02 00 20 04 40 20 00 04 40 20 00 00 20 +;34H~3EH 40H~42H +C_PCIE4 = 60 00 0A 00 00 00 +;46H~49H 52~53H +C_EPHY = B9 6A 98 AC 6B 75 80 +;43H~45H 54H~57H +D_EPHY = 8D 75 7B 01 +;58H~5BH +E0_EPHY = 48 +;5EH +VERSION = 1.031 + + diff --git a/external/cache/sources/linuxpg/8105E.map b/external/cache/sources/linuxpg/8105E.map new file mode 100644 index 0000000..4e6007e --- /dev/null +++ b/external/cache/sources/linuxpg/8105E.map @@ -0,0 +1,8 @@ +29 81 EC 10 36 81 EC 10 23 01 04 01 1C 60 00 E0 +4C 36 00 01 00 0F C3 FF 14 82 C0 8C 80 02 00 00 +11 3C 07 00 10 20 76 76 00 63 01 01 FF 13 AA 03 +02 20 99 A5 80 02 00 20 04 40 20 00 04 40 20 3F +00 00 20 B9 6A 98 60 00 0A 00 E0 00 36 4C 00 00 +01 00 00 00 AC 6B 75 80 8D 75 7B 01 CA 98 48 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/external/cache/sources/linuxpg/8105EC.cfg b/external/cache/sources/linuxpg/8105EC.cfg new file mode 100644 index 0000000..2a60015 --- /dev/null +++ b/external/cache/sources/linuxpg/8105EC.cfg @@ -0,0 +1,65 @@ +NODEID = 00 E0 4C 36 00 01 +;ENDID = 00 E0 4C 36 FF FF +VID = 10 EC +DID = 81 36 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +CONFIG0 = 00 +CONFIG1 = 0F +CONFIGx = 1C +CONFIG3 = 60 +CONFIG4 = 14 +CONFIG5 = 82 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 8A + +PMC = C3 FF +ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +LEDCFG = 98 CA +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 36 00 00 00 01 + +;PCI-E Parameter (Do not change without Realtek approval) +C_PCIE0 = 04 01 +;0AH~0BH +C_PCIE1 = C0 8C 80 02 00 00 11 3C 07 00 10 20 +;1AH~25H +C_PCIE2 = 76 00 63 01 01 FF 13 AA 03 02 20 +;26H~2BH 2DH~31H +C_PCIE3 = 80 02 00 20 04 40 20 00 04 40 20 00 00 20 +;34H~3EH 40H~42H +C_PCIE4 = 60 00 0A 00 00 00 +;46H~49H 52~53H +C_EPHY = B9 6A 98 AC 6B 76 80 +;43H~45H 54H~57H +D_EPHY = 6D 75 7B 01 +;58H~5BH +E_EPHY = 48 87 79 07 80 +;5EH~62H +VERSION = 1.031 + + diff --git a/external/cache/sources/linuxpg/8105EC.map b/external/cache/sources/linuxpg/8105EC.map new file mode 100644 index 0000000..80fcf56 --- /dev/null +++ b/external/cache/sources/linuxpg/8105EC.map @@ -0,0 +1,8 @@ +29 81 EC 10 36 81 EC 10 23 01 04 01 1C 60 00 E0 +4C 36 00 03 00 0F C3 FF 14 82 C0 8C 80 02 00 00 +11 3C 07 00 10 20 76 00 63 01 01 FF 00 13 AA 03 +02 20 00 EA 80 02 00 20 04 40 20 00 04 40 20 3F +00 00 20 B9 6A 98 60 00 0A 00 E0 00 36 4C 00 00 +03 00 00 00 AC 6B 76 80 6D 75 7B 01 CA 98 48 87 +79 07 80 FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF \ No newline at end of file diff --git a/external/cache/sources/linuxpg/8105ECEF.cfg b/external/cache/sources/linuxpg/8105ECEF.cfg new file mode 100644 index 0000000..a8ee092 --- /dev/null +++ b/external/cache/sources/linuxpg/8105ECEF.cfg @@ -0,0 +1,48 @@ +NODEID = 00 E0 4C 36 00 01 +;ENDID = 00 E0 4C 36 FF FF +;VID = 10 EC +;DID = 81 36 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +CONFIG0 = 00 +CONFIG1 = 0F +CONFIGx = 1C +CONFIG3 = 60 +CONFIG4 = 14 +CONFIG5 = 82 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 8A +PMC = C3 FF +ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +LEDCFG = 98 CA +;Prefetchable memory access. Non-Prefetchable set to 04H, Prefetchable set to 0CH +PREFETCHABLE = 04 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 36 00 00 00 01 +VERSION = 1.031 + + diff --git a/external/cache/sources/linuxpg/8105EF.cfg b/external/cache/sources/linuxpg/8105EF.cfg new file mode 100644 index 0000000..a8ee092 --- /dev/null +++ b/external/cache/sources/linuxpg/8105EF.cfg @@ -0,0 +1,48 @@ +NODEID = 00 E0 4C 36 00 01 +;ENDID = 00 E0 4C 36 FF FF +;VID = 10 EC +;DID = 81 36 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +CONFIG0 = 00 +CONFIG1 = 0F +CONFIGx = 1C +CONFIG3 = 60 +CONFIG4 = 14 +CONFIG5 = 82 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 8A +PMC = C3 FF +ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +LEDCFG = 98 CA +;Prefetchable memory access. Non-Prefetchable set to 04H, Prefetchable set to 0CH +PREFETCHABLE = 04 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 36 00 00 00 01 +VERSION = 1.031 + + diff --git a/external/cache/sources/linuxpg/8106E.cfg b/external/cache/sources/linuxpg/8106E.cfg new file mode 100644 index 0000000..324af06 --- /dev/null +++ b/external/cache/sources/linuxpg/8106E.cfg @@ -0,0 +1,65 @@ +NODEID = 00 E0 4C 36 00 01 +;ENDID = 00 E0 4C 36 FF FF +VID = 10 EC +DID = 81 36 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +CONFIG0 = 00 +CONFIG1 = CF +CONFIGx = 1C +CONFIG3 = 60 +CONFIG4 = 14 +CONFIG5 = 82 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 8A + +PMC = C3 FF +ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +LEDCFG = 90 CA +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 36 00 00 00 01 + +;PCI-E Parameter (Do not change without Realtek approval) +C_PCIE0 = 04 01 +;0AH~0BH +C_PCIE1 = C0 8C 80 02 00 00 11 3C 07 00 10 20 +;1AH~25H +C_PCIE2 = 76 00 63 01 01 FF 13 00 03 02 20 +;26H~2BH 2DH~31H +C_PCIE3 = 80 02 00 20 04 40 20 00 04 40 20 00 00 20 +;34H~3EH 40H~42H +C_PCIE4 = 60 00 0A 00 00 00 +;46H~49H 52~53H +C_EPHY = B9 6A 98 AC 6B 76 80 +;43H~45H 54H~57H +D_EPHY = 6D 75 7B 01 +;58H~5BH +E_EPHY = 48 87 79 07 80 +;5EH~62H +VERSION = 1.031 + + diff --git a/external/cache/sources/linuxpg/8106E.map b/external/cache/sources/linuxpg/8106E.map new file mode 100644 index 0000000..471ca06 --- /dev/null +++ b/external/cache/sources/linuxpg/8106E.map @@ -0,0 +1,8 @@ +29 81 EC 10 36 81 EC 10 23 01 04 01 1C 60 00 E0 +4C 36 00 03 00 CF C3 FF 14 82 C0 8C 80 02 00 00 +11 3C 07 00 10 20 76 00 63 01 01 FF 00 13 00 03 +02 20 00 EA 80 02 00 20 04 40 20 00 04 40 20 3F +00 00 20 B9 6A 98 60 00 0A 00 E0 00 36 4C 00 00 +03 00 00 00 AC 6B 76 80 6D 75 7B 01 CA 90 48 87 +79 07 80 FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF \ No newline at end of file diff --git a/external/cache/sources/linuxpg/8106EEF.cfg b/external/cache/sources/linuxpg/8106EEF.cfg new file mode 100644 index 0000000..7ca6564 --- /dev/null +++ b/external/cache/sources/linuxpg/8106EEF.cfg @@ -0,0 +1,53 @@ +NODEID = 00 E0 4C 36 00 01 +;ENDID = 00 E0 4C 36 FF FF +;VID = 10 EC +;DID = 81 36 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +CONFIG0 = 00 +CONFIG1 = CF +CONFIGx = 1C +CONFIG3 = 60 +CONFIG4 = 14 +CONFIG5 = 82 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 8A +PMC = C3 FF +ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +LEDCFG = 90 CA +;Prefetchable memory access. Non-Prefetchable set to 04H, Prefetchable set to 0CH +PREFETCHABLE = 04 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 36 00 00 00 01 + +;LANCFG +;BIT 0:LAN Disable +;BIT 31:Clear LANCFG +;LANCFG = 00 00 00 00 +VERSION = 1.031 + + diff --git a/external/cache/sources/linuxpg/8106EU.cfg b/external/cache/sources/linuxpg/8106EU.cfg new file mode 100644 index 0000000..e75b767 --- /dev/null +++ b/external/cache/sources/linuxpg/8106EU.cfg @@ -0,0 +1,49 @@ +NODEID = 00 E0 4C 36 00 01 +;ENDID = 00 E0 4C 36 FF FF +VID = 10 EC +DID = 81 36 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +;CONFIG0 = 00 +;CONFIG1 = CF +CONFIGx = 3C +;CONFIG3 = 60 +;CONFIG4 = 14 +;CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +;CONFIG7 = 07 +;PMC = C3 FF +;ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +;LEDCFG = 0C A9 +;Prefetchable memory access. Non-Prefetchable set to 04H, Prefetchable set to 0CH +PREFETCHABLE = 04 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 36 00 00 00 01 + +;DISFUNCXIOBAR = 00 +VERSION = 1.031 diff --git a/external/cache/sources/linuxpg/8106EUEF.cfg b/external/cache/sources/linuxpg/8106EUEF.cfg new file mode 100644 index 0000000..ac75fb5 --- /dev/null +++ b/external/cache/sources/linuxpg/8106EUEF.cfg @@ -0,0 +1,54 @@ +NODEID = 00 E0 4C 36 00 01 +;ENDID = 00 E0 4C 36 FF FF +;VID = 10 EC +;DID = 81 36 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +;CONFIG0 = 00 +;CONFIG1 = CF +CONFIGx = 3C +;CONFIG3 = 60 +;CONFIG4 = 14 +;CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +;CONFIG7 = 07 +;PMC = C3 FF +;ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +;LEDCFG = 0C A9 +;Prefetchable memory access. Non-Prefetchable set to 04H, Prefetchable set to 0CH +PREFETCHABLE = 04 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 36 00 00 00 01 + +;LANCFG +;BIT 0:LAN Disable BIT 1:PHY Disable BIT 2:Link OK +;BIT 31:Clear LANCFG +;LANCFG = 00 00 00 00 + +;DISFUNCXIOBAR = 00 +VERSION = 1.031 diff --git a/external/cache/sources/linuxpg/8107E.cfg b/external/cache/sources/linuxpg/8107E.cfg new file mode 100644 index 0000000..cefc049 --- /dev/null +++ b/external/cache/sources/linuxpg/8107E.cfg @@ -0,0 +1,49 @@ +NODEID = 00 E0 4C 36 00 01 +;ENDID = 00 E0 4C 36 FF FF +;VID = 10 EC +;DID = 81 36 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +;CONFIG0 = 00 +;CONFIG1 = CF +;CONFIGx = 3C +;CONFIG3 = 60 +;CONFIG4 = 14 +;CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +;CONFIG7 = 37 +;PMC = C3 FF +;ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +;LEDCFG = 0C A9 +;Prefetchable memory access. Non-Prefetchable set to 04H, Prefetchable set to 0CH +;PREFETCHABLE = 04 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 36 00 00 00 01 + +;DISFUNCXIOBAR = 00 +VERSION = 1.031 diff --git a/external/cache/sources/linuxpg/8107EEF.cfg b/external/cache/sources/linuxpg/8107EEF.cfg new file mode 100644 index 0000000..bc272a6 --- /dev/null +++ b/external/cache/sources/linuxpg/8107EEF.cfg @@ -0,0 +1,58 @@ +NODEID = 00 E0 4C 36 00 01 +;ENDID = 00 E0 4C 36 FF FF +;VID = 10 EC +;DID = 81 36 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +;CONFIG0 = 00 +;CONFIG1 = CF +;CONFIGx = 3C +;CONFIG3 = 60 +;CONFIG4 = 14 +;CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +CONFIG7 = 07 +;PMC = C3 FF +;ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +;LEDCFG = 0C A9 +;Prefetchable memory access. Non-Prefetchable set to 04H, Prefetchable set to 0CH +;PREFETCHABLE = 04 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 36 00 00 00 01 + +;LANCFG +;BIT 0:LAN Disable BIT 1:PHY Disable BIT 2:Link OK +;BIT 31:Clear LANCFG +;LANCFG = 00 00 00 00 + +;CTAPSHORT +;Enable set to 01H, Disable set to 00H +;CTAPSHORT = 01 + +;DISFUNCXIOBAR = 00 +VERSION = 1.031 diff --git a/external/cache/sources/linuxpg/8110SC.bin b/external/cache/sources/linuxpg/8110SC.bin new file mode 100644 index 0000000..05fae50 Binary files /dev/null and b/external/cache/sources/linuxpg/8110SC.bin differ diff --git a/external/cache/sources/linuxpg/8110SC.cfg b/external/cache/sources/linuxpg/8110SC.cfg new file mode 100644 index 0000000..941a5af --- /dev/null +++ b/external/cache/sources/linuxpg/8110SC.cfg @@ -0,0 +1,39 @@ +NODEID = 00 E0 4C 67 00 01 +;ENDID = 00 E0 4C 67 FF FF +VID = 10 EC +DID = 81 67 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +MNGNT = 20 +MXLAT = 40 +CONFIGx = 01 +CONFIG3 = A1 +CONFIG0 = 15 +CONFIG1 = CD +CONFIG4 = 80 +CONFIG5 = 13 +PMC = C2 F7 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Seconds +VERSION = 1.031 + diff --git a/external/cache/sources/linuxpg/8110SC.map b/external/cache/sources/linuxpg/8110SC.map new file mode 100644 index 0000000..c60857a --- /dev/null +++ b/external/cache/sources/linuxpg/8110SC.map @@ -0,0 +1,8 @@ +29 81 EC 10 67 81 EC 10 23 01 20 40 01 A1 00 E0 +4C 67 10 40 15 CD C2 F7 00 80 00 00 00 00 00 13 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 D7 7E 00 00 00 00 00 00 00 00 00 00 00 3F +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ No newline at end of file diff --git a/external/cache/sources/linuxpg/8116AFEF.cfg b/external/cache/sources/linuxpg/8116AFEF.cfg new file mode 100644 index 0000000..39edcdd --- /dev/null +++ b/external/cache/sources/linuxpg/8116AFEF.cfg @@ -0,0 +1,70 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +;VID = 10 EC +;DID = 81 68 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +;CONFIG0 = 00 +;CONFIG1 = CF +CONFIGx = 3C +;CONFIG3 = 60 +;CONFIG4 = 14 +;CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +;CONFIG7 = 07 +;PMC = C3 FF +;ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +;LEDCFG = 0C A9 +;ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;LANCFG +;BIT 0:LAN Disable BIT 2:Link OK +;BIT 31:Clear LANCFG +;LANCFG = 00 00 00 00 + +;LEDSUBCFG +;Please make sure CONFIGX LED low power bit enabled +;(IO reg offset 0x53 bit 2 set to 0) before modifying LEDSUBCFG +;BIT 0:LED0 Low Power Enable in D3cold BIT 1:LED1 Low Power Enable in D3cold +;BIT 2:LED2 Low Power Enable in D3cold +;BIT 3:LED0 Preboot Enable BIT 4: LED1 Preboot Enable +;BIT 5:LED2 Preboot Enable +;LEDSUBCFG = 00 + +;Disable: 00, Enable: 01 +;Secure boot +;SECUREBOOT = 01 + +;PCIE Link Capability +;LINKPCIEGEN = 11 + +;Disable multi-function X +;DISABLEFUNCX = 00 +VERSION = 1.031 + diff --git a/external/cache/sources/linuxpg/8116AFFL.cfg b/external/cache/sources/linuxpg/8116AFFL.cfg new file mode 100644 index 0000000..699a427 --- /dev/null +++ b/external/cache/sources/linuxpg/8116AFFL.cfg @@ -0,0 +1,36 @@ +; RTL8168FP Configuration file +; 2009/04/01 +; +; Out of band MAC ID +;NODEID = 00 E0 4C 68 03 DD +; +; user login name +USERNAME = Administrator +; user password, password length has to be 16 bytes +; default password 'realtek' +PASSWORD = 52 65 61 6c 74 65 6b 00 00 00 00 00 00 00 00 00 +; operation role +; Administrator : 01 +; Operator: 02 +; Guest : 03 +;ROLE = 01 +; OOB IP address +IP = 192.168.0.10 +; OOB subnet mask +SUBNET = 255.255.250.0 +; OOB gateway IP address +GATEWAY = 192.168.0.254 +; OOB DNS server ip address +;DNS = 192.168.0.1 +; ASP console IP address +;ASFIP = 192.168.0.3 +; ASF function setting +; enable : ON +; disable : OFF +;ASFON = ON +; IPV4 DHCP setting +; enable : ON +; disable : OFF +;DHCPIPV4 = OFF +HOSTNAME = DASHOOB +HN_SUFFIX = ON \ No newline at end of file diff --git a/external/cache/sources/linuxpg/8116ASEF.cfg b/external/cache/sources/linuxpg/8116ASEF.cfg new file mode 100644 index 0000000..39edcdd --- /dev/null +++ b/external/cache/sources/linuxpg/8116ASEF.cfg @@ -0,0 +1,70 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +;VID = 10 EC +;DID = 81 68 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +;CONFIG0 = 00 +;CONFIG1 = CF +CONFIGx = 3C +;CONFIG3 = 60 +;CONFIG4 = 14 +;CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +;CONFIG7 = 07 +;PMC = C3 FF +;ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +;LEDCFG = 0C A9 +;ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;LANCFG +;BIT 0:LAN Disable BIT 2:Link OK +;BIT 31:Clear LANCFG +;LANCFG = 00 00 00 00 + +;LEDSUBCFG +;Please make sure CONFIGX LED low power bit enabled +;(IO reg offset 0x53 bit 2 set to 0) before modifying LEDSUBCFG +;BIT 0:LED0 Low Power Enable in D3cold BIT 1:LED1 Low Power Enable in D3cold +;BIT 2:LED2 Low Power Enable in D3cold +;BIT 3:LED0 Preboot Enable BIT 4: LED1 Preboot Enable +;BIT 5:LED2 Preboot Enable +;LEDSUBCFG = 00 + +;Disable: 00, Enable: 01 +;Secure boot +;SECUREBOOT = 01 + +;PCIE Link Capability +;LINKPCIEGEN = 11 + +;Disable multi-function X +;DISABLEFUNCX = 00 +VERSION = 1.031 + diff --git a/external/cache/sources/linuxpg/8116ASFL.cfg b/external/cache/sources/linuxpg/8116ASFL.cfg new file mode 100644 index 0000000..699a427 --- /dev/null +++ b/external/cache/sources/linuxpg/8116ASFL.cfg @@ -0,0 +1,36 @@ +; RTL8168FP Configuration file +; 2009/04/01 +; +; Out of band MAC ID +;NODEID = 00 E0 4C 68 03 DD +; +; user login name +USERNAME = Administrator +; user password, password length has to be 16 bytes +; default password 'realtek' +PASSWORD = 52 65 61 6c 74 65 6b 00 00 00 00 00 00 00 00 00 +; operation role +; Administrator : 01 +; Operator: 02 +; Guest : 03 +;ROLE = 01 +; OOB IP address +IP = 192.168.0.10 +; OOB subnet mask +SUBNET = 255.255.250.0 +; OOB gateway IP address +GATEWAY = 192.168.0.254 +; OOB DNS server ip address +;DNS = 192.168.0.1 +; ASP console IP address +;ASFIP = 192.168.0.3 +; ASF function setting +; enable : ON +; disable : OFF +;ASFON = ON +; IPV4 DHCP setting +; enable : ON +; disable : OFF +;DHCPIPV4 = OFF +HOSTNAME = DASHOOB +HN_SUFFIX = ON \ No newline at end of file diff --git a/external/cache/sources/linuxpg/8116EF.cfg b/external/cache/sources/linuxpg/8116EF.cfg new file mode 100644 index 0000000..21e02a6 --- /dev/null +++ b/external/cache/sources/linuxpg/8116EF.cfg @@ -0,0 +1,76 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +;VID = 10 EC +;DID = 81 68 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +;CONFIG0 = 00 +;CONFIG1 = CF +CONFIGx = 3C +;CONFIG3 = 60 +;CONFIG4 = 14 +;CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +;CONFIG7 = 07 +;PMC = C3 FF +;ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +;LEDCFG = 0C A9 +;ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;LANCFG +;BIT 0:LAN Disable BIT 1:PHY Disable BIT 2:Link OK +;BIT 31:Clear LANCFG +;LANCFG = 00 00 00 00 + +;Link Capability +;PHYGBCR = 02 00 +;PHYANAR = 01 E1 + +;LEDSUBCFG +;Please make sure CONFIGX LED low power bit enabled +;(IO reg offset 0x53 bit 2 set to 0) before modifying LEDSUBCFG +;BIT 0:LED0 Low Power Enable in D3cold BIT 1:LED1 Low Power Enable in D3cold +;BIT 2:LED2 Low Power Enable in D3cold +;BIT 3:LED0 Preboot Enable BIT 4: LED1 Preboot Enable +;BIT 5:LED2 Preboot Enable +;LEDSUBCFG = 00 + +;Disable: 00, Enable: 01 +;UPS mode power saving +;UPSMODEPWRSAVING = 00 +;Secure boot +;SECUREBOOT = 01 + +;PCIE Link Capability +;LINKPCIEGEN = 11 + +;Disable multi-function X +;DISABLEFUNCX = 00 +VERSION = 1.031 + diff --git a/external/cache/sources/linuxpg/8116FL.cfg b/external/cache/sources/linuxpg/8116FL.cfg new file mode 100644 index 0000000..699a427 --- /dev/null +++ b/external/cache/sources/linuxpg/8116FL.cfg @@ -0,0 +1,36 @@ +; RTL8168FP Configuration file +; 2009/04/01 +; +; Out of band MAC ID +;NODEID = 00 E0 4C 68 03 DD +; +; user login name +USERNAME = Administrator +; user password, password length has to be 16 bytes +; default password 'realtek' +PASSWORD = 52 65 61 6c 74 65 6b 00 00 00 00 00 00 00 00 00 +; operation role +; Administrator : 01 +; Operator: 02 +; Guest : 03 +;ROLE = 01 +; OOB IP address +IP = 192.168.0.10 +; OOB subnet mask +SUBNET = 255.255.250.0 +; OOB gateway IP address +GATEWAY = 192.168.0.254 +; OOB DNS server ip address +;DNS = 192.168.0.1 +; ASP console IP address +;ASFIP = 192.168.0.3 +; ASF function setting +; enable : ON +; disable : OFF +;ASFON = ON +; IPV4 DHCP setting +; enable : ON +; disable : OFF +;DHCPIPV4 = OFF +HOSTNAME = DASHOOB +HN_SUFFIX = ON \ No newline at end of file diff --git a/external/cache/sources/linuxpg/8117APEF.cfg b/external/cache/sources/linuxpg/8117APEF.cfg new file mode 100644 index 0000000..b1b4528 --- /dev/null +++ b/external/cache/sources/linuxpg/8117APEF.cfg @@ -0,0 +1,82 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +;VID = 10 EC +;DID = 81 68 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +;CONFIG0 = 00 +;CONFIG1 = CF +CONFIGx = 3C +;CONFIG3 = 60 +;CONFIG4 = 14 +;CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +;CONFIG7 = 07 +;PMC = C3 FF +;ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +;LEDCFG = 0C A9 +;ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;LANCFG +;BIT 0:LAN Disable BIT 1:PHY Disable BIT 2:Link OK +;BIT 31:Clear LANCFG +;LANCFG = 00 00 00 00 + +;Link Capability +;PHYGBCR = 02 00 +;PHYANAR = 01 E1 + +;LEDSUBCFG +;Please make sure CONFIGX LED low power bit enabled +;(IO reg offset 0x53 bit 2 set to 0) before modifying LEDSUBCFG +;BIT 0:LED0 Low Power Enable in D3cold BIT 1:LED1 Low Power Enable in D3cold +;BIT 2:LED2 Low Power Enable in D3cold +;BIT 3:LED0 Preboot Enable BIT 4: LED1 Preboot Enable +;BIT 5:LED2 Preboot Enable +;LEDSUBCFG = 00 + +;Disable: 00, Enable: 01 +;UPHY Reset USB Bypass mode +;USBBYPASSMODE = 00 +;UPS mode power saving +;UPSMODEPWRSAVING = 00 +;Secure boot +;SECUREBOOT = 01 + +;EHCI PMC +;Enable EHCI PME_D3cold & PME_D3hot support in PMC +EHCIPMC = C3 FF + +;PCIE Link Capability +;LINKPCIEGEN = 11 + +;Disable multi-function X +;DISABLEFUNCX = 00 +VERSION = 1.031 + diff --git a/external/cache/sources/linuxpg/8117EF.cfg b/external/cache/sources/linuxpg/8117EF.cfg new file mode 100644 index 0000000..b1b4528 --- /dev/null +++ b/external/cache/sources/linuxpg/8117EF.cfg @@ -0,0 +1,82 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +;VID = 10 EC +;DID = 81 68 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +;CONFIG0 = 00 +;CONFIG1 = CF +CONFIGx = 3C +;CONFIG3 = 60 +;CONFIG4 = 14 +;CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +;CONFIG7 = 07 +;PMC = C3 FF +;ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +;LEDCFG = 0C A9 +;ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;LANCFG +;BIT 0:LAN Disable BIT 1:PHY Disable BIT 2:Link OK +;BIT 31:Clear LANCFG +;LANCFG = 00 00 00 00 + +;Link Capability +;PHYGBCR = 02 00 +;PHYANAR = 01 E1 + +;LEDSUBCFG +;Please make sure CONFIGX LED low power bit enabled +;(IO reg offset 0x53 bit 2 set to 0) before modifying LEDSUBCFG +;BIT 0:LED0 Low Power Enable in D3cold BIT 1:LED1 Low Power Enable in D3cold +;BIT 2:LED2 Low Power Enable in D3cold +;BIT 3:LED0 Preboot Enable BIT 4: LED1 Preboot Enable +;BIT 5:LED2 Preboot Enable +;LEDSUBCFG = 00 + +;Disable: 00, Enable: 01 +;UPHY Reset USB Bypass mode +;USBBYPASSMODE = 00 +;UPS mode power saving +;UPSMODEPWRSAVING = 00 +;Secure boot +;SECUREBOOT = 01 + +;EHCI PMC +;Enable EHCI PME_D3cold & PME_D3hot support in PMC +EHCIPMC = C3 FF + +;PCIE Link Capability +;LINKPCIEGEN = 11 + +;Disable multi-function X +;DISABLEFUNCX = 00 +VERSION = 1.031 + diff --git a/external/cache/sources/linuxpg/8118.cfg b/external/cache/sources/linuxpg/8118.cfg new file mode 100644 index 0000000..64038ee --- /dev/null +++ b/external/cache/sources/linuxpg/8118.cfg @@ -0,0 +1,49 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +;VID = 10 EC +;DID = 81 68 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +;CONFIG0 = 00 +;CONFIG1 = CF +;CONFIGx = 3C +;CONFIG3 = 60 +;CONFIG4 = 14 +;CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +;CONFIG7 = 37 +;PMC = C3 FF +;ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +;LEDCFG = 0C A9 +;Prefetchable memory access. Non-Prefetchable set to 04H, Prefetchable set to 0CH +;PREFETCHABLE = 04 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;DISFUNCXIOBAR = 00 +VERSION = 1.031 diff --git a/external/cache/sources/linuxpg/8118.map b/external/cache/sources/linuxpg/8118.map new file mode 100644 index 0000000..ced2e61 --- /dev/null +++ b/external/cache/sources/linuxpg/8118.map @@ -0,0 +1,8 @@ +29 81 00 E0 4C 68 00 01 EC 10 68 81 EC 10 23 01 +00 E0 4C 68 00 00 00 01 84 FA 3F FF 19 4C 30 02 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF \ No newline at end of file diff --git a/external/cache/sources/linuxpg/8118EF.cfg b/external/cache/sources/linuxpg/8118EF.cfg new file mode 100644 index 0000000..8174407 --- /dev/null +++ b/external/cache/sources/linuxpg/8118EF.cfg @@ -0,0 +1,65 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +;VID = 10 EC +;DID = 81 68 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +;CONFIG0 = 00 +;CONFIG1 = CF +;CONFIGx = 3C +;CONFIG3 = 60 +;CONFIG4 = 14 +;CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +CONFIG7 = 07 +;PMC = C3 FF +;ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +;LEDCFG = 0C A9 +;Prefetchable memory access. Non-Prefetchable set to 04H, Prefetchable set to 0CH +;PREFETCHABLE = 04 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;LANCFG +;BIT 0:LAN Disable BIT 1:PHY Disable BIT 2:Link OK +;BIT 31:Clear LANCFG +;LANCFG = 00 00 00 00 + +;Link Capability +;PHYGBCR = 02 00 +;PHYANAR = 01 E1 +;SpeedUp Capability +;Enable GPHY speed up by MAC set to 29H, Disable GPHY speed up by MAC set to 21H +;PHYPWRFUN = 21 + +;CTAPSHORT +;Enable set to 01H, Disable set to 00H +;CTAPSHORT = 01 + +;DISFUNCXIOBAR = 00 +VERSION = 1.031 diff --git a/external/cache/sources/linuxpg/8118KB.cfg b/external/cache/sources/linuxpg/8118KB.cfg new file mode 100644 index 0000000..1fdc787 --- /dev/null +++ b/external/cache/sources/linuxpg/8118KB.cfg @@ -0,0 +1,72 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +VID = 10 EC +DID = 81 62 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +;CONFIG0 = 00 +;CONFIG1 = CF +CONFIGx = 3C +;For add-on device, please set CONFIG3 to 60H +;CONFIG3 = 60 +;CONFIG4 = 14 +;CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +;CONFIG7 = 17 +;PMC = C3 FF +;ROMBAR = 00 +;LEDXCFG = High-Byte Low-Byte +;LEDX Bit 11: Low power mode enable +;LEDX Bit 10: Preboot enable +;Please make sure CONFIGx LED low power bit enabled +;(IO reg offset 0x53 bit 2 set to 0) before modifying LED low power mode or LED preboot +;LED0CFG = 02 01 +;LED1CFG = 02 02 +;LED2CFG = 02 08 +;LED3CFG = 02 20 +;LED Feature Functions +;Set BIT 0 to 0 : V1 led table. +;Set BIT 0 to 1 : V2 led table. +;BIT 1 to BIT 7 : Reserved +;LEDFEATUREFUNC = 60 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;MDI swap +;MDI non-swap set to 00H, MDI swap set to 20H +;MDISWAP = 00 + +;Tx polarity swap +;BIT 7: P3 non-swap set to 1, P3 swap set to 0 +;BIT 6: P2 non-swap set to 0, P2 swap set to 1 +;BIT 5: P1 non-swap set to 1, P1 swap set to 0 +;BIT 4: P0 non-swap set to 0, P0 swap set to 1 +;BIT 0 to BIT 3 : Reserved +;TXPOLSWAP = A0 + +;DISFUNCXIOBAR = 00 +VERSION = 1.031 diff --git a/external/cache/sources/linuxpg/8118KBEF.cfg b/external/cache/sources/linuxpg/8118KBEF.cfg new file mode 100644 index 0000000..2cf22e4 --- /dev/null +++ b/external/cache/sources/linuxpg/8118KBEF.cfg @@ -0,0 +1,77 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +;VID = 10 EC +;DID = 81 62 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +;CONFIG0 = 00 +;CONFIG1 = CF +CONFIGx = 3C +;For add-on device, please set CONFIG3 to 60H +;CONFIG3 = 60 +;CONFIG4 = 14 +;CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +CONFIG7 = 07 +;PMC = C3 FF +;ROMBAR = 00 +;LEDXCFG = High-Byte Low-Byte +;LEDX Bit 11: Low power mode enable +;LEDX Bit 10: Preboot enable +;Please make sure CONFIGx LED low power bit enabled +;(IO reg offset 0x53 bit 2 set to 0) before modifying LED low power mode or LED preboot +;LED0CFG = 02 01 +;LED1CFG = 02 02 +;LED2CFG = 02 08 +;LED3CFG = 02 20 +;LED Feature Functions +;Set BIT 0 to 0 : V1 led table. +;Set BIT 0 to 1 : V2 led table. +;BIT 1 to BIT 7 : Reserved +;LEDFEATUREFUNC = 60 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;LANCFG +;BIT 0:LAN Disable BIT 1:PHY Disable BIT 2:Link OK +;BIT 31:Clear LANCFG +;LANCFG = 00 00 00 00 + +;MDI swap +;MDI non-swap set to 00H, MDI swap set to 20H +;MDISWAP = 00 + +;Tx polarity swap +;BIT 7: P3 non-swap set to 1, P3 swap set to 0 +;BIT 6: P2 non-swap set to 0, P2 swap set to 1 +;BIT 5: P1 non-swap set to 1, P1 swap set to 0 +;BIT 4: P0 non-swap set to 0, P0 swap set to 1 +;BIT 0 to BIT 3 : Reserved +;TXPOLSWAP = A0 + +;DISFUNCXIOBAR = 00 +VERSION = 1.031 diff --git a/external/cache/sources/linuxpg/8119.cfg b/external/cache/sources/linuxpg/8119.cfg new file mode 100644 index 0000000..58fb413 --- /dev/null +++ b/external/cache/sources/linuxpg/8119.cfg @@ -0,0 +1,49 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +VID = 10 EC +DID = 81 68 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +CONFIG0 = 00 +CONFIG1 = CF +CONFIGx = 3C +CONFIG3 = 60 +CONFIG4 = 14 +CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +CONFIG7 = 07 +PMC = C3 FF +ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +;LEDCFG = 0C A9 +;Prefetchable memory access. Non-Prefetchable set to 04H, Prefetchable set to 0CH +PREFETCHABLE = 04 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 +VERSION = 1.031 + + diff --git a/external/cache/sources/linuxpg/8119.map b/external/cache/sources/linuxpg/8119.map new file mode 100644 index 0000000..b37725e --- /dev/null +++ b/external/cache/sources/linuxpg/8119.map @@ -0,0 +1,32 @@ +29 81 00 E0 4C 68 00 01 EC 10 68 81 EC 10 23 01 +01 00 00 00 68 4C E0 00 CA C9 30 FF 18 51 00 18 +52 CF 18 53 3C 18 54 60 18 55 14 18 56 02 50 42 +C3 FF 40 30 00 FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF \ No newline at end of file diff --git a/external/cache/sources/linuxpg/8119EF.cfg b/external/cache/sources/linuxpg/8119EF.cfg new file mode 100644 index 0000000..c492bd0 --- /dev/null +++ b/external/cache/sources/linuxpg/8119EF.cfg @@ -0,0 +1,58 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +;VID = 10 EC +;DID = 81 68 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +CONFIG0 = 00 +CONFIG1 = CF +CONFIGx = 3C +CONFIG3 = 60 +CONFIG4 = 14 +CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +;CONFIG7 = 07 +PMC = C3 FF +ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +;LEDCFG = 0C A9 +;Prefetchable memory access. Non-Prefetchable set to 04H, Prefetchable set to 0CH +PREFETCHABLE = 04 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;LANCFG +;BIT 0:LAN Disable BIT 1:PHY Disable +;BIT 31:Clear LANCFG +;LANCFG = 00 00 00 00 + +;Link Capability +;PHYGBCR = 03 00 +;PHYANAR = 01 E1 +VERSION = 1.031 + + diff --git a/external/cache/sources/linuxpg/8125.cfg b/external/cache/sources/linuxpg/8125.cfg new file mode 100644 index 0000000..e390c65 --- /dev/null +++ b/external/cache/sources/linuxpg/8125.cfg @@ -0,0 +1,71 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +VID = 10 EC +DID = 81 25 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +;CONFIG0 = 07 +;CONFIG1 = CF +CONFIGx = 3C +;For add-on device, please set CONFIG3 to 60H +;CONFIG3 = 60 +;CONFIG4 = 14 +;CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +;PMC = C3 FF +;ROMBAR = 00 +;LEDXCFG = High-Byte Low-Byte +;LEDX Bit 11: Low power mode enable +;LEDX Bit 10: Preboot enable +;Please make sure CONFIGx LED low power bit enabled +;(IO reg offset 0x53 bit 2 set to 0) before modifying LED low power mode or LED preboot +;LED0CFG = 02 01 +;LED1CFG = 02 02 +;LED2CFG = 02 08 +;LED3CFG = 02 20 +;LED Feature Functions +;Set BIT 0 to 0 : V1 led table. +;Set BIT 0 to 1 : V2 led table. +;BIT 1 to BIT 7 : Reserved +;LEDFEATUREFUNC = 60 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;MDI swap +;MDI non-swap set to 00H, MDI swap set to 20H +;MDISWAP = 00 + +;Tx polarity swap +;BIT 7: P3 non-swap set to 0, P3 swap set to 1 +;BIT 6: P2 non-swap set to 1, P2 swap set to 0 +;BIT 5: P1 non-swap set to 0, P1 swap set to 1 +;BIT 4: P0 non-swap set to 1, P0 swap set to 0 +;BIT 0 to BIT 3 : Reserved +;TXPOLSWAP = 50 + +;DISFUNCXIOBAR = 00 +VERSION = 1.031 diff --git a/external/cache/sources/linuxpg/8125.map b/external/cache/sources/linuxpg/8125.map new file mode 100644 index 0000000..da7b727 --- /dev/null +++ b/external/cache/sources/linuxpg/8125.map @@ -0,0 +1,8 @@ +29 81 00 E0 4C 68 00 01 EC 10 25 81 EC 10 23 01 +00 E0 4C 68 00 00 00 01 8C BD 3F FF F8 53 3C F9 +4C 3D 02 FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF \ No newline at end of file diff --git a/external/cache/sources/linuxpg/8125AG.cfg b/external/cache/sources/linuxpg/8125AG.cfg new file mode 100644 index 0000000..e390c65 --- /dev/null +++ b/external/cache/sources/linuxpg/8125AG.cfg @@ -0,0 +1,71 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +VID = 10 EC +DID = 81 25 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +;CONFIG0 = 07 +;CONFIG1 = CF +CONFIGx = 3C +;For add-on device, please set CONFIG3 to 60H +;CONFIG3 = 60 +;CONFIG4 = 14 +;CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +;PMC = C3 FF +;ROMBAR = 00 +;LEDXCFG = High-Byte Low-Byte +;LEDX Bit 11: Low power mode enable +;LEDX Bit 10: Preboot enable +;Please make sure CONFIGx LED low power bit enabled +;(IO reg offset 0x53 bit 2 set to 0) before modifying LED low power mode or LED preboot +;LED0CFG = 02 01 +;LED1CFG = 02 02 +;LED2CFG = 02 08 +;LED3CFG = 02 20 +;LED Feature Functions +;Set BIT 0 to 0 : V1 led table. +;Set BIT 0 to 1 : V2 led table. +;BIT 1 to BIT 7 : Reserved +;LEDFEATUREFUNC = 60 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;MDI swap +;MDI non-swap set to 00H, MDI swap set to 20H +;MDISWAP = 00 + +;Tx polarity swap +;BIT 7: P3 non-swap set to 0, P3 swap set to 1 +;BIT 6: P2 non-swap set to 1, P2 swap set to 0 +;BIT 5: P1 non-swap set to 0, P1 swap set to 1 +;BIT 4: P0 non-swap set to 1, P0 swap set to 0 +;BIT 0 to BIT 3 : Reserved +;TXPOLSWAP = 50 + +;DISFUNCXIOBAR = 00 +VERSION = 1.031 diff --git a/external/cache/sources/linuxpg/8125AG.map b/external/cache/sources/linuxpg/8125AG.map new file mode 100644 index 0000000..da7b727 --- /dev/null +++ b/external/cache/sources/linuxpg/8125AG.map @@ -0,0 +1,8 @@ +29 81 00 E0 4C 68 00 01 EC 10 25 81 EC 10 23 01 +00 E0 4C 68 00 00 00 01 8C BD 3F FF F8 53 3C F9 +4C 3D 02 FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF \ No newline at end of file diff --git a/external/cache/sources/linuxpg/8125AGEF.cfg b/external/cache/sources/linuxpg/8125AGEF.cfg new file mode 100644 index 0000000..4587c3c --- /dev/null +++ b/external/cache/sources/linuxpg/8125AGEF.cfg @@ -0,0 +1,76 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +;VID = 10 EC +;DID = 81 25 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +;CONFIG0 = 07 +;CONFIG1 = CF +CONFIGx = 3C +;For add-on device, please set CONFIG3 to 60H +;CONFIG3 = 60 +;CONFIG4 = 14 +;CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +;PMC = C3 FF +;ROMBAR = 00 +;LEDXCFG = High-Byte Low-Byte +;LEDX Bit 11: Low power mode enable +;LEDX Bit 10: Preboot enable +;Please make sure CONFIGx LED low power bit enabled +;(IO reg offset 0x53 bit 2 set to 0) before modifying LED low power mode or LED preboot +;LED0CFG = 02 01 +;LED1CFG = 02 02 +;LED2CFG = 02 08 +;LED3CFG = 02 20 +;LED Feature Functions +;Set BIT 0 to 0 : V1 led table. +;Set BIT 0 to 1 : V2 led table. +;BIT 1 to BIT 7 : Reserved +;LEDFEATUREFUNC = 60 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;LANCFG +;BIT 0:LAN Disable BIT 1:PHY Disable BIT 2:Link OK +;BIT 31:Clear LANCFG +;LANCFG = 00 00 00 00 + +;MDI swap +;MDI non-swap set to 00H, MDI swap set to 20H +;MDISWAP = 00 + +;Tx polarity swap +;BIT 7: P3 non-swap set to 0, P3 swap set to 1 +;BIT 6: P2 non-swap set to 1, P2 swap set to 0 +;BIT 5: P1 non-swap set to 0, P1 swap set to 1 +;BIT 4: P0 non-swap set to 1, P0 swap set to 0 +;BIT 0 to BIT 3 : Reserved +;TXPOLSWAP = 50 + +;DISFUNCXIOBAR = 00 +VERSION = 1.031 diff --git a/external/cache/sources/linuxpg/8125APEF.cfg b/external/cache/sources/linuxpg/8125APEF.cfg new file mode 100644 index 0000000..79e8d36 --- /dev/null +++ b/external/cache/sources/linuxpg/8125APEF.cfg @@ -0,0 +1,80 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +;VID = 10 EC +;DID = 81 25 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +;CONFIG0 = 07 +;CONFIG1 = CF +CONFIGx = 3C +;For add-on device, please set CONFIG3 to 60H +;CONFIG3 = 60 +;CONFIG4 = 14 +;CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +;PMC = C3 FF +;ROMBAR = 00 +;LEDXCFG = High-Byte Low-Byte +;LEDX Bit 11: Low power mode enable +;LEDX Bit 10: Preboot enable +;Please make sure CONFIGx LED low power bit enabled +;(IO reg offset 0x53 bit 2 set to 0) before modifying LED low power mode or LED preboot +;LED0CFG = 02 01 +;LED1CFG = 02 02 +;LED2CFG = 02 08 +;LED3CFG = 02 20 +;LED Feature Functions +;Set BIT 0 to 0 : V1 led table. +;Set BIT 0 to 1 : V2 led table. +;BIT 1 to BIT 7 : Reserved +;LEDFEATUREFUNC = 60 +;ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;LANCFG +;BIT 0:LAN Disable BIT 1:PHY Disable BIT 2:Link OK +;BIT 31:Clear LANCFG +;LANCFG = 00 00 00 00 + +;MDI swap +;MDI non-swap set to 00H, MDI swap set to 20H +;MDISWAP = 00 + +;Tx polarity swap +;BIT 7: P3 non-swap set to 0, P3 swap set to 1 +;BIT 6: P2 non-swap set to 1, P2 swap set to 0 +;BIT 5: P1 non-swap set to 0, P1 swap set to 1 +;BIT 4: P0 non-swap set to 1, P0 swap set to 0 +;BIT 0 to BIT 3 : Reserved +;TXPOLSWAP = 50 + +;DISFUNCXIOBAR = 00 + +;Disable: 00, Enable: 01 +;Secure boot +;SECUREBOOT = 01 +VERSION = 1.031 diff --git a/external/cache/sources/linuxpg/8125APFL.cfg b/external/cache/sources/linuxpg/8125APFL.cfg new file mode 100644 index 0000000..c61b2f7 --- /dev/null +++ b/external/cache/sources/linuxpg/8125APFL.cfg @@ -0,0 +1,36 @@ +; RTL8125AP Configuration file +; 2018/03/30 +; +; user login name +USERNAME = Administrator +; user password, password length has to be 16 bytes +; default password 'Realtek' +PASSWORD = 52 65 61 6c 74 65 6b 00 00 00 00 00 00 00 00 00 +; operation role +; Administrator : 01 +; Operator: 02 +; Guest : 03 +; ROLE = 01 +; OOB IP address +IP = 192.168.0.10 +; OOB subnet mask +SUBNET = 255.255.255.0 +; OOB gateway IP address +GATEWAY = 192.168.0.254 +; OOB DNS server ip address +; DNS = 192.168.0.1 +; ASP console IP address +; ASFIP = 192.168.0.3 +; ASF function setting +; enable : ON +; disable : OFF +; ASFON = ON +; IPV4 DHCP setting +; enable : ON +; disable : OFF +; DHCPIPV4 = OFF +HOSTNAME = DASHOOB +HN_SUFFIX = ON +;SARP_ADDR = C8 +;USB_OTG = ON +;WEBPAGE = OFF diff --git a/external/cache/sources/linuxpg/8125B.cfg b/external/cache/sources/linuxpg/8125B.cfg new file mode 100644 index 0000000..1b51e17 --- /dev/null +++ b/external/cache/sources/linuxpg/8125B.cfg @@ -0,0 +1,72 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +VID = 10 EC +DID = 81 25 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +;CONFIG0 = 00 +;CONFIG1 = CF +CONFIGx = 3C +;For add-on device, please set CONFIG3 to 60H +;CONFIG3 = 60 +;CONFIG4 = 14 +;CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +;CONFIG7 = 17 +;PMC = C3 FF +;ROMBAR = 00 +;LEDXCFG = High-Byte Low-Byte +;LEDX Bit 11: Low power mode enable +;LEDX Bit 10: Preboot enable +;Please make sure CONFIGx LED low power bit enabled +;(IO reg offset 0x53 bit 2 set to 0) before modifying LED low power mode or LED preboot +;LED0CFG = 02 01 +;LED1CFG = 02 02 +;LED2CFG = 02 08 +;LED3CFG = 02 20 +;LED Feature Functions +;Set BIT 0 to 0 : V1 led table. +;Set BIT 0 to 1 : V2 led table. +;BIT 1 to BIT 7 : Reserved +;LEDFEATUREFUNC = 60 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;MDI swap +;MDI non-swap set to 00H, MDI swap set to 20H +;MDISWAP = 00 + +;Tx polarity swap +;BIT 7: P3 non-swap set to 1, P3 swap set to 0 +;BIT 6: P2 non-swap set to 0, P2 swap set to 1 +;BIT 5: P1 non-swap set to 1, P1 swap set to 0 +;BIT 4: P0 non-swap set to 0, P0 swap set to 1 +;BIT 0 to BIT 3 : Reserved +;TXPOLSWAP = A0 + +;DISFUNCXIOBAR = 00 +VERSION = 1.031 diff --git a/external/cache/sources/linuxpg/8125BEF.cfg b/external/cache/sources/linuxpg/8125BEF.cfg new file mode 100644 index 0000000..52daaa4 --- /dev/null +++ b/external/cache/sources/linuxpg/8125BEF.cfg @@ -0,0 +1,77 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +;VID = 10 EC +;DID = 81 25 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +;CONFIG0 = 00 +;CONFIG1 = CF +CONFIGx = 3C +;For add-on device, please set CONFIG3 to 60H +;CONFIG3 = 60 +;CONFIG4 = 14 +;CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +CONFIG7 = 07 +;PMC = C3 FF +;ROMBAR = 00 +;LEDXCFG = High-Byte Low-Byte +;LEDX Bit 11: Low power mode enable +;LEDX Bit 10: Preboot enable +;Please make sure CONFIGx LED low power bit enabled +;(IO reg offset 0x53 bit 2 set to 0) before modifying LED low power mode or LED preboot +;LED0CFG = 02 01 +;LED1CFG = 02 02 +;LED2CFG = 02 08 +;LED3CFG = 02 20 +;LED Feature Functions +;Set BIT 0 to 0 : V1 led table. +;Set BIT 0 to 1 : V2 led table. +;BIT 1 to BIT 7 : Reserved +;LEDFEATUREFUNC = 60 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;LANCFG +;BIT 0:LAN Disable BIT 1:PHY Disable BIT 2:Link OK +;BIT 31:Clear LANCFG +;LANCFG = 00 00 00 00 + +;MDI swap +;MDI non-swap set to 00H, MDI swap set to 20H +;MDISWAP = 00 + +;Tx polarity swap +;BIT 7: P3 non-swap set to 1, P3 swap set to 0 +;BIT 6: P2 non-swap set to 0, P2 swap set to 1 +;BIT 5: P1 non-swap set to 1, P1 swap set to 0 +;BIT 4: P0 non-swap set to 0, P0 swap set to 1 +;BIT 0 to BIT 3 : Reserved +;TXPOLSWAP = A0 + +;DISFUNCXIOBAR = 00 +VERSION = 1.031 diff --git a/external/cache/sources/linuxpg/8125BG.cfg b/external/cache/sources/linuxpg/8125BG.cfg new file mode 100644 index 0000000..1b51e17 --- /dev/null +++ b/external/cache/sources/linuxpg/8125BG.cfg @@ -0,0 +1,72 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +VID = 10 EC +DID = 81 25 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +;CONFIG0 = 00 +;CONFIG1 = CF +CONFIGx = 3C +;For add-on device, please set CONFIG3 to 60H +;CONFIG3 = 60 +;CONFIG4 = 14 +;CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +;CONFIG7 = 17 +;PMC = C3 FF +;ROMBAR = 00 +;LEDXCFG = High-Byte Low-Byte +;LEDX Bit 11: Low power mode enable +;LEDX Bit 10: Preboot enable +;Please make sure CONFIGx LED low power bit enabled +;(IO reg offset 0x53 bit 2 set to 0) before modifying LED low power mode or LED preboot +;LED0CFG = 02 01 +;LED1CFG = 02 02 +;LED2CFG = 02 08 +;LED3CFG = 02 20 +;LED Feature Functions +;Set BIT 0 to 0 : V1 led table. +;Set BIT 0 to 1 : V2 led table. +;BIT 1 to BIT 7 : Reserved +;LEDFEATUREFUNC = 60 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;MDI swap +;MDI non-swap set to 00H, MDI swap set to 20H +;MDISWAP = 00 + +;Tx polarity swap +;BIT 7: P3 non-swap set to 1, P3 swap set to 0 +;BIT 6: P2 non-swap set to 0, P2 swap set to 1 +;BIT 5: P1 non-swap set to 1, P1 swap set to 0 +;BIT 4: P0 non-swap set to 0, P0 swap set to 1 +;BIT 0 to BIT 3 : Reserved +;TXPOLSWAP = A0 + +;DISFUNCXIOBAR = 00 +VERSION = 1.031 diff --git a/external/cache/sources/linuxpg/8125BGEF.cfg b/external/cache/sources/linuxpg/8125BGEF.cfg new file mode 100644 index 0000000..5ce1ef4 --- /dev/null +++ b/external/cache/sources/linuxpg/8125BGEF.cfg @@ -0,0 +1,77 @@ +NODEID = 00 E0 4C 68 00 0F +;ENDID = 00 E0 4C 68 FF FF +;VID = 10 EC +;DID = 81 25 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +;CONFIG0 = 00 +;CONFIG1 = CF +CONFIGx = 3C +;For add-on device, please set CONFIG3 to 60H +;CONFIG3 = 60 +;CONFIG4 = 14 +;CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +CONFIG7 = 07 +;PMC = C3 FF +;ROMBAR = 00 +;LEDXCFG = High-Byte Low-Byte +;LEDX Bit 11: Low power mode enable +;LEDX Bit 10: Preboot enable +;Please make sure CONFIGx LED low power bit enabled +;(IO reg offset 0x53 bit 2 set to 0) before modifying LED low power mode or LED preboot +LED0CFG = 18 2B +LED1CFG = 08 2B +LED2CFG = 1A 2B +;LED3CFG = 02 20 +;LED Feature Functions +;Set BIT 0 to 0 : V1 led table. +;Set BIT 0 to 1 : V2 led table. +;BIT 1 to BIT 7 : Reserved +;LEDFEATUREFUNC = 60 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;LANCFG +;BIT 0:LAN Disable BIT 1:PHY Disable BIT 2:Link OK +;BIT 31:Clear LANCFG +;LANCFG = 00 00 00 00 + +;MDI swap +;MDI non-swap set to 00H, MDI swap set to 20H +;MDISWAP = 00 + +;Tx polarity swap +;BIT 7: P3 non-swap set to 1, P3 swap set to 0 +;BIT 6: P2 non-swap set to 0, P2 swap set to 1 +;BIT 5: P1 non-swap set to 1, P1 swap set to 0 +;BIT 4: P0 non-swap set to 0, P0 swap set to 1 +;BIT 0 to BIT 3 : Reserved +;TXPOLSWAP = A0 + +;DISFUNCXIOBAR = 00 +VERSION = 1.031 diff --git a/external/cache/sources/linuxpg/8125BGEF.cfg-orig b/external/cache/sources/linuxpg/8125BGEF.cfg-orig new file mode 100644 index 0000000..52daaa4 --- /dev/null +++ b/external/cache/sources/linuxpg/8125BGEF.cfg-orig @@ -0,0 +1,77 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +;VID = 10 EC +;DID = 81 25 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +;CONFIG0 = 00 +;CONFIG1 = CF +CONFIGx = 3C +;For add-on device, please set CONFIG3 to 60H +;CONFIG3 = 60 +;CONFIG4 = 14 +;CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +CONFIG7 = 07 +;PMC = C3 FF +;ROMBAR = 00 +;LEDXCFG = High-Byte Low-Byte +;LEDX Bit 11: Low power mode enable +;LEDX Bit 10: Preboot enable +;Please make sure CONFIGx LED low power bit enabled +;(IO reg offset 0x53 bit 2 set to 0) before modifying LED low power mode or LED preboot +;LED0CFG = 02 01 +;LED1CFG = 02 02 +;LED2CFG = 02 08 +;LED3CFG = 02 20 +;LED Feature Functions +;Set BIT 0 to 0 : V1 led table. +;Set BIT 0 to 1 : V2 led table. +;BIT 1 to BIT 7 : Reserved +;LEDFEATUREFUNC = 60 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;LANCFG +;BIT 0:LAN Disable BIT 1:PHY Disable BIT 2:Link OK +;BIT 31:Clear LANCFG +;LANCFG = 00 00 00 00 + +;MDI swap +;MDI non-swap set to 00H, MDI swap set to 20H +;MDISWAP = 00 + +;Tx polarity swap +;BIT 7: P3 non-swap set to 1, P3 swap set to 0 +;BIT 6: P2 non-swap set to 0, P2 swap set to 1 +;BIT 5: P1 non-swap set to 1, P1 swap set to 0 +;BIT 4: P0 non-swap set to 0, P0 swap set to 1 +;BIT 0 to BIT 3 : Reserved +;TXPOLSWAP = A0 + +;DISFUNCXIOBAR = 00 +VERSION = 1.031 diff --git a/external/cache/sources/linuxpg/8125EF.cfg b/external/cache/sources/linuxpg/8125EF.cfg new file mode 100644 index 0000000..4587c3c --- /dev/null +++ b/external/cache/sources/linuxpg/8125EF.cfg @@ -0,0 +1,76 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +;VID = 10 EC +;DID = 81 25 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +;CONFIG0 = 07 +;CONFIG1 = CF +CONFIGx = 3C +;For add-on device, please set CONFIG3 to 60H +;CONFIG3 = 60 +;CONFIG4 = 14 +;CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +;PMC = C3 FF +;ROMBAR = 00 +;LEDXCFG = High-Byte Low-Byte +;LEDX Bit 11: Low power mode enable +;LEDX Bit 10: Preboot enable +;Please make sure CONFIGx LED low power bit enabled +;(IO reg offset 0x53 bit 2 set to 0) before modifying LED low power mode or LED preboot +;LED0CFG = 02 01 +;LED1CFG = 02 02 +;LED2CFG = 02 08 +;LED3CFG = 02 20 +;LED Feature Functions +;Set BIT 0 to 0 : V1 led table. +;Set BIT 0 to 1 : V2 led table. +;BIT 1 to BIT 7 : Reserved +;LEDFEATUREFUNC = 60 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;LANCFG +;BIT 0:LAN Disable BIT 1:PHY Disable BIT 2:Link OK +;BIT 31:Clear LANCFG +;LANCFG = 00 00 00 00 + +;MDI swap +;MDI non-swap set to 00H, MDI swap set to 20H +;MDISWAP = 00 + +;Tx polarity swap +;BIT 7: P3 non-swap set to 0, P3 swap set to 1 +;BIT 6: P2 non-swap set to 1, P2 swap set to 0 +;BIT 5: P1 non-swap set to 0, P1 swap set to 1 +;BIT 4: P0 non-swap set to 1, P0 swap set to 0 +;BIT 0 to BIT 3 : Reserved +;TXPOLSWAP = 50 + +;DISFUNCXIOBAR = 00 +VERSION = 1.031 diff --git a/external/cache/sources/linuxpg/8168.cfg b/external/cache/sources/linuxpg/8168.cfg new file mode 100644 index 0000000..7e7cc40 --- /dev/null +++ b/external/cache/sources/linuxpg/8168.cfg @@ -0,0 +1,49 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +VID = 10 EC +DID = 81 68 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +CONFIG0 = 00 +CONFIG1 = CF +CONFIGx = 00 +CONFIG3 = 60 +CONFIG4 = 00 +CONFIG5 = 03 +PMC = C2 F7 +ROMBAR = 00 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;PCI-E Parameter +PCIE1= 04 01 42 60 7E 00 00 04 +PCIE2= FF FF FF FF FF FF 1F +PCIE3= 00 47 10 F0 F0 01 BF 01 00 00 60 00 00 +;0AH,0BH,18H,1A~1EH +;28H~2EH +;30H~31H, 34H~3EH +VERSION = 1.031 + diff --git a/external/cache/sources/linuxpg/8168.map b/external/cache/sources/linuxpg/8168.map new file mode 100644 index 0000000..9c629d1 --- /dev/null +++ b/external/cache/sources/linuxpg/8168.map @@ -0,0 +1,16 @@ +29 81 EC 10 68 81 EC 10 23 01 04 01 00 60 00 E0 +4C 68 00 01 00 CF C2 F7 42 00 60 7E 00 00 04 03 +00 E0 4C 68 00 00 00 01 FF FF FF FF FF FF 1F 00 +00 46 0A C3 10 F0 F0 01 BF 01 00 00 60 00 00 3F +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ No newline at end of file diff --git a/external/cache/sources/linuxpg/8168C.cfg b/external/cache/sources/linuxpg/8168C.cfg new file mode 100644 index 0000000..7c0d4c7 --- /dev/null +++ b/external/cache/sources/linuxpg/8168C.cfg @@ -0,0 +1,56 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +VID = 10 EC +DID = 81 68 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +CONFIG0 = 00 +CONFIG1 = CF +CONFIGx = 0C +CONFIG3 = 62 +CONFIG4 = 00 +CONFIG5 = 02 +PMC = C3 FF +ROMBAR = 00 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;PCI-E Parameter (Do not change without Realtek approval) +C_PCIE0 = 04 01 +;0AH~0BH +C_PCIE1 = c1 8C 80 02 00 00 11 3c 07 00 10 20 +;1AH~25H +C_PCIE2 = 76 00 63 01 01 FF 27 AA 03 02 20 +;26H~2BH 2DH~31H +C_PCIE3 = 80 02 00 20 10 00 21 00 10 00 21 00 00 80 +;34H~3EH 40H~42H +C_PCIE4 = 80 00 20 00 00 00 +;46H~49H 52~53H +C_EPHY = 61 42 55 9E 72 B5 00 +;43H~45H 54H~57H +VERSION = 1.031 + + diff --git a/external/cache/sources/linuxpg/8168C.map b/external/cache/sources/linuxpg/8168C.map new file mode 100644 index 0000000..31bf2fb --- /dev/null +++ b/external/cache/sources/linuxpg/8168C.map @@ -0,0 +1,32 @@ +29 81 EC 10 68 81 EC 10 23 01 04 01 0C 62 00 E0 +4C 68 00 01 00 CF C3 FF 00 02 C1 8C 80 02 00 00 +11 3C 07 00 10 20 76 00 63 01 01 FF 00 27 AA 03 +02 20 1C AC 80 02 00 20 10 00 21 00 10 00 21 3F +00 00 80 61 42 55 80 00 20 00 E0 00 68 4C 00 00 +01 00 00 00 9E 72 B5 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/external/cache/sources/linuxpg/8168CP.cfg b/external/cache/sources/linuxpg/8168CP.cfg new file mode 100644 index 0000000..d88009b --- /dev/null +++ b/external/cache/sources/linuxpg/8168CP.cfg @@ -0,0 +1,106 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +VID = 10 EC +DID = 81 68 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +CONFIG0 = 00 +CONFIG1 = CF +CONFIGx = 4C +CONFIG3 = E2 +CONFIG4 = 00 +CONFIG5 = 02 +PMC = C3 FF +ROMBAR = 00 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;PCI-E Parameter (Do not change without Realtek approval) +C_PCIE0 = 04 01 +;0AH~0BH +C_PCIE1 = C1 8C 80 02 00 00 11 3c 07 00 10 20 +;1AH~25H +C_PCIE2 = 76 00 63 01 01 FF 27 AA 03 02 20 +;;26H~2BH 2DH~31H +C_PCIE3 = 80 02 00 20 10 00 21 00 10 00 21 00 00 80 +;34H~3EH 40H~42H +C_PCIE4 = 80 00 20 00 00 00 +;46H~49H 52~53H +C_EPHY = 61 42 5F 9E 74 F5 00 +;43H~45H 54H~57H + +CP_CONSOLE_NODEID = 00 00 00 00 00 00 +CP_CONSOLE_IP = 00 00 00 00 +CP_CLIENT_IP = 00 00 00 00 + +CP_OPERATOR_KEY = 98 73 F0 5B 1C 67 CC 50 D1 1E 2B B1 10 0D BB C3 8D D7 08 E2 +CP_ADMINISTRATOR_KEY = 10 67 B4 D0 D5 2B C5 0C 3A AF 66 69 B7 34 45 99 28 F4 F9 CC +CP_GENERATOR_KEY = DE EF 16 3B FB 8C 30 50 6B 3B F1 13 77 35 4D 9C 55 BD EB 87 +CP_RANDOM_KEY = 85 DB 22 6F 49 98 55 2C 22 D0 1A EA 88 51 45 48 AA 4F 65 3E + +CP_REMOTE_CONTROL = 88 00 03 88 00 02 88 00 01 88 00 04 +;Remote Control Parameter +;INTEL ==> 88 00 03 88 00 02 88 00 01 88 00 04 +;AMD ==> 71 00 00 71 02 00 71 01 00 71 03 00 +;NVIDIA ==> E0 0A 00 E0 0A 02 E0 0A 01 E0 0A 03 + +;Legacy sensor polling parameter +CP_LSP0 = 5F C0 FF 37 01 01 09 10 00 03 01 +;E0H~EAH +CP_LSP1 = 5F 42 20 20 05 6F 00 08 01 00 01 +;EBH~F5H +CP_LSP2 = 5F 28 FF FF 04 07 02 10 0A 03 01 +;F6H~100H +CP_LSP3 = 5F 29 FF FF 04 07 02 10 0B 07 01 +;101~10BH +CP_LSP4 = 5F 20 FF 90 02 07 02 10 01 03 01 +;10CH~116H +CP_LSP5 = 5F 22 FF 49 02 07 02 10 03 07 01 +;117H~121H +CP_LSP6 = 5F 23 FF 4D 02 07 02 10 04 07 02 +;122H~12CH +CP_LSP7 = 5F 24 FF 4D 02 07 02 10 05 07 03 +;12DH~137H + +;UUID +CP_UUID = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +;SYSTEM ID +CP_SYSID = 00 00 + +CP_EXTENDED_58_5F = 00 00 00 00 00 00 00 00 +CP_EXTENDED_60 = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +CP_EXTENDED_80_8B = 9B AB 0C 00 32 00 03 0A 03 0F C8 00 +CP_EXTENDED_AA_AD = 00 00 6A 92 +CP_EXTENDED_B0_BF = 70 75 62 6C 69 63 00 00 00 00 00 00 00 00 00 00 +CP_EXTENDED_C0_CF = 00 00 00 00 00 00 00 19 67 F8 00 00 00 1F F0 00 +CP_EXTENDED_DC_DF = 7E 00 FF 03 +CP_EXTENDED_138_143 = 04 00 00 00 00 40 06 00 01 00 00 00 +CP_EXTENDED_194_19F = 00 00 00 00 00 00 00 00 00 00 00 00 +CP_EXTENDED_1A0 = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +CP_EXTENDED_1C0 = 00 00 00 00 00 00 00 A2 00 A2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +CP_EXTENDED_1E0 = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +;80H~1FFH +VERSION = 1.031 diff --git a/external/cache/sources/linuxpg/8168CP.map b/external/cache/sources/linuxpg/8168CP.map new file mode 100644 index 0000000..481705d --- /dev/null +++ b/external/cache/sources/linuxpg/8168CP.map @@ -0,0 +1,32 @@ +29 81 EC 10 68 81 EC 10 23 01 04 01 4C E2 00 E0 +4C 68 00 01 00 CF C3 FF 00 02 C1 8C 80 02 00 00 +11 3C 07 00 10 20 76 00 63 01 01 FF 00 27 AA 03 +02 20 DC A5 80 02 00 20 10 00 21 00 10 00 21 3F +00 00 80 61 42 5F 80 00 20 00 E0 00 68 4C 00 00 +01 00 00 00 9E 74 F5 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +9B AB 0C 00 32 00 03 0A 03 0F C8 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 6A 92 00 00 +70 75 62 6C 69 63 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 19 67 F8 00 00 00 1F F0 00 +88 00 03 88 00 02 88 00 01 88 00 04 7E 00 FF 03 +89 04 FF 0D 07 6F 04 20 00 03 00 89 04 FF 01 05 +6F 00 08 01 17 00 80 23 FF 00 04 07 02 10 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 04 00 00 00 00 40 06 00 +01 00 00 00 E2 08 D7 8D C3 BB 0D 10 B1 2B 1E D1 +50 CC 67 1C 5B F0 73 98 CC F9 F4 28 99 45 34 B7 +69 66 AF 3A 0C C5 2B D5 D0 B4 67 10 87 EB BD 55 +9C 4D 35 77 13 F1 3B 6B 50 30 8C FB 3B 16 EF DE +3E 65 4F AA 48 45 51 88 EA 1A D0 22 2C 55 98 49 +6F 22 DB 85 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 A2 00 A2 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ No newline at end of file diff --git a/external/cache/sources/linuxpg/8168D.cfg b/external/cache/sources/linuxpg/8168D.cfg new file mode 100644 index 0000000..57a721d --- /dev/null +++ b/external/cache/sources/linuxpg/8168D.cfg @@ -0,0 +1,62 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +VID = 10 EC +DID = 81 68 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +CONFIG0 = 00 +CONFIG1 = CF +CONFIGx = 9C +CONFIG3 = 62 +CONFIG4 = 04 +CONFIG5 = 02 +PMC = C3 FF +ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +LEDCFG = 98 CA +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;PCI-E Parameter (Do not change without Realtek approval) +C_PCIE0 = 04 01 +;0AH~0BH +C_PCIE1 = c0 8C 80 02 00 00 11 3c 07 00 10 20 +;1AH~25H +C_PCIE2 = 76 00 63 01 01 FF 27 AA 03 02 20 +;26H~2BH 2DH~31H +C_PCIE3 = 80 02 00 20 04 40 20 00 04 40 20 00 00 20 +;34H~3EH 40H~42H +C_PCIE4 = 60 00 0A 00 00 00 +;46H~49H 52~53H +C_EPHY = 63 02 35 B2 73 71 80 +C0_EPHY = E3 02 BD B2 63 B5 EA +;43H~45H 54H~57H +D_EPHY = 87 75 7B 39 +D0_EPHY = 84 75 7A 39 +;58H~5BH +VERSION = 1.031 + + diff --git a/external/cache/sources/linuxpg/8168D.map b/external/cache/sources/linuxpg/8168D.map new file mode 100644 index 0000000..6ac90ab --- /dev/null +++ b/external/cache/sources/linuxpg/8168D.map @@ -0,0 +1,32 @@ +29 81 EC 10 68 81 EC 10 23 01 04 01 9C 62 00 E0 +4C 68 00 01 00 CF C3 FF 04 02 C0 8C 80 02 00 00 +11 3C 07 00 10 20 76 00 63 01 01 FF 00 27 AA 03 +02 20 99 A5 80 02 00 20 04 40 20 00 04 40 20 3F +00 00 20 E1 22 B5 60 00 0A 00 E0 00 68 4C 00 00 +01 00 00 00 B2 73 75 EA 87 75 7A 39 CA 98 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/external/cache/sources/linuxpg/8168DEF.cfg b/external/cache/sources/linuxpg/8168DEF.cfg new file mode 100644 index 0000000..3efd9ab --- /dev/null +++ b/external/cache/sources/linuxpg/8168DEF.cfg @@ -0,0 +1,46 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +;VID = 10 EC +;DID = 81 68 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +CONFIG0 = 00 +CONFIG1 = CF +CONFIGx = 9C +CONFIG3 = 62 +CONFIG4 = 04 +CONFIG5 = 02 +PMC = C3 FF +ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +LEDCFG = 98 CA +;Prefetchable memory access. Non-Prefetchable set to 04H, Prefetchable set to 0CH +PREFETCHABLE = 04 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 +VERSION = 1.031 + + diff --git a/external/cache/sources/linuxpg/8168DPEF.cfg b/external/cache/sources/linuxpg/8168DPEF.cfg new file mode 100644 index 0000000..600f62c --- /dev/null +++ b/external/cache/sources/linuxpg/8168DPEF.cfg @@ -0,0 +1,28 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +;VID = 10 EC +;DID = 81 68 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +CONFIG0 = 00 +;CONFIG1 = CF +CONFIGx = 98 +CONFIG3 = 60 +;CONFIG4 = 04 +;CONFIG5 = 02 +;PMC = C3 FF +;ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +;LEDCFG = 98 CA +;Prefetchable memory access. Non-Prefetchable set to 04H, Prefetchable set to 0CH +PREFETCHABLE = 04 +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;Multi Function Configuration. +;Enable Multi function set to 01H, Disable Multi function set to 00H +;MULTIFUN = 01 +VERSION = 1.031 + diff --git a/external/cache/sources/linuxpg/8168E.cfg b/external/cache/sources/linuxpg/8168E.cfg new file mode 100644 index 0000000..49ef1d6 --- /dev/null +++ b/external/cache/sources/linuxpg/8168E.cfg @@ -0,0 +1,122 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +VID = 10 EC +DID = 81 68 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +CONFIG0 = 00 +CONFIG1 = 0F +;Asf Disable +CONFIGx = 1C +CONFIG3 = 60 +;Asf Enable +;CONFIGx = 5D +;CONFIG3 = E0 + +CONFIG4 = 14 +CONFIG5 = 82 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 8A + +PMC = C3 FF +ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +LEDCFG = 98 CA +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;PCI-E Parameter (Do not change without Realtek approval) +C_PCIE0 = 04 01 +;0AH~0BH +C_PCIE1 = C0 8C 80 02 00 00 11 3C 07 00 10 20 +;1AH~25H +C_PCIE2 = 76 00 63 01 01 FF 13 AA 03 02 20 +;26H~2BH 2DH~31H +C_PCIE3 = 80 02 00 20 04 40 20 00 04 40 20 00 00 20 +;34H~3EH 40H~42H +C_PCIE4 = 60 00 0A 00 00 00 +;46H~49H 52~53H +C_EPHY = B9 6A 98 AC 6B 75 80 +;43H~45H 54H~57H +D_EPHY = 8D 75 7B 01 +;58H~5BH +E0_EPHY = 48 +;5EH + +CP_CONSOLE_NODEID = 00 00 00 00 00 00 +CP_CONSOLE_IP = 00 00 00 00 +CP_CLIENT_IP = 00 00 00 00 + +CP_OPERATOR_KEY = 98 73 F0 5B 1C 67 CC 50 D1 1E 2B B1 10 0D BB C3 8D D7 08 E2 +CP_ADMINISTRATOR_KEY = 10 67 B4 D0 D5 2B C5 0C 3A AF 66 69 B7 34 45 99 28 F4 F9 CC +CP_GENERATOR_KEY = DE EF 16 3B FB 8C 30 50 6B 3B F1 13 77 35 4D 9C 55 BD EB 87 +CP_RANDOM_KEY = 85 DB 22 6F 49 98 55 2C 22 D0 1A EA 88 51 45 48 AA 4F 65 3E + +CP_REMOTE_CONTROL = 88 00 03 88 00 02 88 00 01 88 00 04 +;Remote Control Parameter +;INTEL ==> 88 00 03 88 00 02 88 00 01 88 00 04 +;AMD ==> 71 00 00 71 02 00 71 01 00 71 03 00 +;NVIDIA ==> E0 0A 00 E0 0A 02 E0 0A 01 E0 0A 03 + +;Legacy sensor polling parameter +CP_LSP0 = 83 23 80 80 06 01 00 10 06 07 00 +;E0H~EAH +CP_LSP1 = 81 23 80 80 05 01 00 10 07 07 00 +;EBH~F5H +CP_LSP2 = 80 23 FF 00 04 07 02 10 00 00 00 +;F6H~100H +CP_LSP3 = 00 00 00 00 00 00 00 00 00 00 00 +;101~10BH +CP_LSP4 = 00 00 00 00 00 00 00 00 00 00 00 +;10CH~116H +CP_LSP5 = 00 00 00 00 00 00 00 00 00 00 00 +;117H~121H +CP_LSP6 = 00 00 00 00 00 00 00 00 00 00 00 +;122H~12CH +CP_LSP7 = 00 00 00 00 00 00 00 00 00 00 00 +;12DH~137H + +;UUID +CP_UUID = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +;SYSTEM ID +CP_SYSID = 00 00 + +CP_EXTENDED_5F = 00 +CP_EXTENDED_60 = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +CP_EXTENDED_80_8B = 9B 8B 14 00 32 00 03 0A 03 0F C8 00 +CP_EXTENDED_AA_AD = 00 00 6A 92 +CP_EXTENDED_B0_BF = 70 75 62 6C 69 63 00 00 00 00 00 00 00 00 00 00 +CP_EXTENDED_C0_CF = 00 00 00 00 00 00 00 19 67 F8 00 00 00 1F F0 00 +CP_EXTENDED_DC_DF = 7E 00 FF 02 +CP_EXTENDED_138_143 = 04 00 00 00 00 40 06 00 01 00 00 00 +CP_EXTENDED_194_19F = 00 00 00 00 00 00 00 00 00 00 00 00 +CP_EXTENDED_1A0 = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 EC 10 EC 10 68 81 68 81 00 00 00 00 +CP_EXTENDED_1C0 = 00 00 00 00 00 00 00 A2 00 A2 00 67 F8 00 00 00 1F F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +CP_EXTENDED_1E0 = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +;80H~1FFH +VERSION = 1.031 + + diff --git a/external/cache/sources/linuxpg/8168E.map b/external/cache/sources/linuxpg/8168E.map new file mode 100644 index 0000000..29944e7 --- /dev/null +++ b/external/cache/sources/linuxpg/8168E.map @@ -0,0 +1,32 @@ +29 81 EC 10 68 81 EC 10 23 01 04 01 1C 60 00 E0 +4C 68 00 01 00 0F C3 FF 14 82 C0 8C 80 02 00 00 +11 3C 07 00 10 20 76 76 00 63 01 01 FF 13 AA 03 +02 20 99 A5 80 02 00 20 04 40 20 00 04 40 20 3F +00 00 20 B9 6A 98 60 00 0A 00 E0 00 68 4C 00 00 +01 00 00 00 AC 6B 75 80 8D 75 7B 01 CA 98 48 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +9B 8B 14 00 32 00 03 0A 03 0F C8 00 00 13 72 84 +8B 37 C0 A8 00 03 C0 A8 00 0A 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 6A 92 00 00 +70 75 62 6C 69 63 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 19 67 F8 00 00 00 1F F0 00 +71 00 00 71 02 00 71 01 00 71 03 00 7E 00 FF 02 +83 23 80 80 06 01 00 10 06 07 00 81 23 80 80 05 +01 00 10 07 07 00 80 23 FF 00 04 07 02 10 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 04 00 00 00 00 40 06 00 +01 00 00 00 E2 08 D7 8D C3 BB 0D 10 B1 2B 1E D1 +50 CC 67 1C 5B F0 73 98 CC F9 F4 28 99 45 34 B7 +69 66 AF 3A 0C C5 2B D5 D0 B4 67 10 87 EB BD 55 +9C 4D 35 77 13 F1 3B 6B 50 30 8C FB 3B 16 EF DE +3E 65 4F AA 48 45 51 88 EA 1A D0 22 2C 55 98 49 +6F 22 DB 85 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 EC 10 EC 10 68 81 68 81 00 00 00 00 +00 00 00 00 00 00 00 A2 00 A2 00 67 F8 00 00 00 +1F F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ No newline at end of file diff --git a/external/cache/sources/linuxpg/8168EEF.cfg b/external/cache/sources/linuxpg/8168EEF.cfg new file mode 100644 index 0000000..beb253d --- /dev/null +++ b/external/cache/sources/linuxpg/8168EEF.cfg @@ -0,0 +1,53 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +;VID = 10 EC +;DID = 81 68 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +;CONFIG0 = 00 +CONFIG1 = 0F +;Asf Disable +CONFIGx = 1C +CONFIG3 = 60 +;Asf Enable +;CONFIGx = 5D +;CONFIG3 = E0 + +CONFIG4 = 14 +CONFIG5 = 82 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 8A +PMC = C3 FF +ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +LEDCFG = 98 CA +;Prefetchable memory access. Non-Prefetchable set to 04H, Prefetchable set to 0CH +PREFETCHABLE = 04 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 +VERSION = 1.031 + + diff --git a/external/cache/sources/linuxpg/8168EL.cfg b/external/cache/sources/linuxpg/8168EL.cfg new file mode 100644 index 0000000..6b9b5ab --- /dev/null +++ b/external/cache/sources/linuxpg/8168EL.cfg @@ -0,0 +1,48 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +VID = 10 EC +DID = 81 68 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +CONFIG0 = 00 +CONFIG1 = CF +CONFIGx = 3C +CONFIG3 = 60 +CONFIG4 = 14 +CONFIG5 = 82 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 8A +PMC = C3 FF +ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +;LEDCFG = 0C A9 +;Prefetchable memory access. Non-Prefetchable set to 04H, Prefetchable set to 0CH +PREFETCHABLE = 04 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 +VERSION = 1.031 + + diff --git a/external/cache/sources/linuxpg/8168EL.map b/external/cache/sources/linuxpg/8168EL.map new file mode 100644 index 0000000..e0975e8 --- /dev/null +++ b/external/cache/sources/linuxpg/8168EL.map @@ -0,0 +1,32 @@ +29 81 00 E0 4C 68 00 01 EC 10 68 81 EC 10 23 01 +01 00 00 00 68 4C E0 00 CA C9 30 FF 18 51 00 18 +52 CF 18 53 3C 18 54 60 18 55 14 18 56 82 50 42 +C3 FF 40 30 00 FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF \ No newline at end of file diff --git a/external/cache/sources/linuxpg/8168ELEF.cfg b/external/cache/sources/linuxpg/8168ELEF.cfg new file mode 100644 index 0000000..dfa85f2 --- /dev/null +++ b/external/cache/sources/linuxpg/8168ELEF.cfg @@ -0,0 +1,51 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +;VID = 10 EC +;DID = 81 68 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +CONFIG0 = 00 +CONFIG1 = CF +CONFIGx = 3C +CONFIG3 = 60 +CONFIG4 = 14 +CONFIG5 = 82 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 8A +PMC = C3 FF +ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +;LEDCFG = 0C A9 +;Prefetchable memory access. Non-Prefetchable set to 04H, Prefetchable set to 0CH +PREFETCHABLE = 04 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;LANCFG +;BIT 1:PHY Disable +;BIT 31:Clear LANCFG +;LANCFG = 00 00 00 00 +VERSION = 1.031 diff --git a/external/cache/sources/linuxpg/8168EPEF.cfg b/external/cache/sources/linuxpg/8168EPEF.cfg new file mode 100644 index 0000000..3151477 --- /dev/null +++ b/external/cache/sources/linuxpg/8168EPEF.cfg @@ -0,0 +1,78 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +;VID = 10 EC +;DID = 81 68 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +;CONFIG0 = 00 +;CONFIG1 = CF +CONFIGx = 3C +;CONFIG3 = 60 +;CONFIG4 = 14 +;CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +;CONFIG7 = 07 +;PMC = C3 FF +;ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +;LEDCFG = 0C A9 +;Prefetchable memory access. Non-Prefetchable set to 04H, Prefetchable set to 0CH +PREFETCHABLE = 04 +;ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;LANCFG +;BIT 1:PHY Disable BIT 2:Link OK +;BIT 31:Clear LANCFG +;LANCFG = 00 00 00 00 + +;Multi Function Configuration. +;Enable Multi function set to 01H, Disable Multi function set to 00H +;MULTIFUN = 01 + +;Link Capability +;PHYGBCR = 02 00 +;PHYANAR = 01 E1 + +;LEDSUBCFG +;Please make sure CONFIGX LED low power bit enabled +;(IO reg offset 0x53 bit 2 set to 0) before modifying LEDSUBCFG +;BIT 0:LED0 Low Power Enable in D3cold BIT 1:LED1 Low Power Enable in D3cold +;BIT 2:LED2 Low Power Enable in D3cold +;BIT 3:LED0 Preboot Enable BIT 4: LED1 Preboot Enable +;BIT 5:LED2 Preboot Enable +;LEDSUBCFG = 00 + +;EHCI PMC +;Enable EHCI PME_D3cold & PME_D3hot support in PMC +;Please Do Not program this item if system does not support modern standby. +EHCIPMC = C3 FF + +;Secure boot +;SECUREBOOT = 01 +VERSION = 1.031 + diff --git a/external/cache/sources/linuxpg/8168F.cfg b/external/cache/sources/linuxpg/8168F.cfg new file mode 100644 index 0000000..6b9b5ab --- /dev/null +++ b/external/cache/sources/linuxpg/8168F.cfg @@ -0,0 +1,48 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +VID = 10 EC +DID = 81 68 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +CONFIG0 = 00 +CONFIG1 = CF +CONFIGx = 3C +CONFIG3 = 60 +CONFIG4 = 14 +CONFIG5 = 82 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 8A +PMC = C3 FF +ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +;LEDCFG = 0C A9 +;Prefetchable memory access. Non-Prefetchable set to 04H, Prefetchable set to 0CH +PREFETCHABLE = 04 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 +VERSION = 1.031 + + diff --git a/external/cache/sources/linuxpg/8168F.map b/external/cache/sources/linuxpg/8168F.map new file mode 100644 index 0000000..e0975e8 --- /dev/null +++ b/external/cache/sources/linuxpg/8168F.map @@ -0,0 +1,32 @@ +29 81 00 E0 4C 68 00 01 EC 10 68 81 EC 10 23 01 +01 00 00 00 68 4C E0 00 CA C9 30 FF 18 51 00 18 +52 CF 18 53 3C 18 54 60 18 55 14 18 56 82 50 42 +C3 FF 40 30 00 FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF \ No newline at end of file diff --git a/external/cache/sources/linuxpg/8168FB.cfg b/external/cache/sources/linuxpg/8168FB.cfg new file mode 100644 index 0000000..58fb413 --- /dev/null +++ b/external/cache/sources/linuxpg/8168FB.cfg @@ -0,0 +1,49 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +VID = 10 EC +DID = 81 68 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +CONFIG0 = 00 +CONFIG1 = CF +CONFIGx = 3C +CONFIG3 = 60 +CONFIG4 = 14 +CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +CONFIG7 = 07 +PMC = C3 FF +ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +;LEDCFG = 0C A9 +;Prefetchable memory access. Non-Prefetchable set to 04H, Prefetchable set to 0CH +PREFETCHABLE = 04 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 +VERSION = 1.031 + + diff --git a/external/cache/sources/linuxpg/8168FB.map b/external/cache/sources/linuxpg/8168FB.map new file mode 100644 index 0000000..b37725e --- /dev/null +++ b/external/cache/sources/linuxpg/8168FB.map @@ -0,0 +1,32 @@ +29 81 00 E0 4C 68 00 01 EC 10 68 81 EC 10 23 01 +01 00 00 00 68 4C E0 00 CA C9 30 FF 18 51 00 18 +52 CF 18 53 3C 18 54 60 18 55 14 18 56 02 50 42 +C3 FF 40 30 00 FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF \ No newline at end of file diff --git a/external/cache/sources/linuxpg/8168FBEF.cfg b/external/cache/sources/linuxpg/8168FBEF.cfg new file mode 100644 index 0000000..d90c7da --- /dev/null +++ b/external/cache/sources/linuxpg/8168FBEF.cfg @@ -0,0 +1,57 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +;VID = 10 EC +;DID = 81 68 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +CONFIG0 = 00 +CONFIG1 = CF +CONFIGx = 3C +CONFIG3 = 60 +CONFIG4 = 14 +CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +;CONFIG7 = 07 +PMC = C3 FF +ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +;LEDCFG = 0C A9 +;Prefetchable memory access. Non-Prefetchable set to 04H, Prefetchable set to 0CH +PREFETCHABLE = 04 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;LANCFG +;BIT 0:LAN Disable BIT 1:PHY Disable +;BIT 31:Clear LANCFG +;LANCFG = 00 00 00 00 + +;Link Capability +;PHYGBCR = 03 00 +;PHYANAR = 01 E1 +VERSION = 1.031 + diff --git a/external/cache/sources/linuxpg/8168FEF.cfg b/external/cache/sources/linuxpg/8168FEF.cfg new file mode 100644 index 0000000..3e20d5e --- /dev/null +++ b/external/cache/sources/linuxpg/8168FEF.cfg @@ -0,0 +1,53 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +;VID = 10 EC +;DID = 81 68 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +CONFIG0 = 00 +CONFIG1 = CF +CONFIGx = 3C +CONFIG3 = 60 +CONFIG4 = 14 +CONFIG5 = 82 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 8A +PMC = C3 FF +ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +;LEDCFG = 0C A9 +;Prefetchable memory access. Non-Prefetchable set to 04H, Prefetchable set to 0CH +PREFETCHABLE = 04 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;LANCFG +;BIT 1:PHY Disable +;BIT 31:Clear LANCFG +;LANCFG = 00 00 00 00 +VERSION = 1.031 + + diff --git a/external/cache/sources/linuxpg/8168FPEF.cfg b/external/cache/sources/linuxpg/8168FPEF.cfg new file mode 100644 index 0000000..00428ca --- /dev/null +++ b/external/cache/sources/linuxpg/8168FPEF.cfg @@ -0,0 +1,80 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +;VID = 10 EC +;DID = 81 68 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +;CONFIG0 = 00 +;CONFIG1 = CF +CONFIGx = 3C +;CONFIG3 = 60 +;CONFIG4 = 14 +;CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +;CONFIG7 = 07 +;PMC = C3 FF +;ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +;LEDCFG = 0C A9 +;ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;LANCFG +;BIT 0:LAN Disable BIT 1:PHY Disable BIT 2:Link OK +;BIT 31:Clear LANCFG +;LANCFG = 00 00 00 00 + +;Link Capability +;PHYGBCR = 02 00 +;PHYANAR = 01 E1 + +;LEDSUBCFG +;Please make sure CONFIGX LED low power bit enabled +;(IO reg offset 0x53 bit 2 set to 0) before modifying LEDSUBCFG +;BIT 0:LED0 Low Power Enable in D3cold BIT 1:LED1 Low Power Enable in D3cold +;BIT 2:LED2 Low Power Enable in D3cold +;BIT 3:LED0 Preboot Enable BIT 4: LED1 Preboot Enable +;BIT 5:LED2 Preboot Enable +;LEDSUBCFG = 00 + +;Disable: 00, Enable: 01 +;UPS mode power saving +;UPSMODEPWRSAVING = 00 +;Secure boot +;SECUREBOOT = 01 + +;EHCI PMC +;Enable EHCI PME_D3cold & PME_D3hot support in PMC +EHCIPMC = C3 FF + +;PCIE Link Capability +;LINKPCIEGEN = 11 + +;Disable multi-function X +;DISABLEFUNCX = 00 +VERSION = 1.031 + diff --git a/external/cache/sources/linuxpg/8168G.cfg b/external/cache/sources/linuxpg/8168G.cfg new file mode 100644 index 0000000..f1f4394 --- /dev/null +++ b/external/cache/sources/linuxpg/8168G.cfg @@ -0,0 +1,50 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +VID = 10 EC +DID = 81 68 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +;CONFIG0 = 00 +;CONFIG1 = CF +CONFIGx = 3C +;CONFIG3 = 60 +;CONFIG4 = 14 +;CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +;CONFIG7 = 07 +;PMC = C3 FF +;ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +;LEDCFG = 0C A9 +;Prefetchable memory access. Non-Prefetchable set to 04H, Prefetchable set to 0CH +PREFETCHABLE = 04 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;DISFUNCXIOBAR = 00 +VERSION = 1.031 + diff --git a/external/cache/sources/linuxpg/8168G.map b/external/cache/sources/linuxpg/8168G.map new file mode 100644 index 0000000..7661379 --- /dev/null +++ b/external/cache/sources/linuxpg/8168G.map @@ -0,0 +1,32 @@ +29 81 00 E0 4C 68 00 01 EC 10 68 81 EC 10 23 01 +01 00 00 00 68 4C E0 00 CA C9 30 FF 18 51 00 18 +52 CF 18 53 3C 18 54 62 18 55 14 18 56 02 50 42 +C3 FF 40 30 00 FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF \ No newline at end of file diff --git a/external/cache/sources/linuxpg/8168GEF.cfg b/external/cache/sources/linuxpg/8168GEF.cfg new file mode 100644 index 0000000..3f4d818 --- /dev/null +++ b/external/cache/sources/linuxpg/8168GEF.cfg @@ -0,0 +1,59 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +;VID = 10 EC +;DID = 81 68 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +;CONFIG0 = 00 +;CONFIG1 = CF +CONFIGx = 3C +;CONFIG3 = 60 +;CONFIG4 = 14 +;CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +;CONFIG7 = 07 +;PMC = C3 FF +;ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +;LEDCFG = 0C A9 +;Prefetchable memory access. Non-Prefetchable set to 04H, Prefetchable set to 0CH +PREFETCHABLE = 04 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;LANCFG +;BIT 0:LAN Disable(32pin chip not support) BIT 1:PHY Disable BIT 2:Link OK +;BIT 31:Clear LANCFG +;LANCFG = 00 00 00 00 + +;Link Capability +;PHYGBCR = 02 00 +;PHYANAR = 01 E1 + +;DISFUNCXIOBAR = 00 +VERSION = 1.031 + diff --git a/external/cache/sources/linuxpg/8168GU.cfg b/external/cache/sources/linuxpg/8168GU.cfg new file mode 100644 index 0000000..1680efc --- /dev/null +++ b/external/cache/sources/linuxpg/8168GU.cfg @@ -0,0 +1,49 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +VID = 10 EC +DID = 81 68 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +;CONFIG0 = 00 +;CONFIG1 = CF +CONFIGx = 3C +;CONFIG3 = 60 +;CONFIG4 = 14 +;CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +;CONFIG7 = 07 +;PMC = C3 FF +;ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +;LEDCFG = 0C A9 +;Prefetchable memory access. Non-Prefetchable set to 04H, Prefetchable set to 0CH +PREFETCHABLE = 04 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;DISFUNCXIOBAR = 00 +VERSION = 1.031 diff --git a/external/cache/sources/linuxpg/8168GU.map b/external/cache/sources/linuxpg/8168GU.map new file mode 100644 index 0000000..d6776d7 --- /dev/null +++ b/external/cache/sources/linuxpg/8168GU.map @@ -0,0 +1,8 @@ +29 81 00 E0 4C 68 00 02 EC 10 68 81 EC 10 23 01 +00 E0 4C 68 00 00 00 01 39 ED 3F FF 40 18 04 19 +4C 2A 02 FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF \ No newline at end of file diff --git a/external/cache/sources/linuxpg/8168GUEF.cfg b/external/cache/sources/linuxpg/8168GUEF.cfg new file mode 100644 index 0000000..34b7d40 --- /dev/null +++ b/external/cache/sources/linuxpg/8168GUEF.cfg @@ -0,0 +1,58 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +;VID = 10 EC +;DID = 81 68 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +;CONFIG0 = 00 +;CONFIG1 = CF +CONFIGx = 3C +;CONFIG3 = 60 +;CONFIG4 = 14 +;CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +;CONFIG7 = 07 +;PMC = C3 FF +;ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +;LEDCFG = 0C A9 +;Prefetchable memory access. Non-Prefetchable set to 04H, Prefetchable set to 0CH +PREFETCHABLE = 04 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;LANCFG +;BIT 0:LAN Disable BIT 1:PHY Disable BIT 2:Link OK +;BIT 31:Clear LANCFG +;LANCFG = 00 00 00 00 + +;Link Capability +;PHYGBCR = 02 00 +;PHYANAR = 01 E1 + +;DISFUNCXIOBAR = 00 +VERSION = 1.031 diff --git a/external/cache/sources/linuxpg/8168H.cfg b/external/cache/sources/linuxpg/8168H.cfg new file mode 100644 index 0000000..64038ee --- /dev/null +++ b/external/cache/sources/linuxpg/8168H.cfg @@ -0,0 +1,49 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +;VID = 10 EC +;DID = 81 68 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +;CONFIG0 = 00 +;CONFIG1 = CF +;CONFIGx = 3C +;CONFIG3 = 60 +;CONFIG4 = 14 +;CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +;CONFIG7 = 37 +;PMC = C3 FF +;ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +;LEDCFG = 0C A9 +;Prefetchable memory access. Non-Prefetchable set to 04H, Prefetchable set to 0CH +;PREFETCHABLE = 04 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;DISFUNCXIOBAR = 00 +VERSION = 1.031 diff --git a/external/cache/sources/linuxpg/8168H.map b/external/cache/sources/linuxpg/8168H.map new file mode 100644 index 0000000..feebe34 --- /dev/null +++ b/external/cache/sources/linuxpg/8168H.map @@ -0,0 +1 @@ +29 81 00 E0 4C 68 00 01 EC 10 68 81 EC 10 23 01 00 E0 4C 68 00 00 00 01 84 FA 3F FF 19 4C 30 02 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF \ No newline at end of file diff --git a/external/cache/sources/linuxpg/8168HEF.cfg b/external/cache/sources/linuxpg/8168HEF.cfg new file mode 100644 index 0000000..8174407 --- /dev/null +++ b/external/cache/sources/linuxpg/8168HEF.cfg @@ -0,0 +1,65 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +;VID = 10 EC +;DID = 81 68 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +;CONFIG0 = 00 +;CONFIG1 = CF +;CONFIGx = 3C +;CONFIG3 = 60 +;CONFIG4 = 14 +;CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +CONFIG7 = 07 +;PMC = C3 FF +;ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +;LEDCFG = 0C A9 +;Prefetchable memory access. Non-Prefetchable set to 04H, Prefetchable set to 0CH +;PREFETCHABLE = 04 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;LANCFG +;BIT 0:LAN Disable BIT 1:PHY Disable BIT 2:Link OK +;BIT 31:Clear LANCFG +;LANCFG = 00 00 00 00 + +;Link Capability +;PHYGBCR = 02 00 +;PHYANAR = 01 E1 +;SpeedUp Capability +;Enable GPHY speed up by MAC set to 29H, Disable GPHY speed up by MAC set to 21H +;PHYPWRFUN = 21 + +;CTAPSHORT +;Enable set to 01H, Disable set to 00H +;CTAPSHORT = 01 + +;DISFUNCXIOBAR = 00 +VERSION = 1.031 diff --git a/external/cache/sources/linuxpg/8168K.cfg b/external/cache/sources/linuxpg/8168K.cfg new file mode 100644 index 0000000..64038ee --- /dev/null +++ b/external/cache/sources/linuxpg/8168K.cfg @@ -0,0 +1,49 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +;VID = 10 EC +;DID = 81 68 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +;CONFIG0 = 00 +;CONFIG1 = CF +;CONFIGx = 3C +;CONFIG3 = 60 +;CONFIG4 = 14 +;CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +;CONFIG7 = 37 +;PMC = C3 FF +;ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +;LEDCFG = 0C A9 +;Prefetchable memory access. Non-Prefetchable set to 04H, Prefetchable set to 0CH +;PREFETCHABLE = 04 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;DISFUNCXIOBAR = 00 +VERSION = 1.031 diff --git a/external/cache/sources/linuxpg/8168K.map b/external/cache/sources/linuxpg/8168K.map new file mode 100644 index 0000000..ced2e61 --- /dev/null +++ b/external/cache/sources/linuxpg/8168K.map @@ -0,0 +1,8 @@ +29 81 00 E0 4C 68 00 01 EC 10 68 81 EC 10 23 01 +00 E0 4C 68 00 00 00 01 84 FA 3F FF 19 4C 30 02 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF \ No newline at end of file diff --git a/external/cache/sources/linuxpg/8168KB.cfg b/external/cache/sources/linuxpg/8168KB.cfg new file mode 100644 index 0000000..1fdc787 --- /dev/null +++ b/external/cache/sources/linuxpg/8168KB.cfg @@ -0,0 +1,72 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +VID = 10 EC +DID = 81 62 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +;CONFIG0 = 00 +;CONFIG1 = CF +CONFIGx = 3C +;For add-on device, please set CONFIG3 to 60H +;CONFIG3 = 60 +;CONFIG4 = 14 +;CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +;CONFIG7 = 17 +;PMC = C3 FF +;ROMBAR = 00 +;LEDXCFG = High-Byte Low-Byte +;LEDX Bit 11: Low power mode enable +;LEDX Bit 10: Preboot enable +;Please make sure CONFIGx LED low power bit enabled +;(IO reg offset 0x53 bit 2 set to 0) before modifying LED low power mode or LED preboot +;LED0CFG = 02 01 +;LED1CFG = 02 02 +;LED2CFG = 02 08 +;LED3CFG = 02 20 +;LED Feature Functions +;Set BIT 0 to 0 : V1 led table. +;Set BIT 0 to 1 : V2 led table. +;BIT 1 to BIT 7 : Reserved +;LEDFEATUREFUNC = 60 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;MDI swap +;MDI non-swap set to 00H, MDI swap set to 20H +;MDISWAP = 00 + +;Tx polarity swap +;BIT 7: P3 non-swap set to 1, P3 swap set to 0 +;BIT 6: P2 non-swap set to 0, P2 swap set to 1 +;BIT 5: P1 non-swap set to 1, P1 swap set to 0 +;BIT 4: P0 non-swap set to 0, P0 swap set to 1 +;BIT 0 to BIT 3 : Reserved +;TXPOLSWAP = A0 + +;DISFUNCXIOBAR = 00 +VERSION = 1.031 diff --git a/external/cache/sources/linuxpg/8168KBEF.cfg b/external/cache/sources/linuxpg/8168KBEF.cfg new file mode 100644 index 0000000..2cf22e4 --- /dev/null +++ b/external/cache/sources/linuxpg/8168KBEF.cfg @@ -0,0 +1,77 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +;VID = 10 EC +;DID = 81 62 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +;CONFIG0 = 00 +;CONFIG1 = CF +CONFIGx = 3C +;For add-on device, please set CONFIG3 to 60H +;CONFIG3 = 60 +;CONFIG4 = 14 +;CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +CONFIG7 = 07 +;PMC = C3 FF +;ROMBAR = 00 +;LEDXCFG = High-Byte Low-Byte +;LEDX Bit 11: Low power mode enable +;LEDX Bit 10: Preboot enable +;Please make sure CONFIGx LED low power bit enabled +;(IO reg offset 0x53 bit 2 set to 0) before modifying LED low power mode or LED preboot +;LED0CFG = 02 01 +;LED1CFG = 02 02 +;LED2CFG = 02 08 +;LED3CFG = 02 20 +;LED Feature Functions +;Set BIT 0 to 0 : V1 led table. +;Set BIT 0 to 1 : V2 led table. +;BIT 1 to BIT 7 : Reserved +;LEDFEATUREFUNC = 60 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;LANCFG +;BIT 0:LAN Disable BIT 1:PHY Disable BIT 2:Link OK +;BIT 31:Clear LANCFG +;LANCFG = 00 00 00 00 + +;MDI swap +;MDI non-swap set to 00H, MDI swap set to 20H +;MDISWAP = 00 + +;Tx polarity swap +;BIT 7: P3 non-swap set to 1, P3 swap set to 0 +;BIT 6: P2 non-swap set to 0, P2 swap set to 1 +;BIT 5: P1 non-swap set to 1, P1 swap set to 0 +;BIT 4: P0 non-swap set to 0, P0 swap set to 1 +;BIT 0 to BIT 3 : Reserved +;TXPOLSWAP = A0 + +;DISFUNCXIOBAR = 00 +VERSION = 1.031 diff --git a/external/cache/sources/linuxpg/8168KEF.cfg b/external/cache/sources/linuxpg/8168KEF.cfg new file mode 100644 index 0000000..8174407 --- /dev/null +++ b/external/cache/sources/linuxpg/8168KEF.cfg @@ -0,0 +1,65 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +;VID = 10 EC +;DID = 81 68 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +;CONFIG0 = 00 +;CONFIG1 = CF +;CONFIGx = 3C +;CONFIG3 = 60 +;CONFIG4 = 14 +;CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +CONFIG7 = 07 +;PMC = C3 FF +;ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +;LEDCFG = 0C A9 +;Prefetchable memory access. Non-Prefetchable set to 04H, Prefetchable set to 0CH +;PREFETCHABLE = 04 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;LANCFG +;BIT 0:LAN Disable BIT 1:PHY Disable BIT 2:Link OK +;BIT 31:Clear LANCFG +;LANCFG = 00 00 00 00 + +;Link Capability +;PHYGBCR = 02 00 +;PHYANAR = 01 E1 +;SpeedUp Capability +;Enable GPHY speed up by MAC set to 29H, Disable GPHY speed up by MAC set to 21H +;PHYPWRFUN = 21 + +;CTAPSHORT +;Enable set to 01H, Disable set to 00H +;CTAPSHORT = 01 + +;DISFUNCXIOBAR = 00 +VERSION = 1.031 diff --git a/external/cache/sources/linuxpg/8168L.cfg b/external/cache/sources/linuxpg/8168L.cfg new file mode 100644 index 0000000..64038ee --- /dev/null +++ b/external/cache/sources/linuxpg/8168L.cfg @@ -0,0 +1,49 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +;VID = 10 EC +;DID = 81 68 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +;CONFIG0 = 00 +;CONFIG1 = CF +;CONFIGx = 3C +;CONFIG3 = 60 +;CONFIG4 = 14 +;CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +;CONFIG7 = 37 +;PMC = C3 FF +;ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +;LEDCFG = 0C A9 +;Prefetchable memory access. Non-Prefetchable set to 04H, Prefetchable set to 0CH +;PREFETCHABLE = 04 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;DISFUNCXIOBAR = 00 +VERSION = 1.031 diff --git a/external/cache/sources/linuxpg/8168L.map b/external/cache/sources/linuxpg/8168L.map new file mode 100644 index 0000000..ced2e61 --- /dev/null +++ b/external/cache/sources/linuxpg/8168L.map @@ -0,0 +1,8 @@ +29 81 00 E0 4C 68 00 01 EC 10 68 81 EC 10 23 01 +00 E0 4C 68 00 00 00 01 84 FA 3F FF 19 4C 30 02 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF \ No newline at end of file diff --git a/external/cache/sources/linuxpg/8168LEF.cfg b/external/cache/sources/linuxpg/8168LEF.cfg new file mode 100644 index 0000000..8174407 --- /dev/null +++ b/external/cache/sources/linuxpg/8168LEF.cfg @@ -0,0 +1,65 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +;VID = 10 EC +;DID = 81 68 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +;CONFIG0 = 00 +;CONFIG1 = CF +;CONFIGx = 3C +;CONFIG3 = 60 +;CONFIG4 = 14 +;CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +CONFIG7 = 07 +;PMC = C3 FF +;ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +;LEDCFG = 0C A9 +;Prefetchable memory access. Non-Prefetchable set to 04H, Prefetchable set to 0CH +;PREFETCHABLE = 04 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;LANCFG +;BIT 0:LAN Disable BIT 1:PHY Disable BIT 2:Link OK +;BIT 31:Clear LANCFG +;LANCFG = 00 00 00 00 + +;Link Capability +;PHYGBCR = 02 00 +;PHYANAR = 01 E1 +;SpeedUp Capability +;Enable GPHY speed up by MAC set to 29H, Disable GPHY speed up by MAC set to 21H +;PHYPWRFUN = 21 + +;CTAPSHORT +;Enable set to 01H, Disable set to 00H +;CTAPSHORT = 01 + +;DISFUNCXIOBAR = 00 +VERSION = 1.031 diff --git a/external/cache/sources/linuxpg/8169.cfg b/external/cache/sources/linuxpg/8169.cfg new file mode 100644 index 0000000..ca03dc2 --- /dev/null +++ b/external/cache/sources/linuxpg/8169.cfg @@ -0,0 +1,39 @@ +NODEID = 00 E0 4C 69 00 01 +;ENDID = 00 E0 4C 69 FF FF +VID = 10 EC +DID = 81 69 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +MNGNT = 20 +MXLAT = 40 +CONFIGx = 01 +CONFIG3 = A1 +CONFIG0 = 15 +CONFIG1 = CD +CONFIG4 = 80 +CONFIG5 = 13 +PMC = C2 F7 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Seconds +VERSION = 1.031 + diff --git a/external/cache/sources/linuxpg/8169CB.cfg b/external/cache/sources/linuxpg/8169CB.cfg new file mode 100644 index 0000000..761e024 --- /dev/null +++ b/external/cache/sources/linuxpg/8169CB.cfg @@ -0,0 +1,57 @@ +NODEID = 00 E0 4C 69 00 01 +;ENDID = 00 E0 4C 69 FF FF +VID = 10 EC +DID = 81 69 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +MNGNT = 20 +MXLAT = 40 +CONFIGx = 01 +CONFIG3 = AD +CONFIG0 = 15 +CONFIG1 = CD +CONFIG4 = 80 +CONFIG5 = 13 +PMC = C2 F7 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Seconds + +CISPointer=02 01 +CISDATA=13 03 43 49 53 \ ;Link Target=CIS + 20 04 00 00 4C 02 \ ;JEDEC ID=0x0 Manufacturer ID Realtek=0x024C + 21 02 06 00 \ ;function class ID, 06=NIC + 22 02 01 02 \ ;LAN_TEK 02=Ethernet + 22 05 02 80 96 98 00 \ ;LAN_TEK Speed=10Mhz + 22 05 02 00 E1 F5 05 \ ;LAN_TEK Speed=100Mhz + 22 05 02 00 CA 9A 3B \ ;LAN_TEK Speed=1000Mhz + 22 08 04 06 00 E0 4C 69 00 10 \ ;LAN_TEK ID=00e04c690010 + 1C 02 02 FF \ + 07 06 11 00 80 01 00 00 \ ;base address register + 07 06 82 00 80 01 00 00 \ + 04 06 03 02 10 00 00 00 \ ;configuration tuple + 05 09 01 B8 04 B0 BC 8E 0A FB 04 \ ;configuration table + 15 14 05 00 52 65 61 6C 74 65 6B 00 \ ;Manufacturer String=Realtek + 52 74 6C 38 31 36 39 00 FF ;Product String=Rtl8169 +VERSION = 1.031 + + diff --git a/external/cache/sources/linuxpg/8169X.bin b/external/cache/sources/linuxpg/8169X.bin new file mode 100644 index 0000000..e3af674 Binary files /dev/null and b/external/cache/sources/linuxpg/8169X.bin differ diff --git a/external/cache/sources/linuxpg/8169X.map b/external/cache/sources/linuxpg/8169X.map new file mode 100644 index 0000000..3acf28c --- /dev/null +++ b/external/cache/sources/linuxpg/8169X.map @@ -0,0 +1,8 @@ +29 81 EC 10 69 81 EC 10 23 01 20 40 01 A1 00 E0 +4C 69 11 22 15 CD C2 F7 00 80 00 00 00 00 00 13 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 D8 B5 00 00 00 00 00 00 00 00 00 00 00 3F +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ No newline at end of file diff --git a/external/cache/sources/linuxpg/8401.cfg b/external/cache/sources/linuxpg/8401.cfg new file mode 100644 index 0000000..9bc7a20 --- /dev/null +++ b/external/cache/sources/linuxpg/8401.cfg @@ -0,0 +1,56 @@ +NODEID = 00 E0 4C 36 00 01 +;EndID = 00 E0 4C 36 FF FF +VID = 10 EC +DID = 81 36 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +CONFIG0 = 00 +CONFIG1 = 0F +CONFIGx = 3C +CONFIG3 = 62 +CONFIG4 = 14 +CONFIG5 = 02 +PMC = C3 FF +ROMBAR = 00 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 36 00 00 00 01 + +;PCI-E Parameter +C_PCIE0 = 04 01 +;0AH~0BH +C_PCIE1 = c1 86 80 02 00 00 11 3c 07 00 10 20 +;1AH~25H +C_PCIE2 = 76 00 63 01 01 FF 27 AA 03 02 20 +;26H~2BH 2DH~31H +C_PCIE3 = 80 02 00 20 10 00 21 00 10 00 21 00 00 80 +;34H~3EH 40H~42H +C_PCIE4 = 80 00 20 00 00 00 +;46H~49H 52~53H +C_EPHY = 71 22 98 AF 6B 39 35 +;43H~45H 54H~57H +VERSION = 1.031 + + diff --git a/external/cache/sources/linuxpg/8401.map b/external/cache/sources/linuxpg/8401.map new file mode 100644 index 0000000..4261073 --- /dev/null +++ b/external/cache/sources/linuxpg/8401.map @@ -0,0 +1,32 @@ +29 81 EC 10 36 81 EC 10 23 01 04 01 3C 62 00 E0 +4C 36 00 00 00 0F C3 FF 14 02 C1 86 80 02 00 00 +11 3C 07 00 10 20 76 00 63 01 01 FF 00 27 AA 03 +02 20 38 AC 80 02 00 20 10 00 21 00 10 00 21 3F +00 00 80 71 22 98 80 00 20 00 E0 00 36 4C 00 00 +01 00 00 00 AF 6B 39 35 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/external/cache/sources/linuxpg/8401EF.cfg b/external/cache/sources/linuxpg/8401EF.cfg new file mode 100644 index 0000000..7ab90f1 --- /dev/null +++ b/external/cache/sources/linuxpg/8401EF.cfg @@ -0,0 +1,54 @@ +NODEID = 00 E0 4C 36 00 01 +;ENDID = 00 E0 4C 36 FF FF +;VID = 10 EC +;DID = 81 36 +SVID = 10 EC +SMID = 01 23 + +;If CR SVIDSMID is needed, please unmark CR_SVIDSMID +;CR_SVIDSMID = 10 EC 52 88 + +;Do not change following parameters without Realtek approval +CONFIG0 = 00 +CONFIG1 = 0F +;CONFIGx = 3C +CONFIG3 = 62 +CONFIG4 = 14 +;CONFIG5 = 02 +PMC = C3 FF +ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +LEDCFG = 00 00 +;Prefetchable memory access. Non-Prefetchable set to 04H, Prefetchable set to 0CH +PREFETCHABLE = 04 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;CR_SDIO = 20 +;ON 40 +;OFF 20 + +;EPHY = Address HIGH_BYTE LOW_BYTE ... +;EPHY = 03 00 FB + +;Serial Number in PCI Config Space +SN = 00 E0 4C 36 00 00 00 01 +VERSION = 1.031 diff --git a/external/cache/sources/linuxpg/8402.cfg b/external/cache/sources/linuxpg/8402.cfg new file mode 100644 index 0000000..d8ea486 --- /dev/null +++ b/external/cache/sources/linuxpg/8402.cfg @@ -0,0 +1,53 @@ +NODEID = 00 E0 4C 36 00 01 +;ENDID = 00 E0 4C 36 FF FF +VID = 10 EC +DID = 81 36 +SVID = 10 EC +SMID = 01 23 + +;If CR SVIDSMID is needed, please unmark CR_SVIDSMID +;CR_SVIDSMID = 10 EC 52 86 + +;Do not change following parameters without Realtek approval +CONFIG0 = 00 +CONFIG1 = CF +CONFIGx = 3C +CONFIG3 = 60 +CONFIG4 = 14 +CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +CONFIG7 = 07 +PMC = C3 FF +ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +;LEDCFG = 0C A9 +;Prefetchable memory access. Non-Prefetchable set to 04H, Prefetchable set to 0CH +PREFETCHABLE = 04 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 36 00 00 00 01 + +;DISFUNCXIOBAR = 00 +VERSION = 1.031 + diff --git a/external/cache/sources/linuxpg/8402.map b/external/cache/sources/linuxpg/8402.map new file mode 100644 index 0000000..37947d6 --- /dev/null +++ b/external/cache/sources/linuxpg/8402.map @@ -0,0 +1,32 @@ +29 81 00 E0 4C 36 00 01 EC 10 36 81 EC 10 23 01 +01 00 00 00 36 4C E0 00 CA C9 30 FF 18 51 00 18 +52 CF 18 53 3C 18 54 60 18 55 14 18 56 02 50 42 +C3 FF 40 30 00 FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF \ No newline at end of file diff --git a/external/cache/sources/linuxpg/8402EF.cfg b/external/cache/sources/linuxpg/8402EF.cfg new file mode 100644 index 0000000..c1665ec --- /dev/null +++ b/external/cache/sources/linuxpg/8402EF.cfg @@ -0,0 +1,58 @@ +NODEID = 00 E0 4C 36 00 01 +;ENDID = 00 E0 4C 36 FF FF +;VID = 10 EC +;DID = 81 36 +SVID = 10 EC +SMID = 01 23 + +;If CR SVIDSMID is needed, please unmark CR_SVIDSMID +;CR_SVIDSMID = 10 EC 52 86 + +;Do not change following parameters without Realtek approval +CONFIG0 = 00 +CONFIG1 = CF +CONFIGx = 3C +CONFIG3 = 60 +CONFIG4 = 14 +CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +;CONFIG7 = 07 +PMC = C3 FF +ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +;LEDCFG = 0C A9 +;Prefetchable memory access. Non-Prefetchable set to 04H, Prefetchable set to 0CH +PREFETCHABLE = 04 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 36 00 00 00 01 + +;LANCFG +;BIT 0:LAN Disable BIT 1:PHY Disable +;BIT 31:Clear LANCFG +;LANCFG = 00 00 00 00 + +;DISFUNCXIOBAR = 00 +VERSION = 1.031 + diff --git a/external/cache/sources/linuxpg/8411.cfg b/external/cache/sources/linuxpg/8411.cfg new file mode 100644 index 0000000..3dc2bad --- /dev/null +++ b/external/cache/sources/linuxpg/8411.cfg @@ -0,0 +1,53 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +VID = 10 EC +DID = 81 68 +SVID = 10 EC +SMID = 01 23 + +;If CR SVIDSMID is needed, please unmark CR_SVIDSMID +;CR_SVIDSMID = 10 EC 52 89 + +;Do not change following parameters without Realtek approval +CONFIG0 = 00 +CONFIG1 = CF +CONFIGx = 3C +CONFIG3 = 60 +CONFIG4 = 14 +CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +CONFIG7 = 07 +PMC = C3 FF +ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +;LEDCFG = 0C A9 +;Prefetchable memory access. Non-Prefetchable set to 04H, Prefetchable set to 0CH +PREFETCHABLE = 04 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;DISFUNCXIOBAR = 00 +VERSION = 1.031 + diff --git a/external/cache/sources/linuxpg/8411.map b/external/cache/sources/linuxpg/8411.map new file mode 100644 index 0000000..b37725e --- /dev/null +++ b/external/cache/sources/linuxpg/8411.map @@ -0,0 +1,32 @@ +29 81 00 E0 4C 68 00 01 EC 10 68 81 EC 10 23 01 +01 00 00 00 68 4C E0 00 CA C9 30 FF 18 51 00 18 +52 CF 18 53 3C 18 54 60 18 55 14 18 56 02 50 42 +C3 FF 40 30 00 FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF \ No newline at end of file diff --git a/external/cache/sources/linuxpg/8411B.cfg b/external/cache/sources/linuxpg/8411B.cfg new file mode 100644 index 0000000..abc0fcd --- /dev/null +++ b/external/cache/sources/linuxpg/8411B.cfg @@ -0,0 +1,52 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +VID = 10 EC +DID = 81 68 +SVID = 10 EC +SMID = 01 23 + +;If CR SVIDSMID is needed, please unmark CR_SVIDSMID +;CR_SVIDSMID = 10 EC 52 87 + +;Do not change following parameters without Realtek approval +;CONFIG0 = 00 +;CONFIG1 = CF +CONFIGx = 3C +;CONFIG3 = 60 +;CONFIG4 = 14 +;CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +;CONFIG7 = 07 +;PMC = C3 FF +;ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +;LEDCFG = 0C A9 +;Prefetchable memory access. Non-Prefetchable set to 04H, Prefetchable set to 0CH +;PREFETCHABLE = 04 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;DISFUNCXIOBAR = 00 +VERSION = 1.031 diff --git a/external/cache/sources/linuxpg/8411B.map b/external/cache/sources/linuxpg/8411B.map new file mode 100644 index 0000000..5452be5 --- /dev/null +++ b/external/cache/sources/linuxpg/8411B.map @@ -0,0 +1,32 @@ +29 81 00 E0 4C 68 00 01 EC 10 68 81 EC 10 23 01 +00 E0 4C 68 00 00 00 01 48 FB 3F FF 19 4C 2C 02 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF \ No newline at end of file diff --git a/external/cache/sources/linuxpg/8411BEF.cfg b/external/cache/sources/linuxpg/8411BEF.cfg new file mode 100644 index 0000000..87a3c89 --- /dev/null +++ b/external/cache/sources/linuxpg/8411BEF.cfg @@ -0,0 +1,70 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +;VID = 10 EC +;DID = 81 68 +SVID = 10 EC +SMID = 01 23 + +;If CR SVIDSMID is needed, please unmark CR_SVIDSMID +;CR_SVIDSMID = 10 EC 52 87 + +;Do not change following parameters without Realtek approval +;CONFIG0 = 00 +;CONFIG1 = CF +CONFIGx = 3C +;CONFIG3 = 60 +;CONFIG4 = 14 +;CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +;CONFIG7 = 07 +;PMC = C3 FF +;ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +;LEDCFG = 0C A9 +;Prefetchable memory access. Non-Prefetchable set to 04H, Prefetchable set to 0CH +;PREFETCHABLE = 04 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;LANCFG +;BIT 0:LAN Disable BIT 1:PHY Disable BIT 2:Link OK +;BIT 31:Clear LANCFG +;LANCFG = 00 00 00 00 + +;Link Capability +;PHYGBCR = 02 00 +;PHYANAR = 01 E1 + +;LEDSUBCFG +;Please make sure CONFIGX LED low power bit enabled +;(IO reg offset 0x53 bit 2 set to 0) before modifying LEDSUBCFG +;BIT 0:LED0 Low Power Enable in D3cold BIT 1:LED1 Low Power Enable in D3cold +;BIT 2:LED2 Low Power Enable in D3cold +;BIT 3:LED0 Preboot Enable BIT 4: LED1 Preboot Enable +;BIT 5:LED2 Preboot Enable +;LEDSUBCFG = 00 + +;DISFUNCXIOBAR = 00 +VERSION = 1.031 diff --git a/external/cache/sources/linuxpg/8411EF.cfg b/external/cache/sources/linuxpg/8411EF.cfg new file mode 100644 index 0000000..9d0413b --- /dev/null +++ b/external/cache/sources/linuxpg/8411EF.cfg @@ -0,0 +1,58 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +;VID = 10 EC +;DID = 81 68 +SVID = 10 EC +SMID = 01 23 + +;If CR SVIDSMID is needed, please unmark CR_SVIDSMID +;CR_SVIDSMID = 10 EC 52 89 + +;Do not change following parameters without Realtek approval +CONFIG0 = 00 +CONFIG1 = CF +CONFIGx = 3C +CONFIG3 = 60 +CONFIG4 = 14 +CONFIG5 = 02 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 0A +;CONFIG7 = 07 +PMC = C3 FF +ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +;LEDCFG = 0C A9 +;Prefetchable memory access. Non-Prefetchable set to 04H, Prefetchable set to 0CH +PREFETCHABLE = 04 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 + +;LANCFG +;BIT 0:LAN Disable BIT 1:PHY Disable +;BIT 31:Clear LANCFG +;LANCFG = 00 00 00 00 + +;DISFUNCXIOBAR = 00 +VERSION = 1.031 + diff --git a/external/cache/sources/linuxpg/DPFLASH.bin b/external/cache/sources/linuxpg/DPFLASH.bin new file mode 100644 index 0000000..c50f9e1 Binary files /dev/null and b/external/cache/sources/linuxpg/DPFLASH.bin differ diff --git a/external/cache/sources/linuxpg/Makefile b/external/cache/sources/linuxpg/Makefile new file mode 100644 index 0000000..797767b --- /dev/null +++ b/external/cache/sources/linuxpg/Makefile @@ -0,0 +1,26 @@ +# +# Makefile for the kernel character device drivers. +# + +# +# This file contains the font map for the default (hardware) font +# + +ifneq ($(KERNELRELEASE),) + obj-m := pgdrv.o +# EXTRA_CFLAGS += -DDEBUG +else + KERNELDIR ?= /lib/modules/$(shell uname -r)/build + PWD :=$(shell pwd) + +.PHONY:all +all: + $(MAKE) -C $(KERNELDIR) M=$(PWD) modules +# $(MAKE) -C $(KERNELDIR) M=$(PWD) CROSS_COMPILE=mipsel-linux- ARCH=mips modules + +.PHONY:clean +clean: + $(MAKE) -C $(KERNELDIR) M=$(PWD) clean +# $(MAKE) -C $(KERNELDIR) M=$(PWD) CROSS_COMPILE=mipsel-linux- ARCH=mips clean + +endif diff --git a/external/cache/sources/linuxpg/README b/external/cache/sources/linuxpg/README new file mode 100644 index 0000000..4b37998 --- /dev/null +++ b/external/cache/sources/linuxpg/README @@ -0,0 +1,46 @@ + This is the package for pgtool of Realtek. There are two methods to use + this tool. The method 1 is through a script file. However, you have to use + the Method 2 if the Method 1 doesn't work. + If you use the embedded system, you maybe have to build "pgdrv.ko" first + for the target platform. Please reference the Step 2 of Method 2. And the + steps may be different. + +Method 1: + Step 1: Run the script file to load the necessary elements. + # ./pgload.sh + + Step 2: Run the pgtool "rtnicpg". Use /h to show user guide. + # ./rtnicpg /h | more + + Step 3: Choose the cmd to pg. + Example: Read the EEPROM for the first NIC card. + # ./rtnicpg /r /eeprom /# 1 + + Step 4: Unload the elements of pgtool. + # rmmod pgdrv + + +Method 2: + Step 1: Unload all the NIC driver for Realtek. + # rmmod r8169 + # rmmod r8168 + # rmmod r8101 + + Step 2: Build the pgdrv.ko and install it. + # make clean all + # insmod pgdrv.ko + + Step 3: Run the pgtool "rtnicpg". Use /h to show user guide. + # ./rtnicpg /h | more + + Step 4: Choose the cmd to pg. + Example: Read the EEPROM for the first NIC card. + # ./rtnicpg /r /eeprom /# 1 + + Step 5: Remove the pgdrv. + # rmmod pgdrv + +[NOTICE] + 1. The applications are only for little-endian platform. + 2. Must login with "root". + 3. The NIC driver must be unload first or the pgdrv.ko cannot work. diff --git a/external/cache/sources/linuxpg/RTL8125BG(S)-CG_DataSheet_1.3.pdf b/external/cache/sources/linuxpg/RTL8125BG(S)-CG_DataSheet_1.3.pdf new file mode 100755 index 0000000..9cb4a73 Binary files /dev/null and b/external/cache/sources/linuxpg/RTL8125BG(S)-CG_DataSheet_1.3.pdf differ diff --git a/external/cache/sources/linuxpg/UserGuide.pdf b/external/cache/sources/linuxpg/UserGuide.pdf new file mode 100644 index 0000000..fa037f4 Binary files /dev/null and b/external/cache/sources/linuxpg/UserGuide.pdf differ diff --git a/external/cache/sources/linuxpg/pgdrv.c b/external/cache/sources/linuxpg/pgdrv.c new file mode 100644 index 0000000..280771e --- /dev/null +++ b/external/cache/sources/linuxpg/pgdrv.c @@ -0,0 +1,586 @@ +#include +#include +#include +#include +#include +#include +#include +#include // struct file_operations +#include // mmap +#include // kmalloc +#if LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0) +#include +#endif +#include +#include // copy_to_user +#include // copy_to_user +#include + +#include "pgdrv.h" + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) +#warning KERNEL_VERSION < 2.6.11 +#endif + +static DEV_INFO dev_info[MAX_DEV_NUM]; +static atomic_t dev_num; +static spinlock_t module_lock; +static int major = 0; +static unsigned long mmio = 0; + +module_param(major, int, S_IRUGO|S_IWUSR); +module_param(mmio, ulong, S_IRUGO|S_IWUSR); + +//static int dev_IoctlFun(struct inode *inode, struct file *pFile,unsigned int cmd, unsigned long arg) +static long dev_IoctlFun(struct file *pFile,unsigned int cmd, unsigned long arg) +{ + PPGDEV mydev; + int result; + + if (_IOC_TYPE(cmd) != RTL_IOC_MAGIC) + { + DbgFunPrint("Invalid command!!!"); + return -ENOTTY; + } + + mydev = (PPGDEV)pFile->private_data; + result = 0; + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,16) + if (down_interruptible(&mydev->dev_sem)) + { + DbgFunPrint("lock fail"); + return -ERESTARTSYS; + } +#else + if (mutex_lock_interruptible(&mydev->dev_mutex)) + { + DbgFunPrint("lock fail"); + return -ERESTARTSYS; + } +#endif + + switch(cmd) + { + case IOC_PCI_CONFIG: + { + PCI_CONFIG_RW pci_config; + + if (copy_from_user(&pci_config, (void __user *)arg, sizeof(PCI_CONFIG_RW))) + { + DbgFunPrint("copy_from_user fail"); + result = -EFAULT; + break; + } + + + if (pci_config.bRead==TRUE) + { + if (pci_config.size==1) + { + result = pci_read_config_byte(mydev->pdev, pci_config.addr, &pci_config.byte); + } + else if (pci_config.size==2) + { + result = pci_read_config_word(mydev->pdev, pci_config.addr, &pci_config.word); + } + else if (pci_config.size==4) + { + result = pci_read_config_dword(mydev->pdev, pci_config.addr, &pci_config.dword); + } + else + { + result = -EINVAL; + } + + if (result) + { + DbgFunPrint("Read PCI fail:%d",result); + break; + } + + if (copy_to_user((void __user *)arg , &pci_config, sizeof(PCI_CONFIG_RW))) + { + DbgFunPrint("copy_from_user fail"); + result = -EFAULT; + break; + } + } + else // write + { + if (pci_config.size==1) + { + result = pci_write_config_byte(mydev->pdev, pci_config.addr, pci_config.byte); + } + else if (pci_config.size==2) + { + result = pci_write_config_word(mydev->pdev, pci_config.addr, pci_config.word); + } + else if (pci_config.size==4) + { + result = pci_write_config_dword(mydev->pdev, pci_config.addr, pci_config.dword); + } + else + { + result = -EINVAL; + } + + if (result) + { + DbgFunPrint("Write PCI fail:%d",result); + break; + } + } +#if 0 + DebugPrint("bRead=%u, size=%d, addr=0x%02x , data=0x%08x", + pci_config.bRead, pci_config.size, + pci_config.addr, pci_config.dword); +#endif + break; + } + + case IOC_IOMEM_OFFSET: + if ( put_user(mydev->offset,(unsigned int __user *)arg) ) + { + DbgFunPrint("put_user fail"); + result = -EFAULT; + break; + } + break; + + case IOC_DEV_FUN: + if ( put_user(mydev->pdev->devfn,(unsigned int __user *)arg) ) + { + DbgFunPrint("put_user fail"); + result = -EFAULT; + break; + } + break; + + default: + DbgFunPrint("Command not support!!!"); + result = -ENOTTY; + break; + } + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,16) + up(&mydev->dev_sem); +#else + mutex_unlock(&mydev->dev_mutex); +#endif + return result; +} + +ssize_t dev_read(struct file *filp, char __user *buffer, size_t count, loff_t *f_pos) +{ + PPGDEV mydev; + BYTE *buf; + ssize_t readcount; + + DbgFunPrint("count=%zd",count); + mydev = (PPGDEV)filp->private_data; +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,16) + if (down_interruptible(&mydev->dev_sem)) + { + DbgFunPrint("lock fail"); + return 0; + } +#else + if (mutex_lock_interruptible(&mydev->dev_mutex)) + { + DbgFunPrint("lock fail"); + return 0; + } +#endif + + // To Do: + if (count > 0x100) + { + count = 0x100; +// return 0; + } + else + { + count &= ~0x3; + } + buf = kmalloc(count,GFP_KERNEL); + if (!buf) + { + return -ENOMEM; + } + + for (readcount=0;readcountpdev,readcount,(u32 *)&buf[readcount])) + { + break; + } + } + + if (copy_to_user(buffer,buf,readcount)) + { + readcount = 0; + } + *f_pos += readcount; + + kfree(buf); +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,16) + up(&mydev->dev_sem); +#else + mutex_unlock(&mydev->dev_mutex); +#endif + return readcount; +} + +static int dev_Open(struct inode *inode, struct file *pFile) +{ + PPGDEV mydev; + + mydev = container_of(inode->i_cdev, PGDEV, cdev); + DbgFunPrint("mydev=%p",mydev); + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) + atomic_inc(&mydev->count); + if (atomic_read(&mydev->count) > 1) + { + atomic_dec(&mydev->count); + DbgFunPrint("Busy"); + return -EMFILE; + } +#else + if (atomic_inc_return(&mydev->count) > 1) + { + atomic_dec(&mydev->count); + DbgFunPrint("Busy"); + return -EMFILE; + } +#endif + + pFile->private_data = mydev; + + return 0; +} + +static int dev_Close(struct inode *inode, struct file *pFile) +{ + PPGDEV mydev; + + mydev = container_of(inode->i_cdev, PGDEV, cdev); + DbgFunPrint("mydev=%p",mydev); + pFile->private_data = NULL; + + atomic_dec(&mydev->count); + + return 0; +} + +static void dev_vma_open(struct vm_area_struct *vma) +{ + DebugPrint("dev_vma_open"); +// DbgFunPrint("vma=0x%08x, vm_start=0x%08x, vm_end=0x%08x, vm_pgoff=%d\n", +// (DWORD)vma, (DWORD)vma->vm_start, (DWORD)vma->vm_end, +// (DWORD)vma->vm_pgoff); +} + +static void dev_vma_close(struct vm_area_struct *vma) +{ + DebugPrint("dev_vma_close"); +// DbgFunPrint("vma=0x%08x, vm_start=0x%08x, vm_end=0x%08x, vm_pgoff=%d\n", +// (DWORD)vma, (DWORD)vma->vm_start, (DWORD)vma->vm_end, +// (DWORD)vma->vm_pgoff); +} + +static struct vm_operations_struct dev_vma_ops = { + .open = dev_vma_open, + .close = dev_vma_close, +}; + +static int dev_mmap(struct file *filp, struct vm_area_struct *vma) +{ + PPGDEV mydev; + + mydev = (PPGDEV)filp->private_data; + + if (!mydev) + { + DbgFunPrint("NULL pointer"); + return -EFAULT; + } + DbgFunPrint("\nvma=%p, vm_start=0x%08x, vm_end=0x%08x\nvm_pgoff=%d, vm_flags=0x%x, mydev=%p\n", + vma, (DWORD)vma->vm_start, (DWORD)vma->vm_end, + (DWORD)vma->vm_pgoff,(DWORD)vma->vm_flags, + mydev); + + if (!mydev || !mydev->base_phyaddr) + { + DbgFunPrint("Invalid base_phyaddr=0x%08x",(DWORD)mydev->base_phyaddr); + return -ENXIO; + } + + switch(mydev->deviceID) + { + case 0x8167: + case 0x8169: + { + unsigned int iomem; + pci_read_config_dword(mydev->pdev, 0x14, &iomem); + if (!iomem) + { + DbgFunPrint("Invalid iomem=0x%08x, base_phyaddr=0x%08x",iomem,(DWORD)mydev->base_phyaddr); + pci_write_config_dword(mydev->pdev, 0x14, (DWORD)mydev->base_phyaddr); + } + break; + } + + default: + break; + } + + vma->vm_flags |= VM_IO; +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) + if (remap_page_range(vma, vma->vm_start, mydev->base_phyaddr, vma->vm_end-vma->vm_start, vma->vm_page_prot)) + { + DbgFunPrint("remap_page_range fail!!!"); + return -EAGAIN; + } +#else + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + if (remap_pfn_range(vma, vma->vm_start, mydev->base_phyaddr>>PAGE_SHIFT, vma->vm_end-vma->vm_start, vma->vm_page_prot)) + { + DbgFunPrint("remap_pfn_range fail!!!"); + return -EAGAIN; + } +#endif + vma->vm_ops = &dev_vma_ops; + dev_vma_open(vma); + return 0; +} + +static struct file_operations pg_fops = { + .owner = THIS_MODULE, + .read = dev_read, +// .write = NsmWriteFun, + .mmap = dev_mmap, + .unlocked_ioctl = dev_IoctlFun, + .open = dev_Open, + .release = dev_Close, +}; + +static int __devinit pgdrv_prob(struct pci_dev *pdev, const struct pci_device_id *id) +{ + PPGDEV mydev; + dev_t devno; + int pg_minor, result, i; + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26) + pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 | + PCIE_LINK_STATE_CLKPM); +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) + atomic_inc(&dev_num); + if (atomic_read(&dev_num) > MAX_DEV_NUM) + { + atomic_dec(&dev_num); + DbgFunPrint("Too Many Device"); + return -EFAULT; + } +#else + if (atomic_inc_return(&dev_num) > MAX_DEV_NUM) + { + atomic_dec(&dev_num); + DbgFunPrint("Too Many Device"); + return -EFAULT; + } +#endif + + mydev = kmalloc(sizeof(PGDEV),GFP_KERNEL); + if (!mydev) + { + DebugPrint("Allocate dev fail"); + return -ENOMEM; + } + memset(mydev, 0, sizeof(PGDEV)); + + pg_minor = -1; + devno = 0; + spin_lock(&module_lock); + for (i = 0; i < MAX_DEV_NUM; i++) + { + if (dev_info[i].bUsed == FALSE) + { + dev_info[i].bUsed = TRUE; + devno = dev_info[i].devno; + mydev->index = i; + break; + } + } + spin_unlock(&module_lock); + + mydev->pdev = pdev; + atomic_set(&mydev->count, 0); +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,16) + init_MUTEX(&mydev->dev_sem); +#else + mutex_init(&mydev->dev_mutex); +#endif + + pg_minor = MINOR(devno); + DbgFunPrint("mydev=%p, major=%u, minor=%u",mydev,major,pg_minor); + + cdev_init(&mydev->cdev, &pg_fops); + mydev->cdev.owner = THIS_MODULE; + result = cdev_add(&mydev->cdev, devno, 1); + if (result) + { + DebugPrint("cdev_add fault"); + spin_lock(&module_lock); + dev_info[mydev->index].bUsed = FALSE; + spin_unlock(&module_lock); + kfree(mydev); + return result; + } + + pci_set_drvdata(pdev, mydev); + + result = pci_enable_device(mydev->pdev); + if (result<0) + { + DbgFunPrint("pci_enable_device fail"); + return result; + } + + result = pci_request_regions(mydev->pdev, MODULENAME); + if (result<0) + { + DbgFunPrint("pci_request_regions fail"); + goto error_2; + } + + pci_set_master(mydev->pdev); + + if (mmio) { + mydev->base_phyaddr = mmio; + } else { + switch(id->device) { + case 0x8167: + case 0x8169: + mydev->base_phyaddr = pci_resource_start(mydev->pdev, 1); + break; + default: + mydev->base_phyaddr = pci_resource_start(mydev->pdev, 2); + break; + } + } + + if (!mydev->base_phyaddr) { + DbgFunPrint("Invalid phyaddress"); + result = -EFAULT; + goto error_1; + } + mydev->deviceID = id->device; + mydev->offset = mydev->base_phyaddr & ((1 << PAGE_SHIFT) - 1); + DbgFunPrint("ID=0x%04x base_phyaddr=0x%08x, offset=0x%08x", + mydev->deviceID , (DWORD)mydev->base_phyaddr, + mydev->offset); + + return 0; + +error_1: + pci_release_regions(mydev->pdev); +error_2: + pci_disable_device(mydev->pdev); + cdev_del(&mydev->cdev); + kfree(mydev); + return result; +} + +static void __devexit pgdrv_remove(struct pci_dev *pdev) +{ + PPGDEV mydev; + + mydev = pci_get_drvdata(pdev); + DbgFunPrint("mydev=%p",mydev); + + mydev->base_phyaddr = 0; + pci_release_regions(pdev); + pci_disable_device(pdev); + + cdev_del(&mydev->cdev); + spin_lock(&module_lock); + dev_info[mydev->index].bUsed = FALSE; + spin_unlock(&module_lock); + kfree(mydev); + pci_set_drvdata(pdev, NULL); + atomic_dec(&dev_num); +} + +static struct pci_device_id pgdrv_id_table[] = { + { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8125), }, + { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), }, + { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8161), }, + { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8162), }, + { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), }, + { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), }, + { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), }, + {0,}, +}; + +MODULE_DEVICE_TABLE(pci, pgdrv_id_table); + +static struct pci_driver pgdrv_pci_driver = { + .name = MODULENAME, + .id_table = pgdrv_id_table, + .probe = pgdrv_prob, + .remove = __devexit_p(pgdrv_remove), +}; + +static int __init pgdrv_init(void) +{ + int result, i; + dev_t devno; + + memset(dev_info, 0, sizeof(dev_info)); + atomic_set(&dev_num,0); + spin_lock_init(&module_lock); + + if (!major) + { + result = alloc_chrdev_region(&devno, 0, MAX_DEV_NUM, MODULENAME); + major = MAJOR(devno); + } + else + { + devno = MKDEV(major, 0); + result = register_chrdev_region(devno, MAX_DEV_NUM, MODULENAME); + } + + if (result < 0) + { + DebugPrint("Can't get major %d", major); + return result; + } + DbgFunPrint("Major : %d",major); + + for (i=0; i"); +MODULE_VERSION("1.00.00"); +MODULE_DESCRIPTION("RealTek driver of Ethernet PG tool"); diff --git a/external/cache/sources/linuxpg/pgdrv.h b/external/cache/sources/linuxpg/pgdrv.h new file mode 100644 index 0000000..6704f03 --- /dev/null +++ b/external/cache/sources/linuxpg/pgdrv.h @@ -0,0 +1,90 @@ +#ifndef _PG_DRV_H +#define _PG_DRV_H + +#define BYTE __u8 +#define WORD __u16 +#define DWORD __u32 +#define DWORD64 __u64 +#define BOOLEAN int +typedef void * PVOID; +typedef BYTE * PBYTE; +typedef WORD * PWORD; +typedef DWORD * PDWORD; + +#ifndef TRUE + #define TRUE 1 + #define FALSE 0 +#endif + +#define PRINT_LEVEL KERN_NOTICE + +#ifdef DEBUG +#define DebugPrint(fmt,args...) printk(PRINT_LEVEL "[RTNICPG]" fmt "\n",## args) +#define DbgFunPrint(fmt,args...) printk(PRINT_LEVEL "[RTNICPG]" "%s %i: " fmt "\n",__FUNCTION__,__LINE__,## args) +#else +#define DebugPrint(fmt,args...) //printk(PRINT_LEVEL fmt "\n",## args) +#define DbgFunPrint(fmt,args...) //printk(PRINT_LEVEL "%s %i: " fmt "\n",__FUNCTION__,__LINE__,## args) +#endif + +/******************************************************************************* +*******************************************************************************/ +#define Writel(Address,Data) writel(Data,(void *)(Address)) +#define Readl(Address) readl((void *)(Address)) +#define Writew(Address,Data) writew(Data,(void *)(Address)) +#define Readw(Address) readw((void *)(Address)) +#define Writeb(Address,Data) writeb(Data,(void *)(Address)) +#define Readb(Address) readb((void *)(Address)) + +#define MODULENAME "pgtool" +#define MAX_DEV_NUM 10 +#define MAX_IO_SIZE 0x100 + +typedef struct _DEV_INFO_ +{ + dev_t devno; + bool bUsed; +}DEV_INFO,*PDEV_INFO; + +typedef struct _PG_DEV_ +{ + struct cdev cdev; + struct pci_dev *pdev; + unsigned long base_phyaddr; + unsigned int offset; + unsigned int deviceID; + atomic_t count; +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,16) + struct semaphore dev_sem; +#else + struct mutex dev_mutex; +#endif + unsigned int index; +}PGDEV,*PPGDEV; + +typedef struct _PCI_CONFIG_RW_ +{ + union + { + unsigned char byte; + unsigned short word; + unsigned int dword; + }; + unsigned int bRead:1; + unsigned int size:7; + unsigned int addr:8; + unsigned int reserve:16; +}PCI_CONFIG_RW,*PPCI_CONFIG_RW; + +#define RTL_IOC_MAGIC 0x95 + +#define IOC_PCI_CONFIG _IOWR(RTL_IOC_MAGIC, 0, PCI_CONFIG_RW) +#define IOC_IOMEM_OFFSET _IOR(RTL_IOC_MAGIC, 1, unsigned int) +#define IOC_DEV_FUN _IOR(RTL_IOC_MAGIC, 2, unsigned int) + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,8,0) +#define __devinit +#define __devexit +#define __devexit_p(func) func +#endif + +#endif // end of #ifndef _PG_DRV_H diff --git a/external/cache/sources/linuxpg/pgload.sh b/external/cache/sources/linuxpg/pgload.sh new file mode 100755 index 0000000..a5a6003 --- /dev/null +++ b/external/cache/sources/linuxpg/pgload.sh @@ -0,0 +1,70 @@ +#!/bin/sh +# pgload, v2.1 2011/09/23 +module="pgdrv" +#mode="664" + +# check whrther the kernel is valid or not +#version1=`uname -r | cut -d '.' -f 1` +#version2=`uname -r | cut -d '.' -f 2` +#version3=`uname -r | cut -d '.' -f 3` +#version3=${version3%%-*} +#if [ "$version1" != "2" ] || [ "$version2" != "6" ] ; then +# echo " Your version of kernel is `uname -r`" +# echo " The kernel is too outdated to be used." +# echo " Please update the version to 2.6.16 or later." +# exit 1 +#elif test $version3 -lt 11 ; then +# echo " Your version of kernel is `uname -r`" +# echo " The kernel is outdated." +# echo " Please update the version to 2.6.11 or later." +#fi + +# invoke insmod with all arguments we got +# and use a pathname, as insmod doesn't look in . by default +check=`lsmod | grep r8169` +if [ "$check" != "" ]; then + echo "rmmod r8169" + /sbin/rmmod r8169 +fi + +check=`lsmod | grep r8168` +if [ "$check" != "" ]; then + echo "rmmod r8168" + /sbin/rmmod r8168 +fi + +check=`lsmod | grep r8125` +if [ "$check" != "" ]; then + echo "rmmod r8125" + /sbin/rmmod r8125 +fi + +check=`lsmod | grep r8101` +if [ "$check" != "" ]; then + echo "rmmod r8101" + /sbin/rmmod r8101 +fi + +check=`lsmod | grep $module` +if [ "$check" != "" ]; then + echo "$module has existed." + echo "$check" + exit 1 +else + if test -e ./$module.ko ; then + echo "insmod $module.ko $*" + /sbin/insmod ./$module.ko $* || exit 1 + else + echo "make clean all" + make clean all 1>/dev/null + if test -e ./$module.ko ; then + echo "insmod $module.ko $*" + /sbin/insmod ./$module.ko $* || exit 1 + else + echo "$module.ko doesn't exist." + exit 1 + fi + fi +fi + +exit 0 diff --git a/external/cache/sources/linuxpg/rtnicpg-aarch64-armv8 b/external/cache/sources/linuxpg/rtnicpg-aarch64-armv8 new file mode 100755 index 0000000..99140b8 Binary files /dev/null and b/external/cache/sources/linuxpg/rtnicpg-aarch64-armv8 differ diff --git a/external/cache/sources/linuxpg/rtnicpg-aarch64-linux-gnu b/external/cache/sources/linuxpg/rtnicpg-aarch64-linux-gnu new file mode 100755 index 0000000..a3c5f6c Binary files /dev/null and b/external/cache/sources/linuxpg/rtnicpg-aarch64-linux-gnu differ diff --git a/external/cache/sources/linuxpg/rtnicpg-armv8 b/external/cache/sources/linuxpg/rtnicpg-armv8 new file mode 100755 index 0000000..cc84501 Binary files /dev/null and b/external/cache/sources/linuxpg/rtnicpg-armv8 differ diff --git a/external/cache/sources/linuxpg/rtnicpg-i686 b/external/cache/sources/linuxpg/rtnicpg-i686 new file mode 100755 index 0000000..b2d65d9 Binary files /dev/null and b/external/cache/sources/linuxpg/rtnicpg-i686 differ diff --git a/external/cache/sources/linuxpg/rtnicpg-mips64el-64r2 b/external/cache/sources/linuxpg/rtnicpg-mips64el-64r2 new file mode 100755 index 0000000..8641d70 Binary files /dev/null and b/external/cache/sources/linuxpg/rtnicpg-mips64el-64r2 differ diff --git a/external/cache/sources/linuxpg/rtnicpg-mipsel-32r2 b/external/cache/sources/linuxpg/rtnicpg-mipsel-32r2 new file mode 100755 index 0000000..9aa17c9 Binary files /dev/null and b/external/cache/sources/linuxpg/rtnicpg-mipsel-32r2 differ diff --git a/external/cache/sources/linuxpg/rtnicpg-x86_64 b/external/cache/sources/linuxpg/rtnicpg-x86_64 new file mode 100755 index 0000000..ec96911 Binary files /dev/null and b/external/cache/sources/linuxpg/rtnicpg-x86_64 differ diff --git a/external/cache/sources/linuxpg/sccm.csv b/external/cache/sources/linuxpg/sccm.csv new file mode 100644 index 0000000..944eb2d --- /dev/null +++ b/external/cache/sources/linuxpg/sccm.csv @@ -0,0 +1 @@ +DASHOOB000005,64652174-BD28-6C93-68C6-909A7AA8C46D,00:E0:4C:68:00:01 \ No newline at end of file