Add linuxpg

external/cache/sources/linuxpg/8105E.cfg

@@ -0,0 +1,65 @@
+NODEID = 00 E0 4C 36 00 01
+;ENDID = 00 E0 4C 36 FF FF
+VID = 10 EC
+DID = 81 36
+SVID = 10 EC
+SMID = 01 23
+
+;Do not change following parameters without Realtek approval
+CONFIG0 = 00
+CONFIG1 = 0F
+CONFIGx = 1C
+CONFIG3 = 60
+CONFIG4 = 14
+CONFIG5 = 82
+;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1
+;CONFIG5 = 8A
+
+PMC = C3 FF
+ROMBAR = 00
+;LEDCFG = High-Byte(19H) Low-Byte(18H)
+LEDCFG = 98 CA
+ROMCONF = 3F
+;Bit 7-6    Boot Protocol
+;           00 ==> PXE protocol
+;           01 ==> RPL protocol
+;Bit 5-4    Boot order (method)
+;           00 ==> ROM disable
+;           01 ==> Int 18h
+;           10 ==> Int 19h
+;           11 ==> PnP/BEV(BBS)
+;Bit 3      Show Config Message
+;           0 ==> Enable
+;           1 ==> Disable
+;Bit 2      Shift+F10 Menu Entry
+;           0 ==> Enable
+;           1 ==> Disable
+;Bit 1-0    Show Config Time
+;           00 ==> 3 Seconds
+;           01 ==> 5 Seconds
+;           10 ==> 1 Seconds
+;           11 ==> 0 Second
+
+;Serial Number in PCI Config Space
+SN = 00 E0 4C 36 00 00 00 01
+
+;PCI-E Parameter (Do not change without Realtek approval)
+C_PCIE0 = 04 01
+;0AH~0BH
+C_PCIE1 = C0 8C 80 02 00 00 11 3C 07 00 10 20
+;1AH~25H
+C_PCIE2 = 76 00 63 01 01 FF    13 AA 03 02 20
+;26H~2BH 2DH~31H
+C_PCIE3 = 80 02 00 20 04 40 20 00 04 40 20   00 00 20
+;34H~3EH 40H~42H
+C_PCIE4 = 60 00 0A 00   00 00
+;46H~49H  52~53H
+C_EPHY = B9 6A 98     AC 6B 75 80
+;43H~45H 54H~57H
+D_EPHY = 8D 75 7B 01
+;58H~5BH
+E0_EPHY = 48
+;5EH
+VERSION = 1.031
+
+