Обновить platform/generic/cvitek_riscv.c

2026-02-11 02:19:45 +07:00 · 2026-02-11 01:41:03 +07:00 · 2026-02-11 01:34:56 +07:00 · 2025-01-24 14:50:56 +08:00 · 2025-01-13 16:32:03 +08:00 · 2024-10-14 19:27:45 +08:00
303 changed files with 3599 additions and 24012 deletions
--- a/.clang-format
+++ b/.clang-format
@@ -1,16 +0,0 @@
-AlignConsecutiveAssignments: true
-AlignEscapedNewlines: Left
-AlignTrailingComments: true
-AllowShortFunctionsOnASingleLine: None
-BraceWrapping:
-  AfterFunction: true
-BreakBeforeBraces: Custom
-BreakStringLiterals: false
-ContinuationIndentWidth: 8
-Cpp11BracedListStyle: false
-IndentWidth: 8
-ReflowComments: false
-SortIncludes: false
-SpacesInContainerLiterals: false
-TabWidth: 8
-UseTab: Always
--- a/.gitignore
+++ b/.gitignore
@@ -9,5 +9,3 @@ install/

 # Development friendly files
 tags
-cscope*
-*.swp
--- a/25
+++ b/25
@@ -1,25 +0,0 @@
-# SPDX-License-Identifier: BSD-2-Clause
-
-mainmenu "OpenSBI $(OPENSBI_PLATFORM) Configuration"
-
-config OPENSBI_SRC_DIR
-	string
-	option env="OPENSBI_SRC_DIR"
-
-config OPENSBI_PLATFORM
-	string
-	option env="OPENSBI_PLATFORM"
-
-config OPENSBI_PLATFORM_SRC_DIR
-	string
-	option env="OPENSBI_PLATFORM_SRC_DIR"
-
-menu "Platform Options"
-source "$(OPENSBI_PLATFORM_SRC_DIR)/Kconfig"
-endmenu
-
-source "$(OPENSBI_SRC_DIR)/lib/sbi/Kconfig"
-
-source "$(OPENSBI_SRC_DIR)/lib/utils/Kconfig"
-
-source "$(OPENSBI_SRC_DIR)/firmware/Kconfig"
--- a/325
+++ b/325
@@ -47,14 +47,11 @@ ifdef PLATFORM_DIR
    platform_parent_dir=$(platform_dir_path)
  else
    PLATFORM=$(shell basename $(platform_dir_path))
-    platform_parent_dir=$(shell realpath ${platform_dir_path}/..)
+    platform_parent_dir=$(subst $(PLATFORM),,$(platform_dir_path))
  endif
 else
 platform_parent_dir=$(src_dir)/platform
 endif
-ifndef PLATFORM_DEFCONFIG
-PLATFORM_DEFCONFIG=defconfig
-endif

 # Check if verbosity is ON for build process
 CMD_PREFIX_DEFAULT := @
@@ -73,74 +70,32 @@ export libsbi_dir=$(CURDIR)/lib/sbi
 export libsbiutils_dir=$(CURDIR)/lib/utils
 export firmware_dir=$(CURDIR)/firmware

-# Setup variables for kconfig
-ifdef PLATFORM
-export PYTHONDONTWRITEBYTECODE=1
-export KCONFIG_DIR=$(platform_build_dir)/kconfig
-export KCONFIG_AUTOLIST=$(KCONFIG_DIR)/auto.list
-export KCONFIG_AUTOHEADER=$(KCONFIG_DIR)/autoconf.h
-export KCONFIG_AUTOCMD=$(KCONFIG_DIR)/auto.conf.cmd
-export KCONFIG_CONFIG=$(KCONFIG_DIR)/.config
-# Additional exports for include paths in Kconfig files
-export OPENSBI_SRC_DIR=$(src_dir)
-export OPENSBI_PLATFORM=$(PLATFORM)
-export OPENSBI_PLATFORM_SRC_DIR=$(platform_src_dir)
-endif
-
 # Find library version
 OPENSBI_VERSION_MAJOR=`grep "define OPENSBI_VERSION_MAJOR" $(include_dir)/sbi/sbi_version.h | sed 's/.*MAJOR.*\([0-9][0-9]*\)/\1/'`
 OPENSBI_VERSION_MINOR=`grep "define OPENSBI_VERSION_MINOR" $(include_dir)/sbi/sbi_version.h | sed 's/.*MINOR.*\([0-9][0-9]*\)/\1/'`
 OPENSBI_VERSION_GIT=$(shell if [ -d $(src_dir)/.git ]; then git describe 2> /dev/null; fi)

 # Setup compilation commands
-ifneq ($(LLVM),)
-CC		=	clang
-AR		=	llvm-ar
-LD		=	ld.lld
-OBJCOPY		=	llvm-objcopy
-else
 ifdef CROSS_COMPILE
 CC		=	$(CROSS_COMPILE)gcc
+CPP		=	$(CROSS_COMPILE)cpp
 AR		=	$(CROSS_COMPILE)ar
 LD		=	$(CROSS_COMPILE)ld
 OBJCOPY		=	$(CROSS_COMPILE)objcopy
 else
 CC		?=	gcc
+CPP		?=	cpp
 AR		?=	ar
 LD		?=	ld
 OBJCOPY		?=	objcopy
 endif
-endif
-CPP		=	$(CC) -E
 AS		=	$(CC)
 DTC		=	dtc

-ifneq ($(shell $(CC) --version 2>&1 | head -n 1 | grep clang),)
-CC_IS_CLANG	=	y
-else
-CC_IS_CLANG	=	n
-endif
-
-ifneq ($(shell $(LD) --version 2>&1 | head -n 1 | grep LLD),)
-LD_IS_LLD	=	y
-else
-LD_IS_LLD	=	n
-endif
-
-ifeq ($(CC_IS_CLANG),y)
-ifneq ($(CROSS_COMPILE),)
-CLANG_TARGET	=	--target=$(notdir $(CROSS_COMPILE:%-=%))
-endif
-endif
-
-# Guess the compiler's XLEN
-OPENSBI_CC_XLEN := $(shell TMP=`$(CC) $(CLANG_TARGET) -dumpmachine | sed 's/riscv\([0-9][0-9]\).*/\1/'`; echo $${TMP})
-
-# Guess the compiler's ABI and ISA
-ifneq ($(CC_IS_CLANG),y)
+# Guess the compillers xlen
+OPENSBI_CC_XLEN := $(shell TMP=`$(CC) -dumpmachine | sed 's/riscv\([0-9][0-9]\).*/\1/'`; echo $${TMP})
 OPENSBI_CC_ABI := $(shell TMP=`$(CC) -v 2>&1 | sed -n 's/.*\(with\-abi=\([a-zA-Z0-9]*\)\).*/\2/p'`; echo $${TMP})
 OPENSBI_CC_ISA := $(shell TMP=`$(CC) -v 2>&1 | sed -n 's/.*\(with\-arch=\([a-zA-Z0-9]*\)\).*/\2/p'`; echo $${TMP})
-endif

 # Setup platform XLEN
 ifndef PLATFORM_RISCV_XLEN
@@ -151,47 +106,6 @@ ifndef PLATFORM_RISCV_XLEN
  endif
 endif

-ifeq ($(CC_IS_CLANG),y)
-ifeq ($(CROSS_COMPILE),)
-CLANG_TARGET	=	--target=riscv$(PLATFORM_RISCV_XLEN)-unknown-elf
-endif
-endif
-
-ifeq ($(LD_IS_LLD),y)
-RELAX_FLAG	=	-mno-relax
-USE_LD_FLAG	=	-fuse-ld=lld
-else
-USE_LD_FLAG	=	-fuse-ld=bfd
-endif
-
-# Check whether the linker supports creating PIEs
-OPENSBI_LD_PIE := $(shell $(CC) $(CLANG_TARGET) $(RELAX_FLAG) $(USE_LD_FLAG) -fPIE -nostdlib -Wl,-pie -x c /dev/null -o /dev/null >/dev/null 2>&1 && echo y || echo n)
-
-# Check whether the compiler supports -m(no-)save-restore
-CC_SUPPORT_SAVE_RESTORE := $(shell $(CC) $(CLANG_TARGET) $(RELAX_FLAG) -nostdlib -mno-save-restore -x c /dev/null -o /dev/null 2>&1 | grep "\-save\-restore" >/dev/null && echo n || echo y)
-
-# Check whether the assembler and the compiler support the Zicsr and Zifencei extensions
-CC_SUPPORT_ZICSR_ZIFENCEI := $(shell $(CC) $(CLANG_TARGET) $(RELAX_FLAG) -nostdlib -march=rv$(OPENSBI_CC_XLEN)imafd_zicsr_zifencei -x c /dev/null -o /dev/null 2>&1 | grep "zicsr\|zifencei" > /dev/null && echo n || echo y)
-
-# Build Info:
-# OPENSBI_BUILD_TIME_STAMP -- the compilation time stamp
-# OPENSBI_BUILD_COMPILER_VERSION -- the compiler version info
-BUILD_INFO ?= n
-ifeq ($(BUILD_INFO),y)
-OPENSBI_BUILD_DATE_FMT = +%Y-%m-%d %H:%M:%S %z
-ifdef SOURCE_DATE_EPOCH
-	OPENSBI_BUILD_TIME_STAMP ?= $(shell date -u -d "@$(SOURCE_DATE_EPOCH)" \
-		"$(OPENSBI_BUILD_DATE_FMT)" 2>/dev/null || \
-		date -u -r "$(SOURCE_DATE_EPOCH)" \
-		"$(OPENSBI_BUILD_DATE_FMT)" 2>/dev/null || \
-		date -u "$(OPENSBI_BUILD_DATE_FMT)")
-else
-	OPENSBI_BUILD_TIME_STAMP ?= $(shell date "$(OPENSBI_BUILD_DATE_FMT)")
-endif
-OPENSBI_BUILD_COMPILER_VERSION=$(shell $(CC) -v 2>&1 | grep ' version ' | \
-	sed 's/[[:space:]]*$$//')
-endif
-
 # Setup list of objects.mk files
 ifdef PLATFORM
 platform-object-mks=$(shell if [ -d $(platform_src_dir)/ ]; then find $(platform_src_dir) -iname "objects.mk" | sort -r; fi)
@@ -200,38 +114,12 @@ libsbi-object-mks=$(shell if [ -d $(libsbi_dir) ]; then find $(libsbi_dir) -inam
 libsbiutils-object-mks=$(shell if [ -d $(libsbiutils_dir) ]; then find $(libsbiutils_dir) -iname "objects.mk" | sort -r; fi)
 firmware-object-mks=$(shell if [ -d $(firmware_dir) ]; then find $(firmware_dir) -iname "objects.mk" | sort -r; fi)

-# The "make all" rule should always be first rule
-.PHONY: all
-all:
-
-# Include platform specific .config
+# Include platform specifig config.mk
 ifdef PLATFORM
-.PHONY: menuconfig
-menuconfig: $(platform_src_dir)/Kconfig $(src_dir)/Kconfig
-	$(CMD_PREFIX)mkdir -p $(KCONFIG_DIR)
-	$(CMD_PREFIX)$(src_dir)/scripts/Kconfiglib/menuconfig.py $(src_dir)/Kconfig
-	$(CMD_PREFIX)$(src_dir)/scripts/Kconfiglib/genconfig.py --header-path $(KCONFIG_AUTOHEADER) --sync-deps $(KCONFIG_DIR) --file-list $(KCONFIG_AUTOLIST) $(src_dir)/Kconfig
-
-.PHONY: savedefconfig
-savedefconfig: $(platform_src_dir)/Kconfig $(src_dir)/Kconfig
-	$(CMD_PREFIX)mkdir -p $(KCONFIG_DIR)
-	$(CMD_PREFIX)$(src_dir)/scripts/Kconfiglib/savedefconfig.py --kconfig $(src_dir)/Kconfig --out $(KCONFIG_DIR)/defconfig
-
-$(KCONFIG_CONFIG): $(platform_src_dir)/configs/$(PLATFORM_DEFCONFIG) $(platform_src_dir)/Kconfig $(src_dir)/Kconfig
-	$(CMD_PREFIX)mkdir -p $(KCONFIG_DIR)
-	$(CMD_PREFIX)$(src_dir)/scripts/Kconfiglib/defconfig.py --kconfig $(src_dir)/Kconfig $(platform_src_dir)/configs/$(PLATFORM_DEFCONFIG)
-	$(CMD_PREFIX)$(src_dir)/scripts/Kconfiglib/genconfig.py --header-path $(KCONFIG_AUTOHEADER) --sync-deps $(KCONFIG_DIR) --file-list $(KCONFIG_AUTOLIST) $(src_dir)/Kconfig
-
-$(KCONFIG_AUTOCMD): $(KCONFIG_CONFIG)
-	$(CMD_PREFIX)mkdir -p $(KCONFIG_DIR)
-	$(CMD_PREFIX)printf "%s: " $(KCONFIG_CONFIG) > $(KCONFIG_AUTOCMD)
-	$(CMD_PREFIX)cat $(KCONFIG_AUTOLIST) | tr '\n' ' ' >> $(KCONFIG_AUTOCMD)
-
-include $(KCONFIG_CONFIG)
-include $(KCONFIG_AUTOCMD)
+include $(platform_src_dir)/config.mk
 endif

-# Include all objects.mk files
+# Include all object.mk files
 ifdef PLATFORM
 include $(platform-object-mks)
 endif
@@ -241,8 +129,8 @@ include $(firmware-object-mks)

 # Setup list of objects
 libsbi-objs-path-y=$(foreach obj,$(libsbi-objs-y),$(build_dir)/lib/sbi/$(obj))
+libsbiutils-objs-path-y=$(foreach obj,$(libsbiutils-objs-y),$(build_dir)/lib/utils/$(obj))
 ifdef PLATFORM
-libsbiutils-objs-path-y=$(foreach obj,$(libsbiutils-objs-y),$(platform_build_dir)/lib/utils/$(obj))
 platform-objs-path-y=$(foreach obj,$(platform-objs-y),$(platform_build_dir)/$(obj))
 firmware-bins-path-y=$(foreach bin,$(firmware-bins-y),$(platform_build_dir)/firmware/$(bin))
 endif
@@ -255,6 +143,20 @@ deps-y+=$(libsbi-objs-path-y:.o=.dep)
 deps-y+=$(libsbiutils-objs-path-y:.o=.dep)
 deps-y+=$(firmware-objs-path-y:.o=.dep)

+ifeq (,$(wildcard ${PM_SRAM_BIN_PATH}))
+	ifeq (${CHIP_ARCH},CV180X)
+		PM_SRAM_BIN_PATH=${OPENSBI_PATH}/pm_default_cv180x.bin
+	endif
+	ifeq (${CHIP_ARCH},CV181X)
+		PM_SRAM_BIN_PATH=${OPENSBI_PATH}/pm_default_cv181x.bin
+	endif
+else
+ifeq ($(filter clean %clean clean%,$(MAKECMDGOALS)),)
+$(shell touch -c platform\generic\cvitek_riscv.c > /dev/null)
+endif
+endif
+$(info PM_SRAM_BIN_PATH is '${PM_SRAM_BIN_PATH}')
+
 # Setup platform ABI, ISA and Code Model
 ifndef PLATFORM_RISCV_ABI
  ifneq ($(PLATFORM_RISCV_TOOLCHAIN_DEFAULT), 1)
@@ -269,11 +171,7 @@ ifndef PLATFORM_RISCV_ABI
 endif
 ifndef PLATFORM_RISCV_ISA
  ifneq ($(PLATFORM_RISCV_TOOLCHAIN_DEFAULT), 1)
-    ifeq ($(CC_SUPPORT_ZICSR_ZIFENCEI), y)
-      PLATFORM_RISCV_ISA = rv$(PLATFORM_RISCV_XLEN)imafdc_zicsr_zifencei
-    else
-      PLATFORM_RISCV_ISA = rv$(PLATFORM_RISCV_XLEN)imafdc
-    endif
+    PLATFORM_RISCV_ISA = rv$(PLATFORM_RISCV_XLEN)imafdc
  else
    PLATFORM_RISCV_ISA = $(OPENSBI_CC_ISA)
  endif
@@ -310,75 +208,61 @@ else
 endif

 # Setup compilation commands flags
-ifeq ($(CC_IS_CLANG),y)
-GENFLAGS	+=	$(CLANG_TARGET)
-GENFLAGS	+=	-Wno-unused-command-line-argument
-endif
-GENFLAGS	+=	-I$(platform_src_dir)/include
+GENFLAGS	=	-I$(platform_src_dir)/include
 GENFLAGS	+=	-I$(include_dir)
 ifneq ($(OPENSBI_VERSION_GIT),)
 GENFLAGS	+=	-DOPENSBI_VERSION_GIT="\"$(OPENSBI_VERSION_GIT)\""
 endif
-ifeq ($(BUILD_INFO),y)
-GENFLAGS	+=	-DOPENSBI_BUILD_TIME_STAMP="\"$(OPENSBI_BUILD_TIME_STAMP)\""
-GENFLAGS	+=	-DOPENSBI_BUILD_COMPILER_VERSION="\"$(OPENSBI_BUILD_COMPILER_VERSION)\""
-endif
-ifdef PLATFORM
-GENFLAGS	+=	-include $(KCONFIG_AUTOHEADER)
-endif
 GENFLAGS	+=	$(libsbiutils-genflags-y)
 GENFLAGS	+=	$(platform-genflags-y)
 GENFLAGS	+=	$(firmware-genflags-y)

-CFLAGS		=	-g -Wall -Werror -ffreestanding -nostdlib -fno-stack-protector -fno-strict-aliasing -O2
-CFLAGS		+=	-fno-omit-frame-pointer -fno-optimize-sibling-calls -mstrict-align
-# enable -m(no-)save-restore option by CC_SUPPORT_SAVE_RESTORE
-ifeq ($(CC_SUPPORT_SAVE_RESTORE),y)
-CFLAGS		+=	-mno-save-restore
+define add_define
+    GENFLAGS	+=	-D$(1)$(if $(value $(1)),=$(value $(1)),)
+endef
+
+ifeq (${CONFIG_OPENSBI_FASTBOOT},y)
+$(eval $(call add_define,CONFIG_OPENSBI_FASTBOOT))
 endif
+
+CFLAGS		=	-g -Wall -Werror -ffreestanding -nostdlib -fno-strict-aliasing -O2
+CFLAGS		+=	-fno-omit-frame-pointer -fno-optimize-sibling-calls
+CFLAGS		+=	-mno-save-restore -mstrict-align
 CFLAGS		+=	-mabi=$(PLATFORM_RISCV_ABI) -march=$(PLATFORM_RISCV_ISA)
 CFLAGS		+=	-mcmodel=$(PLATFORM_RISCV_CODE_MODEL)
-CFLAGS		+=	$(RELAX_FLAG)
 CFLAGS		+=	$(GENFLAGS)
 CFLAGS		+=	$(platform-cflags-y)
 CFLAGS		+=	-fno-pie -no-pie
 CFLAGS		+=	$(firmware-cflags-y)
+CFLAGS		+=	-DPM_SRAM_BIN_PATH=$(PM_SRAM_BIN_PATH)
+ifeq ($(CHIP_ARCH),CV180X)
+CFLAGS		+=	-DCONFIG_CV180X
+endif
+ifeq (${CHIP_ARCH},CV181X)
+CFLAGS		+=	-DCONFIG_CV181X
+endif

 CPPFLAGS	+=	$(GENFLAGS)
 CPPFLAGS	+=	$(platform-cppflags-y)
 CPPFLAGS	+=	$(firmware-cppflags-y)

 ASFLAGS		=	-g -Wall -nostdlib
-ASFLAGS		+=	-fno-omit-frame-pointer -fno-optimize-sibling-calls -mstrict-align
-# enable -m(no-)save-restore option by CC_SUPPORT_SAVE_RESTORE
-ifeq ($(CC_SUPPORT_SAVE_RESTORE),y)
-ASFLAGS		+=	-mno-save-restore
-endif
+ASFLAGS		+=	-fno-omit-frame-pointer -fno-optimize-sibling-calls
+ASFLAGS		+=	-mno-save-restore -mstrict-align
 ASFLAGS		+=	-mabi=$(PLATFORM_RISCV_ABI) -march=$(PLATFORM_RISCV_ISA)
 ASFLAGS		+=	-mcmodel=$(PLATFORM_RISCV_CODE_MODEL)
-ASFLAGS		+=	$(RELAX_FLAG)
-ifneq ($(CC_IS_CLANG),y)
-ifneq ($(RELAX_FLAG),)
-ASFLAGS		+=	-Wa,$(RELAX_FLAG)
-endif
-endif
 ASFLAGS		+=	$(GENFLAGS)
 ASFLAGS		+=	$(platform-asflags-y)
 ASFLAGS		+=	$(firmware-asflags-y)

 ARFLAGS		=	rcs

-ELFFLAGS	+=	$(USE_LD_FLAG)
-ELFFLAGS	+=	-Wl,--build-id=none -Wl,-N
+ELFFLAGS	+=	-Wl,--build-id=none -N -static-libgcc -lgcc
 ELFFLAGS	+=	$(platform-ldflags-y)
 ELFFLAGS	+=	$(firmware-ldflags-y)

 MERGEFLAGS	+=	-r
-ifeq ($(LD_IS_LLD),y)
-MERGEFLAGS	+=	-b elf
-else
 MERGEFLAGS	+=	-b elf$(PLATFORM_RISCV_XLEN)-littleriscv
-endif
 MERGEFLAGS	+=	-m elf$(PLATFORM_RISCV_XLEN)lriscv

 DTSCPPFLAGS	=	$(CPPFLAGS) -nostdinc -nostdlib -fno-builtin -D__DTS__ -x assembler-with-cpp
@@ -450,93 +334,45 @@ compile_d2c = $(CMD_PREFIX)mkdir -p `dirname $(1)`; \
 	     $(if $($(2)-varprefix-$(3)),$(eval D2C_NAME_PREFIX := $($(2)-varprefix-$(3))),$(eval D2C_NAME_PREFIX := $(5))) \
 	     $(if $($(2)-padding-$(3)),$(eval D2C_PADDING_BYTES := $($(2)-padding-$(3))),$(eval D2C_PADDING_BYTES := 0)) \
 	     $(src_dir)/scripts/d2c.sh -i $(6) -a $(D2C_ALIGN_BYTES) -p $(D2C_NAME_PREFIX) -t $(D2C_PADDING_BYTES) > $(1)
-compile_carray = $(CMD_PREFIX)mkdir -p `dirname $(1)`; \
-	     echo " CARRAY    $(subst $(build_dir)/,,$(1))"; \
-	     $(eval CARRAY_VAR_LIST := $(carray-$(subst .c,,$(shell basename $(1)))-y)) \
-	     $(src_dir)/scripts/carray.sh -i $(2) -l "$(CARRAY_VAR_LIST)" > $(1)
 compile_gen_dep = $(CMD_PREFIX)mkdir -p `dirname $(1)`; \
 	     echo " GEN-DEP   $(subst $(build_dir)/,,$(1))"; \
 	     echo "$(1:.dep=$(2)): $(3)" >> $(1)

 targets-y  = $(build_dir)/lib/libsbi.a
+targets-y  += $(build_dir)/lib/libsbiutils.a
 ifdef PLATFORM
 targets-y += $(platform_build_dir)/lib/libplatsbi.a
 endif
 targets-y += $(firmware-bins-path-y)

-# The default "make all" rule
+# Default rule "make" should always be first rule
 .PHONY: all
 all: $(targets-y)

 # Preserve all intermediate files
 .SECONDARY:

-# Rules for lib/sbi sources
 $(build_dir)/lib/libsbi.a: $(libsbi-objs-path-y)
 	$(call compile_ar,$@,$^)

+$(build_dir)/lib/libsbiutils.a: $(libsbi-objs-path-y) $(libsbiutils-objs-path-y)
+	$(call compile_ar,$@,$^)
+
 $(platform_build_dir)/lib/libplatsbi.a: $(libsbi-objs-path-y) $(libsbiutils-objs-path-y) $(platform-objs-path-y)
 	$(call compile_ar,$@,$^)

-$(build_dir)/%.dep: $(src_dir)/%.carray $(KCONFIG_CONFIG)
-	$(call compile_gen_dep,$@,.c,$< $(KCONFIG_CONFIG))
-	$(call compile_gen_dep,$@,.o,$(@:.dep=.c))
-
-$(build_dir)/%.c: $(src_dir)/%.carray
-	$(call compile_carray,$@,$<)
-
-$(build_dir)/%.dep: $(src_dir)/%.c $(KCONFIG_CONFIG)
+$(build_dir)/%.dep: $(src_dir)/%.c
 	$(call compile_cc_dep,$@,$<)

 $(build_dir)/%.o: $(src_dir)/%.c
 	$(call compile_cc,$@,$<)

-$(build_dir)/%.o: $(build_dir)/%.c
-	$(call compile_cc,$@,$<)
-
-ifeq ($(BUILD_INFO),y)
-$(build_dir)/lib/sbi/sbi_init.o: $(libsbi_dir)/sbi_init.c FORCE
-	$(call compile_cc,$@,$<)
-endif
-
-$(build_dir)/%.dep: $(src_dir)/%.S $(KCONFIG_CONFIG)
+$(build_dir)/%.dep: $(src_dir)/%.S
 	$(call compile_as_dep,$@,$<)

 $(build_dir)/%.o: $(src_dir)/%.S
 	$(call compile_as,$@,$<)

-# Rules for platform sources
-$(platform_build_dir)/%.dep: $(platform_src_dir)/%.carray $(KCONFIG_CONFIG)
-	$(call compile_gen_dep,$@,.c,$< $(KCONFIG_CONFIG))
-	$(call compile_gen_dep,$@,.o,$(@:.dep=.c))
-
-$(platform_build_dir)/%.c: $(platform_src_dir)/%.carray
-	$(call compile_carray,$@,$<)
-
-$(platform_build_dir)/%.dep: $(platform_src_dir)/%.c $(KCONFIG_CONFIG)
-	$(call compile_cc_dep,$@,$<)
-
-$(platform_build_dir)/%.o: $(platform_src_dir)/%.c $(KCONFIG_CONFIG)
-	$(call compile_cc,$@,$<)
-
-$(platform_build_dir)/%.dep: $(platform_src_dir)/%.S
-	$(call compile_as_dep,$@,$<)
-
-$(platform_build_dir)/%.o: $(platform_src_dir)/%.S
-	$(call compile_as,$@,$<)
-
-$(platform_build_dir)/%.dep: $(platform_src_dir)/%.dts $(KCONFIG_CONFIG)
-	$(call compile_gen_dep,$@,.dtb,$< $(KCONFIG_CONFIG))
-	$(call compile_gen_dep,$@,.c,$(@:.dep=.dtb))
-	$(call compile_gen_dep,$@,.o,$(@:.dep=.c))
-
-$(platform_build_dir)/%.c: $(platform_build_dir)/%.dtb
-	$(call compile_d2c,$@,platform,$(subst .dtb,.o,$(subst /,-,$(subst $(platform_build_dir)/,,$<))),16,dt,$<)
-
-$(platform_build_dir)/%.dtb: $(platform_src_dir)/%.dts
-	$(call compile_dts,$@,$<)
-
-# Rules for lib/utils and firmware sources
 $(platform_build_dir)/%.bin: $(platform_build_dir)/%.elf
 	$(call compile_objcopy,$@,$<)

@@ -546,20 +382,39 @@ $(platform_build_dir)/%.elf: $(platform_build_dir)/%.o $(platform_build_dir)/%.e
 $(platform_build_dir)/%.ld: $(src_dir)/%.ldS
 	$(call compile_cpp,$@,$<)

-$(platform_build_dir)/%.dep: $(src_dir)/%.carray $(KCONFIG_CONFIG)
-	$(call compile_gen_dep,$@,.c,$< $(KCONFIG_CONFIG))
+$(platform_build_dir)/%.dep: $(platform_src_dir)/%.c
+	$(call compile_cc_dep,$@,$<)
+
+$(platform_build_dir)/%.o: $(platform_src_dir)/%.c
+	$(call compile_cc,$@,$<)
+
+$(platform_build_dir)/%.o: $(platform_build_dir)/%.c
+	$(call compile_cc,$@,$<)
+
+$(platform_build_dir)/%.dep: $(platform_src_dir)/%.S
+	$(call compile_as_dep,$@,$<)
+
+$(platform_build_dir)/%.o: $(platform_src_dir)/%.S
+	$(call compile_as,$@,$<)
+
+$(platform_build_dir)/%.dep: $(platform_src_dir)/%.dts
+	$(call compile_gen_dep,$@,.dtb,$<)
+	$(call compile_gen_dep,$@,.c,$(@:.dep=.dtb))
 	$(call compile_gen_dep,$@,.o,$(@:.dep=.c))

-$(platform_build_dir)/%.c: $(src_dir)/%.carray
-	$(call compile_carray,$@,$<)
+$(platform_build_dir)/%.c: $(platform_build_dir)/%.dtb
+	$(call compile_d2c,$@,platform,$(subst .dtb,.o,$(subst /,-,$(subst $(platform_build_dir)/,,$<))),16,dt,$<)

-$(platform_build_dir)/%.dep: $(src_dir)/%.c $(KCONFIG_CONFIG)
+$(platform_build_dir)/%.dtb: $(platform_src_dir)/%.dts
+	$(call compile_dts,$@,$<)
+
+$(platform_build_dir)/%.dep: $(src_dir)/%.c
 	$(call compile_cc_dep,$@,$<)

 $(platform_build_dir)/%.o: $(src_dir)/%.c
 	$(call compile_cc,$@,$<)

-$(platform_build_dir)/%.dep: $(src_dir)/%.S $(KCONFIG_CONFIG)
+$(platform_build_dir)/%.dep: $(src_dir)/%.S
 	$(call compile_as_dep,$@,$<)

 $(platform_build_dir)/%.o: $(src_dir)/%.S
@@ -603,6 +458,7 @@ endif
 endif

 install_targets-y  = install_libsbi
+install_targets-y  += install_libsbiutils
 ifdef PLATFORM
 install_targets-y += install_libplatsbi
 install_targets-y += install_firmwares
@@ -617,12 +473,17 @@ install_libsbi: $(build_dir)/lib/libsbi.a
 	$(call inst_header_dir,$(install_root_dir)/$(install_include_path),$(include_dir)/sbi)
 	$(call inst_file,$(install_root_dir)/$(install_lib_path)/libsbi.a,$(build_dir)/lib/libsbi.a)

+.PHONY: install_libsbiutils
+install_libsbiutils: $(build_dir)/lib/libsbiutils.a
+	$(call inst_header_dir,$(install_root_dir)/$(install_include_path),$(include_dir)/sbi_utils)
+	$(call inst_file,$(install_root_dir)/$(install_lib_path)/libsbiutils.a,$(build_dir)/lib/libsbiutils.a)
+
 .PHONY: install_libplatsbi
-install_libplatsbi: $(platform_build_dir)/lib/libplatsbi.a $(build_dir)/lib/libsbi.a
+install_libplatsbi: $(platform_build_dir)/lib/libplatsbi.a $(build_dir)/lib/libsbi.a $(build_dir)/lib/libsbiutils.a
 	$(call inst_file,$(install_root_dir)/$(install_lib_path)/opensbi/$(platform_subdir)/lib/libplatsbi.a,$(platform_build_dir)/lib/libplatsbi.a)

 .PHONY: install_firmwares
-install_firmwares: $(platform_build_dir)/lib/libplatsbi.a $(build_dir)/lib/libsbi.a $(firmware-bins-path-y)
+install_firmwares: $(platform_build_dir)/lib/libplatsbi.a $(build_dir)/lib/libsbi.a $(build_dir)/lib/libsbiutils.a $(firmware-bins-path-y)
 	$(call inst_file_list,$(install_root_dir),$(build_dir),$(install_firmware_path)/$(platform_subdir)/firmware,$(firmware-elfs-path-y))
 	$(call inst_file_list,$(install_root_dir),$(build_dir),$(install_firmware_path)/$(platform_subdir)/firmware,$(firmware-bins-path-y))

@@ -630,17 +491,6 @@ install_firmwares: $(platform_build_dir)/lib/libplatsbi.a $(build_dir)/lib/libsb
 install_docs: $(build_dir)/docs/latex/refman.pdf
 	$(call inst_file,$(install_root_dir)/$(install_docs_path)/refman.pdf,$(build_dir)/docs/latex/refman.pdf)

-.PHONY: cscope
-cscope:
-	$(CMD_PREFIX)find \
-		"$(src_dir)/firmware" \
-		"$(src_dir)/include" \
-		"$(src_dir)/lib" \
-		"$(platform_src_dir)" \
-	-name "*.[chS]" -print > cscope.files
-	$(CMD_PREFIX)echo "$(KCONFIG_AUTOHEADER)" >> cscope.files
-	$(CMD_PREFIX)cscope -bkq -i cscope.files -f cscope.out
-
 # Rule for "make clean"
 .PHONY: clean
 clean:
@@ -670,8 +520,3 @@ ifeq ($(install_root_dir),$(install_root_dir_default)/usr)
 	$(if $(V), @echo " RM        $(install_root_dir_default)")
 	$(CMD_PREFIX)rm -rf $(install_root_dir_default)
 endif
-	$(if $(V), @echo " RM        $(src_dir)/cscope*")
-	$(CMD_PREFIX)rm -f $(src_dir)/cscope*
-
-.PHONY: FORCE
-FORCE:
--- a/README.md
+++ b/README.md
@@ -92,37 +92,16 @@ N.B. Any S-mode boot loader (i.e. U-Boot) doesn't need to support HSM extension,
 as it doesn't need to boot all the harts. The operating system should be
 capable enough to bring up all other non-booting harts using HSM extension.

-Required Toolchain and Packages
-------------------------------
+Required Toolchain
+------------------

 OpenSBI can be compiled natively or cross-compiled on a x86 host. For
-cross-compilation, you can build your own toolchain, download a prebuilt one
-from the [Bootlin toolchain repository] or install a distribution-provided
-toolchain; if you opt to use LLVM/Clang, most distribution toolchains will
-support cross-compiling for RISC-V using the same toolchain as your native
-LLVM/Clang toolchain due to LLVM's ability to support multiple backends in the
-same binary, so is often an easy way to obtain a working cross-compilation
-toolchain.
-
-Basically, we prefer toolchains with Position Independent Executable (PIE)
-support like *riscv64-linux-gnu-gcc*, *riscv64-unknown-freebsd-gcc*, or
-*Clang/LLVM* as they generate PIE firmware images that can run at arbitrary
-address with appropriate alignment. If a bare-metal GNU toolchain (e.g.
-*riscv64-unknown-elf-gcc*) is used, static linked firmware images are
-generated instead. *Clang/LLVM* can still generate PIE images if a bare-metal
-triple is used (e.g. *-target riscv64-unknown-elf*).
+cross-compilation, you can build your own toolchain or just download
+a prebuilt one from the [Bootlin toolchain repository].

 Please note that only a 64-bit version of the toolchain is available in
 the Bootlin toolchain repository for now.

-In addition to a toolchain, OpenSBI also requires the following packages on
-the host:
-
-1. device-tree-compiler: The device tree compiler for compiling device
-   tree sources (DTS files).
-2. python3: The python 3.0 (or compatible) language support for various
-   scripts.
-
 Building and Installing the OpenSBI Platform-Independent Library
 ----------------------------------------------------------------

@@ -132,7 +111,7 @@ architecture than RISC-V.

 For cross-compiling, the environment variable *CROSS_COMPILE* must be defined
 to specify the name prefix of the RISC-V compiler toolchain executables, e.g.
-*riscv64-linux-gnu-* if the gcc executable used is *riscv64-linux-gnu-gcc*.
+*riscv64-unknown-elf-* if the gcc executable used is *riscv64-unknown-elf-gcc*.

 To build *libsbi.a* simply execute:
 ```
@@ -204,100 +183,25 @@ top-level make command line. These options, such as *PLATFORM_<xyz>* or
 *docs/platform/<platform_name>.md* files and
 *docs/firmware/<firmware_name>.md* files.

-All OpenSBI platforms support Kconfig style build-time configuration. Users
-can change the build-time configuration of a platform using a graphical
-interface as follows:
-```
-make PLATFORM=<platform_subdir> menuconfig
-```
-
-Alternately, an OpenSBI platform can have multiple default configurations
-and users can select a custom default configuration as follows:
-```
-make PLATFORM=<platform_subdir> PLATFORM_DEFCONFIG=<platform_custom_defconfig>
-```
-
 Building 32-bit / 64-bit OpenSBI Images
 ---------------------------------------
 By default, building OpenSBI generates 32-bit or 64-bit images based on the
 supplied RISC-V cross-compile toolchain. For example if *CROSS_COMPILE* is set
-to *riscv64-linux-gnu-*, 64-bit OpenSBI images will be generated. If building
+to *riscv64-unknown-elf-*, 64-bit OpenSBI images will be generated. If building
 32-bit OpenSBI images, *CROSS_COMPILE* should be set to a toolchain that is
-pre-configured to generate 32-bit RISC-V codes, like *riscv32-linux-gnu-*.
+pre-configured to generate 32-bit RISC-V codes, like *riscv32-unknown-elf-*.

 However it's possible to explicitly specify the image bits we want to build with
 a given RISC-V toolchain. This can be done by setting the environment variable
 *PLATFORM_RISCV_XLEN* to the desired width, for example:

 ```
-export CROSS_COMPILE=riscv64-linux-gnu-
+export CROSS_COMPILE=riscv64-unknown-elf-
 export PLATFORM_RISCV_XLEN=32
 ```

 will generate 32-bit OpenSBI images. And vice vesa.

-Building with Clang/LLVM
------------------------
-
-OpenSBI can also be built with Clang/LLVM. To build with just Clang but keep
-the default binutils (which will still use the *CROSS_COMPILE* prefix if
-defined), override the *CC* make variable with:
-```
-make CC=clang
-```
-
-To build with a full LLVM-based toolchain, not just Clang, enable the *LLVM*
-option with:
-```
-make LLVM=1
-```
-
-When using Clang, *CROSS_COMPILE* often does not need to be defined unless
-using GNU binutils with prefixed binary names. *PLATFORM_RISCV_XLEN* will be
-used to infer a default triple to pass to Clang, so if *PLATFORM_RISCV_XLEN*
-itself defaults to an undesired value then prefer setting that rather than the
-full triple via *CROSS_COMPILE*. If *CROSS_COMPILE* is nonetheless defined,
-rather than being used as a prefix for the executable name, it will instead be
-passed via the `--target` option with the trailing `-` removed, so must be a
-valid triple.
-
-These can also be mixed; for example using a GCC cross-compiler but LLVM
-binutils would be:
-```
-make CC=riscv64-linux-gnu-gcc LLVM=1
-```
-
-These variables must be passed for all the make invocations described in this
-document.
-
-NOTE: Using Clang with a `riscv*-linux-gnu` GNU binutils linker has been seen
-to produce broken binaries with missing relocations; it is therefore currently
-recommended that this combination be avoided or *FW_PIC=n* be used to disable
-building OpenSBI as a position-independent binary.
-
-Building with timestamp and compiler info
-----------------------------------------
-
-When doing development, we may want to know the build time and compiler info
-for debug purpose. OpenSBI can also be built with timestamp and compiler info.
-To build with those info and print it out at boot time, we can just simply add
-`BUILD_INFO=y`, like:
-```
-make BUILD_INFO=y
-```
-
-But if you have used `BUILD_INFO=y`, and want to switch back to `BUILD_INFO=n`,
-you must do
-```
-make clean
-```
-before the next build.
-
-NOTE: Using `BUILD_INFO=y` without specifying SOURCE_DATE_EPOCH will violate
-[reproducible builds]. This definition is ONLY for development and debug
-purpose, and should NOT be used in a product which follows "reproducible
-builds".
-
 Contributing to OpenSBI
 -----------------------

@@ -380,4 +284,3 @@ make I=<install_directory> install_docs
 [Doxygen manual]: http://www.doxygen.nl/manual/index.html
 [Kendryte standalone SDK]: https://github.com/kendryte/kendryte-standalone-sdk
 [third party notices]: ThirdPartyNotices.md
-[reproducible builds]: https://reproducible-builds.org
--- a/docs/contributing.md
+++ b/docs/contributing.md
@@ -29,7 +29,7 @@ and "top:".
 5. Maintainers should use "Rebase and Merge" when using GitHub to merge pull
 requests to avoid creating unnecessary merge commits.
 6. Maintainers should avoid creating branches directly in the main
-riscv/opensbi repository. Instead, prefer using a fork of the riscv/opensbi main
+riscv/opensbi repository. Instead prefer using a fork of the riscv/opensbi main
 repository and branches within that fork to create pull requests.
 7. A maintainer cannot merge his own pull requests in the riscv/opensbi main
 repository.
--- a/docs/domain_support.md
+++ b/docs/domain_support.md
@@ -2,7 +2,7 @@ OpenSBI Domain Support
 ======================

 An OpenSBI domain is a system-level partition (subset) of underlying hardware
-having its own memory regions (RAM and MMIO devices) and HARTs. The OpenSBI
+having it's own memory regions (RAM and MMIO devices) and HARTs. The OpenSBI
 will try to achieve secure isolation between domains using RISC-V platform
 features such as PMP, ePMP, IOPMP, SiFive Shield, etc.

@@ -15,7 +15,7 @@ Important entities which help implement OpenSBI domain support are:
 Each HART of a RISC-V platform must have an OpenSBI domain assigned to it.
 The OpenSBI platform support is responsible for populating domains and
 providing HART id to domain mapping. The OpenSBI domain support will by
-default assign **the ROOT domain** to all HARTs of a RISC-V platform, so
+default assign **the ROOT domain** to all HARTs of a RISC-V platform so
 it is not mandatory for the OpenSBI platform support to populate domains.

 Domain Memory Region
@@ -29,7 +29,7 @@ OpenSBI and has following details:
 * **base** - The base address of a memory region is **2 ^ order**
  aligned start address
 * **flags** - The flags of a memory region represent memory type (i.e.
-  RAM or MMIO) and allowed accesses (i.e. READ, WRITE, EXECUTE, etc.)
+  RAM or MMIO) and allowed accesses (i.e. READ, WRITE, EXECUTE, etc)

 Domain Instance
 ---------------
@@ -52,6 +52,7 @@ has following details:
 * **next_mode** - Privilege mode of the next booting stage for this
  domain. This can be either S-mode or U-mode.
 * **system_reset_allowed** - Is domain allowed to reset the system?
+* **system_suspend_allowed** - Is domain allowed to suspend the system?

 The memory regions represented by **regions** in **struct sbi_domain** have
 following additional constraints to align with RISC-V PMP requirements:
@@ -91,6 +92,7 @@ following manner:
 * **next_mode** - Next booting stage mode in coldboot HART scratch space
  is the next mode for the ROOT domain
 * **system_reset_allowed** - The ROOT domain is allowed to reset the system
+* **system_suspend_allowed** - The ROOT domain is allowed to suspend the system

 Domain Effects
 --------------
@@ -187,6 +189,8 @@ The DT properties of a domain instance DT node are as follows:
  stage mode of coldboot HART** is used as default value.
 * **system-reset-allowed** (Optional) - A boolean flag representing
  whether the domain instance is allowed to do system reset.
+* **system-suspend-allowed** (Optional) - A boolean flag representing
+  whether the domain instance is allowed to do system suspend.

 ### Assigning HART To Domain Instance

@@ -252,6 +256,7 @@ be done:
                next-addr = <0x0 0x80100000>;
                next-mode = <0x0>;
                system-reset-allowed;
+                system-suspend-allowed;
            };

            udomain: untrusted-domain {
--- a/docs/firmware/fw.md
+++ b/docs/firmware/fw.md
@@ -9,13 +9,6 @@ OpenSBI generic library code. The supported firmwares type will differ in how
 the arguments passed by the platform early boot stage are handled, as well as
 how the boot stage following the firmware will be handled and executed.

-The previous booting stage will pass information via the following registers
-of RISC-V CPU:
-
-* hartid via *a0* register
-* device tree blob address in memory via *a1* register. The address must
-  be aligned to 8 bytes.
-
 OpenSBI currently supports three different types of firmwares.

 Firmware with Dynamic Information (*FW_DYNAMIC*)
@@ -53,7 +46,7 @@ the booting stage to follow OpenSBI firmware.
 A *FW_PAYLOAD* firmware is also useful for cases where the booting stage prior
 to OpenSBI firmware does not pass a *flattened device tree (FDT file)*. In such
 case, a *FW_PAYLOAD* firmware allows embedding a flattened device tree in the
-.rodata section of the final firmware.
+.text section of the final firmware.

 Firmware Configuration and Compilation
 --------------------------------------
@@ -69,12 +62,6 @@ parameters:
  argument by the prior booting stage.
 * **FW_FDT_PADDING** - Optional zero bytes padding to the embedded flattened
  device tree binary file specified by **FW_FDT_PATH** option.
-* **FW_PIC** - "FW_PIC=y" generates position independent executable firmware
-  images. OpenSBI can run at arbitrary address with appropriate alignment.
-  Therefore, the original relocation mechanism ("FW_PIC=n") will be skipped.
-  In other words, OpenSBI will directly run at the load address without any
-  code movement. This option requires a toolchain with PIE support, and it
-  is on by default.

 Additionally, each firmware type as a set of type specific configuration
 parameters. Detailed information for each firmware type can be found in the
--- a/docs/firmware/fw_dynamic.md
+++ b/docs/firmware/fw_dynamic.md
@@ -6,9 +6,8 @@ information about next booting stage (e.g. a bootloader or an OS) and runtime
 OpenSBI library options from previous booting stage.

 The previous booting stage will pass information to *FW_DYNAMIC* by creating
-*struct fw_dynamic_info* in memory and passing its address to *FW_DYNAMIC*
-via *a2* register of RISC-V CPU. The address must be aligned to 8 bytes on
-RV64 and 4 bytes on RV32.
+*struct fw_dynamic_info* in memory and passing it's address to *FW_DYNAMIC*
+via *a2* register of RISC-V CPU.

 A *FW_DYNAMIC* firmware is particularly useful when the booting stage executed
 prior to OpenSBI firmware is capable of loading both the OpenSBI firmware and
@@ -20,7 +19,7 @@ the booting stage binary to follow OpenSBI firmware.
 A platform can enable *FW_DYNAMIC* firmware using any of the following methods.

 1. Specifying `FW_DYNAMIC=y` on the top level `make` command line.
-2. Specifying `FW_DYNAMIC=y` in the target platform *objects.mk* configuration
+2. Specifying `FW_DYNAMIC=y` in the target platform *config.mk* configuration
 file.

 The compiled *FW_DYNAMIC* firmware ELF file is named *fw_dynamic.elf*. It's
@@ -31,6 +30,6 @@ directory.
 *FW_DYNAMIC* Firmware Configuration Options
 -------------------------------------------

-The *FW_DYNAMIC* firmware does not require any platform specific configuration
+The *FW_DYNAMIC* firmware does not requires any platform specific configuration
 parameters because all required information is passed by previous booting stage
 at runtime via *struct fw_dynamic_info*.
--- a/docs/firmware/fw_jump.md
+++ b/docs/firmware/fw_jump.md
@@ -15,7 +15,7 @@ and the booting stage binary to follow the OpenSBI firmware.
 A platform *FW_JUMP* firmware can be enabled by any of the following methods:

 1. Specifying `FW_JUMP=y` on the top level `make` command line.
-2. Specifying `FW_JUMP=y` in the target platform *objects.mk* configuration file.
+2. Specifying `FW_JUMP=y` in the target platform *config.mk* configuration file.

 The compiled *FW_JUMP* firmware ELF file is named *fw_jump.elf*. Its expanded
 image file is *fw_jump.bin*. Both files are created in the platform-specific
@@ -26,7 +26,7 @@ build directory under the *build/platform/<platform_subdir>/firmware* directory.

 To operate correctly, a *FW_JUMP* firmware requires some configuration
 parameters to be defined using either the top level `make` command line or the
-target platform *objects.mk* configuration file. The possible parameters are as
+target platform *config.mk* configuration file. The possible parameters are as
 follows:

 * **FW_JUMP_ADDR** - Address of the entry point of the booting stage to be
@@ -41,22 +41,6 @@ follows:
  provided, then the OpenSBI firmware will pass the FDT address passed by the
  previous booting stage to the next booting stage.

-  When using the default *FW_JUMP_FDT_ADDR* with *PLATFORM=generic*, you must
-  ensure *FW_JUMP_FDT_ADDR* is set high enough to avoid overwriting the kernel.
-  You can use the following method.
-
-  ```
-  ${CROSS_COMPILE}objdump -h $KERNEL_ELF | sort -k 5,5 | awk -n '/^ +[0-9]+ /\
-  {addr="0x"$3; size="0x"$5; printf "0x""%x\n",addr+size}' \
-  | (( `tail -1` > 0x2200000 )) && echo fdt overlaps kernel,\
-  increase FW_JUMP_FDT_ADDR
-
-  ${LLVM}objdump -h --show-lma $KERNEL_ELF | sort -k 5,5 | \
-  awk -n '/^ +[0-9]+ / {addr="0x"$3; size="0x"$5; printf "0x""%x\n",addr+size}'\
-  | (( `tail -1` > 0x2200000 )) && echo fdt overlaps kernel,\
-  increase FW_JUMP_FDT_ADDR
-  ```
-
 *FW_JUMP* Example
 -----------------

--- a/docs/firmware/fw_payload.md
+++ b/docs/firmware/fw_payload.md
@@ -12,7 +12,7 @@ firmware and the booting stage to follow OpenSBI firmware.
 A *FW_PAYLOAD* firmware is also useful for cases where the booting stage prior
 to the OpenSBI firmware does not pass a *flattened device tree (FDT file)*. In
 such a case, a *FW_PAYLOAD* firmware allows embedding a flattened device tree
-in the .rodata section of the final firmware.
+in the .text section of the final firmware.

 Enabling *FW_PAYLOAD* compilation
 ---------------------------------
@@ -20,7 +20,7 @@ Enabling *FW_PAYLOAD* compilation
 The *FW_PAYLOAD* firmware can be enabled by any of the following methods:

 1. Specifying `FW_PAYLOAD=y` on the top level `make` command line.
-2. Specifying `FW_PAYLOAD=y` in the target platform *objects.mk* configuration
+2. Specifying `FW_PAYLOAD=y` in the target platform *config.mk* configuration
   file.

 The compiled *FW_PAYLOAD* firmware ELF file is named *fw_jump.elf*. Its
@@ -33,7 +33,7 @@ Configuration Options

 A *FW_PAYLOAD* firmware is built according to configuration parameters and
 options. These configuration parameters can be defined using either the top
-level `make` command line or the target platform *objects.mk* configuration
+level `make` command line or the target platform *config.mk* configuration
 file. The parameters currently defined are as follows:

 * **FW_PAYLOAD_OFFSET** - Offset from *FW_TEXT_BASE* where the payload binary
--- a/docs/library_usage.md
+++ b/docs/library_usage.md
@@ -8,7 +8,11 @@ OpenSBI provides two types of static libraries:
   hooks for the execution of this interface must be provided by the firmware or
   bootloader linking with this library. This library is installed as
   *<install_directory>/lib/libsbi.a*
-2. *libplatsbi.a* - An example platform-specific static library integrating
+2. *libsbiutils.a* - A static library that will contain all common code required
+   by any platform supported in OpenSBI. It will be built by default and included
+   in libplatsbi.a. This library is installed as
+   *<install_directory>/lib/libsbiutils.a*.
+3. *libplatsbi.a* - An example platform-specific static library integrating
   *libsbi.a* with platform-specific hooks. This library is available only for
   the platforms supported by OpenSBI. This library is installed as
   *<install_directory>/platform/<platform_subdir>/lib/libplatsbi.a*
@@ -73,7 +77,7 @@ firmware drivers based on the external firmware architecture.
 **OPENSBI_EXTERNAL_SBI_TYPES** identifier is introduced to *sbi_types.h* for selecting
 external header file during the build preprocess in order to define OpensSBI data types
 based on external firmware data type binding.
-For example, *bool* is declared as *int* in sbi_types.h. However, in EDK2 build system,
+For example, *bool* is declared as *int* in sbi_types.h. However in EDK2 build system,
 *bool* is declared as *BOOLEAN* which is defined as *unsigned char* data type.

 External firmware can define **OPENSBI_EXTERNAL_SBI_TYPES** in CFLAGS and specify it to the
--- a/docs/platform/andes-ae350.md
+++ b/docs/platform/andes-ae350.md
@@ -1,14 +1,14 @@
 Andes AE350 SoC Platform
 ========================
 The AE350 AXI/AHB-based platform N25(F)/NX25(F)/D25F/A25/AX25 CPU with level-one
-memories, interrupt controller, debug module, AXI and AHB Bus Matrix Controller,
-AXI-to-AHB Bridge and a collection of fundamental AHB/APB bus IP components
-pre-integrated together as a system design. The high-quality and configurable
+memories,interrupt controller, debug module, AXI and AHB Bus Matrix Controller,
+AXI-to-AHB Bridge and a collection of fundamentalAHB/APB bus IP components
+pre-integrated together as a system design.The high-quality and configurable
 AHB/APB IPs suites a majority embedded systems, and the verified platform serves
 as a starting point to jump start SoC designs.

 To build platform specific library and firmwares, provide the
-*PLATFORM=generic* parameter to the top level `make` command.
+*PLATFORM=andes/ae350* parameter to the top level make command.

 Platform Options
 ----------------
@@ -18,190 +18,13 @@ The Andes AE350 platform does not have any platform-specific options.
 Building Andes AE350 Platform
 -----------------------------

-AE350's dts is included in https://github.com/andestech/linux/tree/RISCV-Linux-5.4-ast-v5_1_0-branch
+To use Linux v5.2 should be used to build Andes AE350 OpenSBI binaries by using
+the compile time option FW_FDT_PATH.
+
+AE350's dts is included in https://github.com/andestech/linux/tree/ast-v3_2_0-release-public

 **Linux Kernel Payload**

 ```
-make PLATFORM=generic FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image FW_FDT_PATH=<ae350.dtb path>
-```
-
-DTS Example: (Quad-core AX45MP)
-------------------------------
-
-```
-	compatible = "andestech,ae350";
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		timebase-frequency = <60000000>;
-
-		CPU0: cpu@0 {
-			device_type = "cpu";
-			reg = <0>;
-			status = "okay";
-			compatible = "riscv";
-			riscv,isa = "rv64imafdc";
-			riscv,priv-major = <1>;
-			riscv,priv-minor = <10>;
-			mmu-type = "riscv,sv48";
-			clock-frequency = <60000000>;
-			i-cache-size = <0x8000>;
-			i-cache-sets = <256>;
-			i-cache-line-size = <64>;
-			i-cache-block-size = <64>;
-			d-cache-size = <0x8000>;
-			d-cache-sets = <128>;
-			d-cache-line-size = <64>;
-			d-cache-block-size = <64>;
-			next-level-cache = <&L2>;
-			CPU0_intc: interrupt-controller {
-				#interrupt-cells = <1>;
-				interrupt-controller;
-				compatible = "riscv,cpu-intc";
-			};
-		};
-		CPU1: cpu@1 {
-			device_type = "cpu";
-			reg = <1>;
-			status = "okay";
-			compatible = "riscv";
-			riscv,isa = "rv64imafdc";
-			riscv,priv-major = <1>;
-			riscv,priv-minor = <10>;
-			mmu-type = "riscv,sv48";
-			clock-frequency = <60000000>;
-			i-cache-size = <0x8000>;
-			i-cache-sets = <256>;
-			i-cache-line-size = <64>;
-			i-cache-block-size = <64>;
-			d-cache-size = <0x8000>;
-			d-cache-sets = <128>;
-			d-cache-line-size = <64>;
-			d-cache-block-size = <64>;
-			next-level-cache = <&L2>;
-			CPU1_intc: interrupt-controller {
-				#interrupt-cells = <1>;
-				interrupt-controller;
-				compatible = "riscv,cpu-intc";
-			};
-		};
-		CPU2: cpu@2 {
-			device_type = "cpu";
-			reg = <2>;
-			status = "okay";
-			compatible = "riscv";
-			riscv,isa = "rv64imafdc";
-			riscv,priv-major = <1>;
-			riscv,priv-minor = <10>;
-			mmu-type = "riscv,sv48";
-			clock-frequency = <60000000>;
-			i-cache-size = <0x8000>;
-			i-cache-sets = <256>;
-			i-cache-line-size = <64>;
-			i-cache-block-size = <64>;
-			d-cache-size = <0x8000>;
-			d-cache-sets = <128>;
-			d-cache-line-size = <64>;
-			d-cache-block-size = <64>;
-			next-level-cache = <&L2>;
-			CPU2_intc: interrupt-controller {
-				#interrupt-cells = <1>;
-				interrupt-controller;
-				compatible = "riscv,cpu-intc";
-			};
-		};
-		CPU3: cpu@3 {
-			device_type = "cpu";
-			reg = <3>;
-			status = "okay";
-			compatible = "riscv";
-			riscv,isa = "rv64imafdc";
-			riscv,priv-major = <1>;
-			riscv,priv-minor = <10>;
-			mmu-type = "riscv,sv48";
-			clock-frequency = <60000000>;
-			i-cache-size = <0x8000>;
-			i-cache-sets = <256>;
-			i-cache-line-size = <64>;
-			i-cache-block-size = <64>;
-			d-cache-size = <0x8000>;
-			d-cache-sets = <128>;
-			d-cache-line-size = <64>;
-			d-cache-block-size = <64>;
-			next-level-cache = <&L2>;
-			CPU3_intc: interrupt-controller {
-				#interrupt-cells = <1>;
-				interrupt-controller;
-				compatible = "riscv,cpu-intc";
-			};
-		};
-	};
-
-	soc {
-		#address-cells = <2>;
-		#size-cells = <2>;
-		compatible = "andestech,riscv-ae350-soc", "simple-bus";
-		ranges;
-
-		plic0: interrupt-controller@e4000000 {
-			compatible = "riscv,plic0";
-			reg = <0x00000000 0xe4000000 0x00000000 0x02000000>;
-			interrupts-extended = < &CPU0_intc 11 &CPU0_intc 9
-			                        &CPU1_intc 11 &CPU1_intc 9
-			                        &CPU2_intc 11 &CPU2_intc 9
-			                        &CPU3_intc 11 &CPU3_intc 9 >;
-			interrupt-controller;
-			#address-cells = <2>;
-			#interrupt-cells = <2>;
-			riscv,ndev = <71>;
-		};
-
-		plicsw: interrupt-controller@e6400000 {
-			compatible = "andestech,plicsw";
-			reg = <0x00000000 0xe6400000 0x00000000 0x00400000>;
-			interrupts-extended = < &CPU0_intc 3
-			                        &CPU1_intc 3
-			                        &CPU2_intc 3
-			                        &CPU3_intc 3 >;
-			interrupt-controller;
-			#address-cells = <2>;
-			#interrupt-cells = <2>;
-		};
-
-		plmt0: plmt0@e6000000 {
-			compatible = "andestech,plmt0";
-			reg = <0x00000000 0xe6000000 0x00000000 0x00100000>;
-			interrupts-extended = < &CPU0_intc 7
-			                        &CPU1_intc 7
-			                        &CPU2_intc 7
-			                        &CPU3_intc 7 >;
-		};
-
-		wdt: watchdog@f0500000 {
-			compatible = "andestech,atcwdt200";
-			reg = <0x00000000 0xf0500000 0x00000000 0x00001000>;
-			interrupts = <3 4>;
-			interrupt-parent = <&plic0>;
-			clock-frequency = <15000000>;
-		};
-
-		serial0: serial@f0300000 {
-			compatible = "andestech,uart16550", "ns16550a";
-			reg = <0x00000000 0xf0300000 0x00000000 0x00001000>;
-			interrupts = <9 4>;
-			interrupt-parent = <&plic0>;
-			clock-frequency = <19660800>;
-			current-speed = <38400>;
-			reg-shift = <2>;
-			reg-offset = <32>;
-			reg-io-width = <4>;
-			no-loopback-test = <1>;
-		};
-
-		smu: smu@f0100000 {
-			compatible = "andestech,atcsmu";
-			reg = <0x00000000 0xf0100000 0x00000000 0x00001000>;
-		};
-	};
+make PLATFORM=andes/ae350 FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image FW_FDT_PATH=<ae350.dtb path>
 ```
--- a/docs/platform/fpga-ariane.md
+++ b/docs/platform/fpga-ariane.md
@@ -7,7 +7,7 @@ Linux.

 The FPGA SoC currently contains the following peripherals:
 - DDR3 memory controller
- SPI controller to connect to an SDCard
+- SPI controller to conncet to an SDCard
 - Ethernet controller
 - JTAG port (see debugging section below)
 - Bootrom containing zero stage bootloader and device tree.
--- a/docs/platform/generic.md
+++ b/docs/platform/generic.md
@@ -45,18 +45,12 @@ The *Generic* platform does not have any platform-specific options.
 RISC-V Platforms Using Generic Platform
 ---------------------------------------

-* **Andes AE350 Platform** (*[andes-ae350.md]*)
 * **QEMU RISC-V Virt Machine** (*[qemu_virt.md]*)
-* **Renesas RZ/Five SoC** (*[renesas-rzfive.md]*)
-* **Shakti C-class SoC Platform** (*[shakti_cclass.md]*)
-* **SiFive HiFive Unleashed** (*[sifive_fu540.md]*)
 * **Spike** (*[spike.md]*)
+* **Shakti C-class SoC Platform** (*[shakti_cclass.md]*)
 * **T-HEAD C9xx series Processors** (*[thead-c9xx.md]*)

-[andes-ae350.md]: andse-ae350.md
 [qemu_virt.md]: qemu_virt.md
-[renesas-rzfive.md]: renesas-rzfive.md
-[shakti_cclass.md]: shakti_cclass.md
-[sifive_fu540.md]: sifive_fu540.md
 [spike.md]: spike.md
+[shakti_cclass.md]: shakti_cclass.md
 [thead-c9xx.md]: thead-c9xx.md
--- a/docs/platform/platform.md
+++ b/docs/platform/platform.md
@@ -39,15 +39,11 @@ OpenSBI currently supports the following virtual and hardware platforms:
  processor based SOCs. More details on this platform can be found in the
  file *[shakti_cclass.md]*.

-* **Renesas RZ/Five SoC**: Platform support for Renesas RZ/Five (R9A07G043F) SoC
-  used on the Renesas RZ/Five SMARC EVK board. More details on this platform can
-  be found in the file *[renesas-rzfive.md]*.
-
 The code for these supported platforms can be used as example to implement
 support for other platforms. The *platform/template* directory also provides
-template files for implementing support for a new platform. The *objects.mk*,
-*Kconfig*, *configs/defconfig* and *platform.c* template files provides enough
-comments to facilitate the implementation.
+template files for implementing support for a new platform. The *object.mk*,
+*config.mk* and *platform.c* template files provides enough comments to
+facilitate the implementation.

 [generic.md]: generic.md
 [qemu_virt.md]: qemu_virt.md
@@ -58,4 +54,3 @@ comments to facilitate the implementation.
 [spike.md]: spike.md
 [fpga-openpiton.md]: fpga-openpiton.md
 [shakti_cclass.md]: shakti_cclass.md
-[renesas-rzfive.md]: renesas-rzfive.md
--- a/docs/platform/qemu_virt.md
+++ b/docs/platform/qemu_virt.md
@@ -147,27 +147,3 @@ qemu-system-riscv32 -M virt -m 256M -nographic \
 	-device virtio-blk-device,drive=hd0 \
 	-append "root=/dev/vda rw console=ttyS0"
 ```
-
-Debugging with GDB
------------------
-
-In a first console start OpenSBI with QEMU:
-
-```
-qemu-system-riscv64 -M virt -m 256M -nographic \
-	-bios build/platform/generic/firmware/fw_payload.bin \
-	-gdb tcp::1234 \
-	-S
-
-```
-
-Parameter *-gdb tcp::1234* specifies 1234 as the debug port.
-Parameter *-S* lets QEMU wait at the first instruction.
-
-In a second console start GDB:
-
-```
-gdb build/platform/generic/firmware/fw_payload.elf \
-	-ex 'target remote localhost:1234'
-
-```
--- a/docs/platform/renesas-rzfive.md
+++ b/docs/platform/renesas-rzfive.md
@@ -1,160 +0,0 @@
-Renesas RZ/Five SoC (R9A07G043F) Platform
-=========================================
-The RZ/Five microprocessor includes a single RISC-V CPU Core (Andes AX45MP)
-1.0 GHz, 16-bit DDR3L/DDR4 interface. Supported interfaces include:
- Memory controller for DDR4-1600 / DDR3L-1333 with 16 bits
- System RAM (RAM of 128 Kbytes (ECC))
- SPI Multi I/O Bus Controller 1ch
- SD Card Host Interface/Multimedia Card Interface (SD/MMC) 2ch
- Serial Sound Interface (SSI) 4ch
- Sampling Rate Converter (SRC) 1ch
- USB2.0 host/function interface 2ch (ch0: Host-Function ch1: Host only)
- Gigabit Ethernet Interface (GbE) 2ch
- Controller Area Network Interface (CAN) 2ch (CAN-FD ISO 11898-1 (CD2014) compliant)
- Multi-function Timer Pulse Unit 3 (MTU3a) 9 ch (16 bits × 8 channels, 32 bits × 1 channel)
- Port Output Enable 3 (POE3)
- Watchdog Timer (WDT) 1ch
- General Timer (GTM) 3ch (32bits)
- I2C Bus Interface (I2C) 4ch
- Serial Communication Interface with FIFO (SCIFA) 5ch
- Serial Communication Interface (SCI) 2ch
- Renesas Serial Peripheral Interface (RSPI) 3ch
- A/D Converter (ADC) 2ch
-making it ideal for applications such as entry-class social infrastructure
-gateway control and industrial gateway control. More details can be found at
-below link [0].
-
-[0] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
-
-To build platform specific library and firmwares, provide the
-*PLATFORM=generic* parameter to the top level make command.
-
-Platform Options
----------------
-
-The Renesas RZ/Five platform does not have any platform-specific options.
-
-Building Renesas RZ/Five Platform
---------------------------------
-
-```
-make PLATFORM=generic
-```
-
-DTS Example: (RZ/Five AX45MP)
-----------------------------
-
-```
-	compatible = "renesas,r9a07g043f01", "renesas,r9a07g043";
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		timebase-frequency = <12000000>;
-
-		cpu0: cpu@0 {
-			compatible = "andestech,ax45mp", "riscv";
-			device_type = "cpu";
-			reg = <0x0>;
-			status = "okay";
-			riscv,isa = "rv64imafdc";
-			mmu-type = "riscv,sv39";
-			i-cache-size = <0x8000>;
-			i-cache-line-size = <0x40>;
-			d-cache-size = <0x8000>;
-			d-cache-line-size = <0x40>;
-			clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
-
-			cpu0_intc: interrupt-controller {
-				#interrupt-cells = <1>;
-				compatible = "riscv,cpu-intc";
-				interrupt-controller;
-			};
-		};
-	};
-
-	soc {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		ranges;
-
-		scif0: serial@1004b800 {
-			compatible = "renesas,scif-r9a07g043",
-				     "renesas,scif-r9a07g044";
-			reg = <0 0x1004b800 0 0x400>;
-			interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
-				     <414 IRQ_TYPE_LEVEL_HIGH>,
-				     <415 IRQ_TYPE_LEVEL_HIGH>,
-				     <413 IRQ_TYPE_LEVEL_HIGH>,
-				     <416 IRQ_TYPE_LEVEL_HIGH>,
-				     <416 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "eri", "rxi", "txi",
-					  "bri", "dri", "tei";
-			clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
-			clock-names = "fck";
-			power-domains = <&cpg>;
-			resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
-			status = "disabled";
-		};
-
-		cpg: clock-controller@11010000 {
-			compatible = "renesas,r9a07g043-cpg";
-			reg = <0 0x11010000 0 0x10000>;
-			clocks = <&extal_clk>;
-			clock-names = "extal";
-			#clock-cells = <2>;
-			#reset-cells = <1>;
-			#power-domain-cells = <0>;
-		};
-
-		sysc: system-controller@11020000 {
-			compatible = "renesas,r9a07g043-sysc";
-			reg = <0 0x11020000 0 0x10000>;
-			status = "disabled";
-		};
-
-		pinctrl: pinctrl@11030000 {
-			compatible = "renesas,r9a07g043-pinctrl";
-			reg = <0 0x11030000 0 0x10000>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			#interrupt-cells = <2>;
-			interrupt-controller;
-			gpio-ranges = <&pinctrl 0 0 152>;
-			clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
-			power-domains = <&cpg>;
-			resets = <&cpg R9A07G043_GPIO_RSTN>,
-				 <&cpg R9A07G043_GPIO_PORT_RESETN>,
-				 <&cpg R9A07G043_GPIO_SPARE_RESETN>;
-		};
-
-		plmt0: plmt0@110c0000 {
-			compatible = "andestech,plmt0", "riscv,plmt0";
-			reg = <0x0 0x110c0000 0x0 0x10000>;
-			interrupts-extended = <&cpu0_intc 7>;
-		};
-
-		plic: interrupt-controller@12c00000 {
-			compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
-			#interrupt-cells = <2>;
-			#address-cells = <0>;
-			riscv,ndev = <511>;
-			interrupt-controller;
-			reg = <0x0 0x12c00000 0x0 0x400000>;
-			clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
-			power-domains = <&cpg>;
-			resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
-			interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
-		};
-
-		plicsw: interrupt-controller@13000000 {
-			compatible = "andestech,plicsw";
-			reg = <0x0 0x13000000 0x0 0x400000>;
-			interrupts-extended = <&cpu0_intc 3>;
-			interrupt-controller;
-			#address-cells = <2>;
-			#interrupt-cells = <2>;
-		};
-	};
-```
--- a/docs/platform/sifive_fu540.md
+++ b/docs/platform/sifive_fu540.md
@@ -8,7 +8,7 @@ With QEMU v4.2 or above release, the 'sifive_u' machine can be used to test
 OpenSBI image built for the real hardware as well.

 To build platform specific library and firmwares, provide the
-*PLATFORM=generic* parameter to the top level `make` command.
+*PLATFORM=sifive/fu540* parameter to the top level `make` command.

 Platform Options
 ----------------
@@ -32,10 +32,10 @@ To use Linux v5.2 (or higher), the pre-built DTB (DT binary) from Linux v5.2
 the compile time option *FW_FDT_PATH*.

 ```
-make PLATFORM=generic FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image
+make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image
 or
 (For Linux v5.2 or higher)
-make PLATFORM=generic FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image FW_FDT_PATH=<hifive-unleashed-a00.dtb path from Linux kernel>
+make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image FW_FDT_PATH=<hifive-unleashed-a00.dtb path from Linux kernel>
 ```

 **U-Boot Payload**
@@ -45,7 +45,7 @@ sifive_fu540_defconfig configuration and with U-Boot v2020.01, and up to
 v2021.04. sifive_unleashed_defconfig shall be used with v2021.07 or above.

 ```
-make PLATFORM=generic FW_PAYLOAD_PATH=<u-boot_build_dir>/u-boot-dtb.bin
+make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH=<u-boot_build_dir>/u-boot-dtb.bin
 ```
 For U-Boot v2020.07-rc4 or later releases, SPL support was added in U-Boot.
 Please refer to the detailed U-Boot booting guide available at [U-Boot].
@@ -64,7 +64,7 @@ That's why the generated firmware binary in above steps should be copied to
 the partition of the sdcard with above GUID.

 ```
-dd if=build/platform/generic/firmware/fw_payload.bin of=/dev/disk2s1 bs=1024
+dd if=build/platform/sifive/fu540/firmware/fw_payload.bin of=/dev/disk2s1 bs=1024
 ```

 In my case, it is the first partition is **disk2s1** that has been formatted
@@ -150,7 +150,7 @@ If you want to test OpenSBI with QEMU 'sifive_u' machine, please follow the
 same instructions above, with the exception of not passing FW_FDT_PATH.

 This is because QEMU generates a device tree blob on the fly based on the
-command line parameters, and it's compatible with the one used in the upstream
+command line parameters and it's compatible with the one used in the upstream
 Linux kernel.

 When U-Boot v2021.07 (or higher) is used as the payload, as the SiFive FU540
@@ -161,7 +161,7 @@ U-Boot uses the DTB generated by QEMU, and u-boot.bin should be used as the
 payload image, like:

 ```
-make PLATFORM=generic FW_PAYLOAD_PATH=<u-boot_build_dir>/u-boot.bin
+make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH=<u-boot_build_dir>/u-boot.bin
 ```

 U-Boot v2020.07 release added SPL support to SiFive HiFive Unleashed board,
@@ -179,12 +179,12 @@ The above errors can be safely ignored as we don't run U-Boot SPL under QEMU.
 Run:
 ```
 qemu-system-riscv64 -M sifive_u -m 256M -nographic \
-	-bios build/platform/generic/firmware/fw_payload.bin
+	-bios build/platform/sifive/fu540/firmware/fw_payload.bin
 ```
 or
 ```
 qemu-system-riscv64 -M sifive_u -m 256M -nographic \
-	-bios build/platform/generic/firmware/fw_jump.bin \
+	-bios build/platform/sifive/fu540/firmware/fw_jump.bin \
 	-kernel <uboot_build_dir>/u-boot.bin
 ```

--- a/docs/platform/spike.md
+++ b/docs/platform/spike.md
@@ -43,18 +43,7 @@ make PLATFORM=generic FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Im

 Run:
 ```
-spike -m256 \
-	--initrd <path_to_cpio_ramdisk> \
-	--bootargs 'root=/dev/ram rw console=hvc0 earlycon=sbi' \
-	build/platform/generic/firmware/fw_payload.elf
-```
-or
-```
-spike -m256 \
-	--kernel <linux_build_directory>/arch/riscv/boot/Image \
-	--initrd <path_to_cpio_ramdisk> \
-	--bootargs 'root=/dev/ram rw console=hvc0 earlycon=sbi' \
-	build/platform/generic/firmware/fw_jump.elf
+spike --initrd <path_to_cpio_ramdisk> build/platform/generic/firmware/fw_payload.elf
 ```

 Execution on QEMU RISC-V 64-bit
--- a/docs/platform/thead-c9xx.md
+++ b/docs/platform/thead-c9xx.md
@@ -13,10 +13,10 @@ Platform Options
 ----------------

 The *T-HEAD C9xx* does not have any platform-specific compile options
-because it uses generic platform.
+because it use generic platform.

 ```
-CROSS_COMPILE=riscv64-linux-gnu- PLATFORM=generic /usr/bin/make
+CROSS_COMPILE=riscv64-linux-gnu- PLATFORM=generic FW_PIC=y /usr/bin/make
 ```

 The *T-HEAD C9xx* DTB provided to OpenSBI generic firmwares will usually have
@@ -51,18 +51,23 @@ DTS Example1: (Single core, eg: Allwinner D1 - c906)
 		compatible = "simple-bus";
 		ranges;

+		reset: reset-sample {
+			compatible = "thead,reset-sample";
+			plic-delegate = <0x0 0x101ffffc>;
+		};
+
 		clint0: clint@14000000 {
-			compatible = "allwinner,sun20i-d1-clint";
+			compatible = "riscv,clint0";
 			interrupts-extended = <
 				&cpu0_intc  3 &cpu0_intc  7
 				>;
 			reg = <0x0 0x14000000 0x0 0x04000000>;
+			clint,has-no-64bit-mmio;
 		};

 		intc: interrupt-controller@10000000 {
 			#interrupt-cells = <1>;
-			compatible = "allwinner,sun20i-d1-plic",
-				     "thead,c900-plic";
+			compatible = "riscv,plic0";
 			interrupt-controller;
 			interrupts-extended = <
 				&cpu0_intc  0xffffffff &cpu0_intc  9
@@ -145,6 +150,7 @@ DTS Example2: (Multi cores with soc reset-regs)

 		reset: reset-sample {
 			compatible = "thead,reset-sample";
+			plic-delegate = <0xff 0xd81ffffc>;
 			entry-reg = <0xff 0xff019050>;
 			entry-cnt = <4>;
 			control-reg = <0xff 0xff015004>;
@@ -162,11 +168,12 @@ DTS Example2: (Multi cores with soc reset-regs)
 				&cpu4_intc  3 &cpu4_intc  7
 				>;
 			reg = <0xff 0xdc000000 0x0 0x04000000>;
+			clint,has-no-64bit-mmio;
 		};

 		intc: interrupt-controller@ffd8000000 {
 			#interrupt-cells = <1>;
-			compatible = "thead,c900-plic";
+			compatible = "riscv,plic0";
 			interrupt-controller;
 			interrupts-extended = <
 				&cpu0_intc  0xffffffff &cpu0_intc  9
@@ -187,6 +194,7 @@ DTS Example2: (Multi cores with old reset csrs)
 ```
 	reset: reset-sample {
 		compatible = "thead,reset-sample";
+		plic-delegate = <0xff 0xd81ffffc>;
 		using-csr-reset;
 		csr-copy = <0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc
 			    0x3b0 0x3b1 0x3b2 0x3b3
--- a/docs/platform_guide.md
+++ b/docs/platform_guide.md
@@ -17,7 +17,7 @@ the supported platforms. These firmwares are linked against *libplatsbi.a*.
 Firmware binaries are installed in
 *<install_directory>/platform/<platform_subdir>/bin*. These firmwares can be
 used as executable runtime firmwares on the supported platforms as a replacement
-for the legacy *riscv-pk* boot loader (BBL).
+for the legacy *riskv-pk* boot loader (BBL).

 A complete doxygen-style documentation of *struct sbi_platform* and related
 APIs is available in the file *include/sbi/sbi_platform.h*.
@@ -25,19 +25,18 @@ APIs is available in the file *include/sbi/sbi_platform.h*.
 Adding support for a new platform
 ---------------------------------

-Support for a new platform named *&lt;xyz&gt;* can be added as follows:
+Support for a new platform named *<xyz>* can be added as follows:

-1. Create a directory named *&lt;xyz&gt;* under the *platform/* directory.
-2. Create platform configuration files named *Kconfig* and *configs/defconfig*
-   under the *platform/&lt;xyz&gt;/* directory. These configuration files will
-   provide the build time configuration for the sources to be compiled.
-3. Create a *platform/&lt;xyz&gt;/objects.mk* file for listing the platform
-   object files to be compiled. This file also provides platform-specific
+1. Create a directory named *<xyz>* under the *platform/* directory.
+2. Create a platform configuration file named *config.mk* under the
+   *platform/<xyz>/* directory. This configuration file will provide
   compiler flags, and select firmware options.
-4. Create a *platform/&lt;xyz&gt;/platform.c* file providing a
-   *struct sbi_platform* instance.
+3. Create a *platform/<xyz>/objects.mk* file for listing the
+   platform-specific object files to be compiled.
+4. Create a *platform/<xyz>/platform.c* file providing a *struct sbi_platform*
+   instance.

 A platform support code template is available under the *platform/template*
 directory. Copying this directory and its content as a new directory named
-*&lt;xyz&gt;* under the *platform/* directory will create all the files
-mentioned above.
+*<xyz>* under the *platform/* directory will create all the files mentioned
+above.
--- a/docs/platform_requirements.md
+++ b/docs/platform_requirements.md
@@ -10,7 +10,7 @@ To handle this, we have two types of RISC-V platform requirements:
 2. **Release specific platform requirements** which apply to a OpenSBI
   release and later releases

-Currently, we don't have any **Release specific platform requirements**,
+Currently, we don't have any **Release specific platform requirements**
 but such platform requirements will be added in future.

 Base Platform Requirements
--- a/docs/pmu_support.md
+++ b/docs/pmu_support.md
@@ -1,127 +0,0 @@
-OpenSBI SBI PMU extension support
-==================================
-SBI PMU extension supports allow supervisor software to configure/start/stop
-any performance counter at anytime. Thus, a user can leverage full
-capability of performance analysis tools such as perf if SBI PMU extension is
-enabled. The OpenSBI implementation makes the following assumptions about the
-hardware platform.
-
- * The platform must provide information about PMU event to counter mapping
-via device tree or platform specific hooks. Otherwise, SBI PMU extension will
-not be enabled.
-
- * The platforms should provide information about the PMU event selector values
-that should be encoded in the expected value of MHPMEVENTx while configuring
-MHPMCOUNTERx for that specific event. This can be done via a device tree or
-platform specific hooks. The exact value to be written to he MHPMEVENTx is
-completely depends on platform. Generic platform writes the zero-extended event_idx
-as the expected value for hardware cache/generic events as suggested by the SBI
-specification.
-
-SBI PMU Device Tree Bindings
----------------------------
-
-Platforms may choose to describe PMU event selector and event to counter mapping
-values via device tree. The following sections describe the PMU DT node
-bindings in details.
-
-* **compatible** (Mandatory) - The compatible string of SBI PMU device tree node.
-This DT property must have the value **riscv,pmu**.
-
-* **riscv,event-to-mhpmevent**(Optional) - It represents an ONE-to-ONE mapping
-between a PMU event and the event selector value that platform expects to be
-written to the MHPMEVENTx CSR for that event. The mapping is encoded in a
-table format where each row represents an event. The first column represent the
-event idx where the 2nd & 3rd column represent the event selector value that
-should be encoded in the expected value to be written in MHPMEVENTx.
-This property shouldn't encode any raw hardware event.
-
-* **riscv,event-to-mhpmcounters**(Optional) - It represents a MANY-to-MANY
-mapping between a range of events and all the MHPMCOUNTERx in a bitmap format
-that can be used to monitor these range of events. The information is encoded in
-a table format where each row represents a certain range of events and
-corresponding counters. The first column represents starting of the pmu event id
-and 2nd column represents the end of the pmu event id. The third column
-represent a bitmap of all the MHPMCOUNTERx. This property is mandatory if
-riscv,event-to-mhpmevent is present. Otherwise, it can be omitted. This property
-shouldn't encode any raw event.
-
-* **riscv,raw-event-to-mhpmcounters**(Optional) - It represents an ONE-to-MANY
-or MANY-to-MANY mapping between the raw event(s) and all the MHPMCOUNTERx in
-a bitmap format that can be used to monitor that raw event. The encoding of the
-raw events are platform specific. The information is encoded in a table format
-where each row represents the specific raw event(s). The first column is a 64bit
-match value where the invariant bits of range of events are set. The second
-column is a 64 bit mask that will have all the variant bits of the range of
-events cleared. All other bits should be set in the mask.
-The third column is a 32bit value to represent bitmap of all MHPMCOUNTERx that
-can monitor these set of event(s).
-If a platform directly encodes each raw PMU event as a unique ID, the value of
-select_mask must be 0xffffffff_ffffffff.
-
-*Note:* A platform may choose to provide the mapping between event & counters
-via platform hooks rather than the device tree.
-
-### Example 1
-
-```
-pmu {
-	compatible 			= "riscv,pmu";
-	riscv,event-to-mhpmevent 		= <0x0000B  0x0000 0x0001>;
-	riscv,event-to-mhpmcounters 	= <0x00001 0x00001 0x00000001>,
-						  <0x00002 0x00002 0x00000004>,
-						  <0x00003 0x0000A 0x00000ff8>,
-						  <0x10000 0x10033 0x000ff000>;
-					/* For event ID 0x0002 */
-	riscv,raw-event-to-mhpmcounters = <0x0000 0x0002 0xffffffff 0xffffffff 0x00000f8>,
-					/* For event ID 0-4 */
-					<0x0 0x0 0xffffffff 0xfffffff0 0x00000ff0>,
-					/* For event ID 0xffffffff0000000f - 0xffffffff000000ff */
-					<0xffffffff 0x0 0xffffffff 0xffffff0f 0x00000ff0>;
-};
-```
-
-### Example 2
-
-```
-/*
- * For HiFive Unmatched board. The encodings can be found here
- * https://sifive.cdn.prismic.io/sifive/1a82e600-1f93-4f41-b2d8-86ed8b16acba_fu740-c000-manual-v1p6.pdf
- * This example also binds standard SBI PMU hardware id's to U74 PMU event codes, U74 uses bitfield for
- * events encoding, so several U74 events can be bound to single perf id.
- * See SBI PMU hardware id's in include/sbi/sbi_ecall_interface.h
- */
-pmu {
-	compatible 			= "riscv,pmu";
-	riscv,event-to-mhpmevent =
-/* SBI_PMU_HW_CACHE_REFERENCES -> Instruction cache/ITIM busy | Data cache/DTIM busy */
-				   <0x00003 0x00000000 0x1801>,
-/* SBI_PMU_HW_CACHE_MISSES -> Instruction cache miss | Data cache miss or memory-mapped I/O access */
-				   <0x00004 0x00000000 0x0302>,
-/* SBI_PMU_HW_BRANCH_INSTRUCTIONS -> Conditional branch retired */
-				   <0x00005 0x00000000 0x4000>,
-/* SBI_PMU_HW_BRANCH_MISSES -> Branch direction misprediction | Branch/jump target misprediction */
-				   <0x00006 0x00000000 0x6001>,
-/* L1D_READ_MISS -> Data cache miss or memory-mapped I/O access */
-				   <0x10001 0x00000000 0x0202>,
-/* L1D_WRITE_ACCESS -> Data cache write-back */
-				   <0x10002 0x00000000 0x0402>,
-/* L1I_READ_ACCESS -> Instruction cache miss */
-				   <0x10009 0x00000000 0x0102>,
-/* LL_READ_MISS -> UTLB miss */
-				   <0x10011 0x00000000 0x2002>,
-/* DTLB_READ_MISS -> Data TLB miss */
-				   <0x10019 0x00000000 0x1002>,
-/* ITLB_READ_MISS-> Instruction TLB miss */
-				   <0x10021 0x00000000 0x0802>;
-	riscv,event-to-mhpmcounters = <0x00003 0x00006 0x18>,
-				      <0x10001 0x10002 0x18>,
-				      <0x10009 0x10009 0x18>,
-				      <0x10011 0x10011 0x18>,
-				      <0x10019 0x10019 0x18>,
-				      <0x10021 0x10021 0x18>;
-	riscv,raw-event-to-mhpmcounters = <0x0 0x0 0xffffffff 0xfc0000ff 0x18>,
-					  <0x0 0x1 0xffffffff 0xfff800ff 0x18>,
-					  <0x0 0x2 0xffffffff 0xffffe0ff 0x18>;
-};
-```
--- a/firmware/Kconfig
+++ b/firmware/Kconfig
@@ -1 +0,0 @@
-# SPDX-License-Identifier: BSD-2-Clause
--- a/firmware/fw_base.S
+++ b/firmware/fw_base.S
@@ -65,14 +65,14 @@ _try_lottery:

 	/* Save load address */
 	lla	t0, _load_start
-	lla	t1, _fw_start
+	lla	t1, _start
 	REG_S	t1, 0(t0)

 #ifdef FW_PIC
 	/* relocate the global table content */
 	lla	t0, _link_start
 	REG_L	t0, 0(t0)
-	/* t1 shall has the address of _fw_start */
+	/* t1 shall has the address of _start */
 	sub	t2, t1, t0
 	lla	t3, _runtime_offset
 	REG_S	t2, (t3)
@@ -128,9 +128,9 @@ _relocate:
 	REG_L	t1, 0(t1)
 	lla	t2, _load_start
 	REG_L	t2, 0(t2)
-	beq	t0, t2, _relocate_done
 	sub	t3, t1, t0
 	add	t3, t3, t2
+	beq	t0, t2, _relocate_done
 	lla	t4, _relocate_done
 	sub	t4, t4, t2
 	add	t4, t4, t0
@@ -172,7 +172,7 @@ _relocate_copy_to_upper_loop:
 	blt	t0, t1, _relocate_copy_to_upper_loop
 	jr	t4
 _wait_relocate_copy_done:
-	lla	t0, _fw_start
+	lla	t0, _start
 	lla	t1, _link_start
 	REG_L	t1, 0(t1)
 	beq	t0, t1, _wait_for_boot_hart
@@ -259,7 +259,7 @@ _bss_zero:
 	 * s8 -> HART Stack Size
 	 */
 	lla	a4, platform
-#if __riscv_xlen > 32
+#if __riscv_xlen == 64
 	lwu	s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4)
 	lwu	s8, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(a4)
 #else
@@ -278,14 +278,6 @@ _bss_zero:
 	/* hartid 0 is mandated by ISA */
 	li	t1, 0
 _scratch_init:
-	/*
-	 * The following registers hold values that are computed before
-	 * entering this block, and should remain unchanged.
-	 *
-	 * t3 -> the firmware end address
-	 * s7 -> HART count
-	 * s8 -> HART stack size
-	 */
 	add	tp, t3, zero
 	mul	a5, s8, t1
 	sub	tp, tp, a5
@@ -295,7 +287,10 @@ _scratch_init:
 	/* Initialize scratch space */
 	/* Store fw_start and fw_size in scratch space */
 	lla	a4, _fw_start
-	sub	a5, t3, a4
+	lla	a5, _fw_end
+	mul	t0, s7, s8
+	add	a5, a5, t0
+	sub	a5, a5, a4
 	REG_S	a4, SBI_SCRATCH_FW_START_OFFSET(tp)
 	REG_S	a5, SBI_SCRATCH_FW_SIZE_OFFSET(tp)
 	/* Store next arg1 in scratch space */
@@ -349,7 +344,8 @@ _scratch_init:
 	 * previous booting stage.
 	 */
 	beqz	a1, _fdt_reloc_done
-	/* Mask values in a4 */
+	/* Mask values in a3 and a4 */
+	li	a3, ~(__SIZEOF_POINTER__ - 1)
 	li	a4, 0xff
 	/* t1 = destination FDT start address */
 	MOV_3R	s0, a0, s1, a1, s2, a2
@@ -358,8 +354,10 @@ _scratch_init:
 	MOV_3R	a0, s0, a1, s1, a2, s2
 	beqz	t1, _fdt_reloc_done
 	beq	t1, a1, _fdt_reloc_done
+	and	t1, t1, a3
 	/* t0 = source FDT start address */
 	add	t0, a1, zero
+	and	t0, t0, a3
 	/* t2 = source FDT size in big-endian */
 #if __riscv_xlen == 64
 	lwu	t2, 4(t0)
@@ -503,7 +501,6 @@ _skip_trap_exit_rv32_hyp:
 	/* We don't expect to reach here hence just hang */
 	j	_start_hang

-	.data
 	.align 3
 #ifdef FW_PIC
 _runtime_offset:
@@ -556,39 +553,12 @@ _start_hang:

 	.section .entry, "ax", %progbits
 	.align 3
+	.globl fw_platform_init
 	.weak fw_platform_init
 fw_platform_init:
 	add	a0, a1, zero
 	ret

-	/* Map implicit memcpy() added by compiler to sbi_memcpy() */
-	.section .text
-	.align 3
-	.globl memcpy
-memcpy:
-	tail	sbi_memcpy
-
-	/* Map implicit memset() added by compiler to sbi_memset() */
-	.section .text
-	.align 3
-	.globl memset
-memset:
-	tail	sbi_memset
-
-	/* Map implicit memmove() added by compiler to sbi_memmove() */
-	.section .text
-	.align 3
-	.globl memmove
-memmove:
-	tail	sbi_memmove
-
-	/* Map implicit memcmp() added by compiler to sbi_memcmp() */
-	.section .text
-	.align 3
-	.globl memcmp
-memcmp:
-	tail	sbi_memcmp
-
 .macro	TRAP_SAVE_AND_SETUP_SP_T0
 	/* Swap TP and MSCRATCH */
 	csrrw	tp, CSR_MSCRATCH, tp
--- a/firmware/fw_base.ldS
+++ b/firmware/fw_base.ldS
@@ -8,7 +8,7 @@
 */

 	. = FW_TEXT_START;
-	/* Don't add any section between FW_TEXT_START and _fw_start */
+
 	PROVIDE(_fw_start = .);

 	. = ALIGN(0x1000); /* Need this to create proper sections */
@@ -24,12 +24,14 @@
 		PROVIDE(_text_end = .);
 	}

-	/* End of the code sections */
-
 	. = ALIGN(0x1000); /* Ensure next section is page aligned */

+	/* End of the code sections */
+
 	/* Beginning of the read-only data sections */

+	. = ALIGN(0x1000); /* Ensure next section is page aligned */
+
 	.rodata :
 	{
 		PROVIDE(_rodata_start = .);
@@ -40,10 +42,10 @@

 	/* End of the read-only data sections */

-	. = ALIGN(0x1000); /* Ensure next section is page aligned */
-
 	/* Beginning of the read-write data sections */

+	. = ALIGN(0x1000); /* Ensure next section is page aligned */
+
 	.data :
 	{
 		PROVIDE(_data_start = .);
--- a/firmware/fw_dynamic.S
+++ b/firmware/fw_dynamic.S
@@ -36,7 +36,7 @@ fw_boot_hart:
 	bgt	a0, a1, _bad_dynamic_info

 	/* Read boot HART id */
-	li	a1, FW_DYNAMIC_INFO_VERSION_2
+	li	a1, 0x2
 	blt	a0, a1, 2f
 	REG_L	a0, FW_DYNAMIC_INFO_BOOT_HART_OFFSET(a2)
 	ret
@@ -57,6 +57,14 @@ fw_save_info:
 	lla	a4, _dynamic_next_arg1
 	REG_S	a1, (a4)

+	/* Sanity checks */
+	li	a4, FW_DYNAMIC_INFO_MAGIC_VALUE
+	REG_L	a3, FW_DYNAMIC_INFO_MAGIC_OFFSET(a2)
+	bne	a3, a4, _bad_dynamic_info
+	li	a4, FW_DYNAMIC_INFO_VERSION_MAX
+	REG_L	a3, FW_DYNAMIC_INFO_VERSION_OFFSET(a2)
+	bgt	a3, a4, _bad_dynamic_info
+
 	/* Save version == 0x1 fields */
 	lla	a4, _dynamic_next_addr
 	REG_L	a3, FW_DYNAMIC_INFO_NEXT_ADDR_OFFSET(a2)
@@ -69,7 +77,7 @@ fw_save_info:
 	REG_S	a3, (a4)

 	/* Save version == 0x2 fields */
-	li	a4, FW_DYNAMIC_INFO_VERSION_2
+	li	a4, 0x2
 	REG_L	a3, FW_DYNAMIC_INFO_VERSION_OFFSET(a2)
 	blt	a3, a4, 2f
 	lla	a4, _dynamic_boot_hart
--- a/firmware/objects.mk
+++ b/firmware/objects.mk
@@ -14,14 +14,14 @@ firmware-asflags-y +=
 firmware-ldflags-y +=

 ifndef FW_PIC
-FW_PIC := $(OPENSBI_LD_PIE)
+FW_PIC := y
 endif

 ifeq ($(FW_PIC),y)
 firmware-genflags-y +=	-DFW_PIC
 firmware-asflags-y  +=	-fpic
 firmware-cflags-y   +=	-fPIE -pie
-firmware-ldflags-y  +=	-Wl,--no-dynamic-linker -Wl,-pie
+firmware-ldflags-y  +=  -Wl,--no-dynamic-linker
 endif

 ifdef FW_TEXT_START
--- a/firmware/payloads/test.elf.ldS
+++ b/firmware/payloads/test.elf.ldS
@@ -33,12 +33,14 @@ SECTIONS
 		PROVIDE(_text_end = .);
 	}

-	/* End of the code sections */
-
 	. = ALIGN(0x1000); /* Ensure next section is page aligned */

+	/* End of the code sections */
+
 	/* Beginning of the read-only data sections */

+	. = ALIGN(0x1000); /* Ensure next section is page aligned */
+
 	.rodata :
 	{
 		PROVIDE(_rodata_start = .);
@@ -49,10 +51,10 @@ SECTIONS

 	/* End of the read-only data sections */

-	. = ALIGN(0x1000); /* Ensure next section is page aligned */
-
 	/* Beginning of the read-write data sections */

+	. = ALIGN(0x1000); /* Ensure next section is page aligned */
+
 	.data :
 	{
 		PROVIDE(_data_start = .);
--- a/firmware/payloads/test_main.c
+++ b/firmware/payloads/test_main.c
@@ -9,25 +9,24 @@

 #include <sbi/sbi_ecall_interface.h>

-#define SBI_ECALL(__eid, __fid, __a0, __a1, __a2)                             \
+#define SBI_ECALL(__num, __a0, __a1, __a2)                                    \
 	({                                                                    \
 		register unsigned long a0 asm("a0") = (unsigned long)(__a0);  \
 		register unsigned long a1 asm("a1") = (unsigned long)(__a1);  \
 		register unsigned long a2 asm("a2") = (unsigned long)(__a2);  \
-		register unsigned long a6 asm("a6") = (unsigned long)(__fid); \
-		register unsigned long a7 asm("a7") = (unsigned long)(__eid); \
+		register unsigned long a7 asm("a7") = (unsigned long)(__num); \
 		asm volatile("ecall"                                          \
 			     : "+r"(a0)                                       \
-			     : "r"(a1), "r"(a2), "r"(a6), "r"(a7)             \
+			     : "r"(a1), "r"(a2), "r"(a7)                      \
 			     : "memory");                                     \
 		a0;                                                           \
 	})

-#define SBI_ECALL_0(__eid, __fid) SBI_ECALL(__eid, __fid, 0, 0, 0)
-#define SBI_ECALL_1(__eid, __fid, __a0) SBI_ECALL(__eid, __fid, __a0, 0, 0)
-#define SBI_ECALL_2(__eid, __fid, __a0, __a1) SBI_ECALL(__eid, __fid, __a0, __a1, 0)
+#define SBI_ECALL_0(__num) SBI_ECALL(__num, 0, 0, 0)
+#define SBI_ECALL_1(__num, __a0) SBI_ECALL(__num, __a0, 0, 0)
+#define SBI_ECALL_2(__num, __a0, __a1) SBI_ECALL(__num, __a0, __a1, 0)

-#define sbi_ecall_console_putc(c) SBI_ECALL_1(SBI_EXT_0_1_CONSOLE_PUTCHAR, 0, (c))
+#define sbi_ecall_console_putc(c) SBI_ECALL_1(SBI_EXT_0_1_CONSOLE_PUTCHAR, (c))

 static inline void sbi_ecall_console_puts(const char *str)
 {
--- a/include/sbi/fw_dynamic.h
+++ b/include/sbi/fw_dynamic.h
@@ -15,24 +15,23 @@
 /* clang-format off */

 /** Offset of magic member in fw_dynamic_info */
-#define FW_DYNAMIC_INFO_MAGIC_OFFSET		(0 * __SIZEOF_LONG__)
+#define FW_DYNAMIC_INFO_MAGIC_OFFSET		(0 * __SIZEOF_POINTER__)
 /** Offset of version member in fw_dynamic_info */
-#define FW_DYNAMIC_INFO_VERSION_OFFSET		(1 * __SIZEOF_LONG__)
+#define FW_DYNAMIC_INFO_VERSION_OFFSET		(1 * __SIZEOF_POINTER__)
 /** Offset of next_addr member in fw_dynamic_info (version >= 1) */
-#define FW_DYNAMIC_INFO_NEXT_ADDR_OFFSET	(2 * __SIZEOF_LONG__)
+#define FW_DYNAMIC_INFO_NEXT_ADDR_OFFSET	(2 * __SIZEOF_POINTER__)
 /** Offset of next_mode member in fw_dynamic_info  (version >= 1) */
-#define FW_DYNAMIC_INFO_NEXT_MODE_OFFSET	(3 * __SIZEOF_LONG__)
+#define FW_DYNAMIC_INFO_NEXT_MODE_OFFSET	(3 * __SIZEOF_POINTER__)
 /** Offset of options member in fw_dynamic_info  (version >= 1) */
-#define FW_DYNAMIC_INFO_OPTIONS_OFFSET		(4 * __SIZEOF_LONG__)
+#define FW_DYNAMIC_INFO_OPTIONS_OFFSET		(4 * __SIZEOF_POINTER__)
 /** Offset of boot_hart member in fw_dynamic_info  (version >= 2) */
-#define FW_DYNAMIC_INFO_BOOT_HART_OFFSET	(5 * __SIZEOF_LONG__)
+#define FW_DYNAMIC_INFO_BOOT_HART_OFFSET	(5 * __SIZEOF_POINTER__)

 /** Expected value of info magic ('OSBI' ascii string in hex) */
 #define FW_DYNAMIC_INFO_MAGIC_VALUE		0x4942534f

 /** Maximum supported info version */
-#define FW_DYNAMIC_INFO_VERSION_2		0x2
-#define FW_DYNAMIC_INFO_VERSION_MAX		FW_DYNAMIC_INFO_VERSION_2
+#define FW_DYNAMIC_INFO_VERSION_MAX		0x2

 /** Possible next mode values */
 #define FW_DYNAMIC_INFO_NEXT_MODE_U		0x0
@@ -75,41 +74,6 @@ struct fw_dynamic_info {
 	unsigned long boot_hart;
 } __packed;

-/**
- * Prevent modification of struct fw_dynamic_info from affecting
- * FW_DYNAMIC_INFO_xxx_OFFSET
- */
-_Static_assert(
-	offsetof(struct fw_dynamic_info, magic)
-		== FW_DYNAMIC_INFO_MAGIC_OFFSET,
-	"struct fw_dynamic_info definition has changed, please redefine "
-	"FW_DYNAMIC_INFO_MAGIC_OFFSET");
-_Static_assert(
-	offsetof(struct fw_dynamic_info, version)
-		== FW_DYNAMIC_INFO_VERSION_OFFSET,
-	"struct fw_dynamic_info definition has changed, please redefine "
-	"FW_DYNAMIC_INFO_VERSION_OFFSET");
-_Static_assert(
-	offsetof(struct fw_dynamic_info, next_addr)
-		== FW_DYNAMIC_INFO_NEXT_ADDR_OFFSET,
-	"struct fw_dynamic_info definition has changed, please redefine "
-	"FW_DYNAMIC_INFO_NEXT_ADDR_OFFSET");
-_Static_assert(
-	offsetof(struct fw_dynamic_info, next_mode)
-		== FW_DYNAMIC_INFO_NEXT_MODE_OFFSET,
-	"struct fw_dynamic_info definition has changed, please redefine "
-	"FW_DYNAMIC_INFO_NEXT_MODE_OFFSET");
-_Static_assert(
-	offsetof(struct fw_dynamic_info, options)
-		== FW_DYNAMIC_INFO_OPTIONS_OFFSET,
-	"struct fw_dynamic_info definition has changed, please redefine "
-	"FW_DYNAMIC_INFO_OPTIONS_OFFSET");
-_Static_assert(
-	offsetof(struct fw_dynamic_info, boot_hart)
-		== FW_DYNAMIC_INFO_BOOT_HART_OFFSET,
-	"struct fw_dynamic_info definition has changed, please redefine "
-	"FW_DYNAMIC_INFO_BOOT_HART_OFFSET");
-
 #endif

 #endif
--- a/include/sbi/riscv_encoding.h
+++ b/include/sbi/riscv_encoding.h
@@ -25,7 +25,7 @@
 #define MSTATUS_MPP			(_UL(3) << MSTATUS_MPP_SHIFT)
 #define MSTATUS_FS			_UL(0x00006000)
 #define MSTATUS_XS			_UL(0x00018000)
-#define MSTATUS_VS			_UL(0x00000600)
+#define MSTATUS_VS			_UL(0x01800000)
 #define MSTATUS_MPRV			_UL(0x00020000)
 #define MSTATUS_SUM			_UL(0x00040000)
 #define MSTATUS_MXR			_UL(0x00080000)
@@ -38,14 +38,10 @@
 #define MSTATUS_SXL			_ULL(0x0000000C00000000)
 #define MSTATUS_SBE			_ULL(0x0000001000000000)
 #define MSTATUS_MBE			_ULL(0x0000002000000000)
-#define MSTATUS_GVA			_ULL(0x0000004000000000)
-#define MSTATUS_GVA_SHIFT		38
 #define MSTATUS_MPV			_ULL(0x0000008000000000)
 #else
 #define MSTATUSH_SBE			_UL(0x00000010)
 #define MSTATUSH_MBE			_UL(0x00000020)
-#define MSTATUSH_GVA			_UL(0x00000040)
-#define MSTATUSH_GVA_SHIFT		6
 #define MSTATUSH_MPV			_UL(0x00000080)
 #endif
 #define MSTATUS32_SD			_UL(0x80000000)
@@ -90,7 +86,6 @@
 #define IRQ_VS_EXT			10
 #define IRQ_M_EXT			11
 #define IRQ_S_GEXT			12
-#define IRQ_PMU_OVF			13

 #define MIP_SSIP			(_UL(1) << IRQ_S_SOFT)
 #define MIP_VSSIP			(_UL(1) << IRQ_VS_SOFT)
@@ -102,7 +97,6 @@
 #define MIP_VSEIP			(_UL(1) << IRQ_VS_EXT)
 #define MIP_MEIP			(_UL(1) << IRQ_M_EXT)
 #define MIP_SGEIP			(_UL(1) << IRQ_S_GEXT)
-#define MIP_LCOFIP			(_UL(1) << IRQ_PMU_OVF)

 #define SIP_SSIP			MIP_SSIP
 #define SIP_STIP			MIP_STIP
@@ -177,52 +171,6 @@
 #define HGATP_MODE_SHIFT		HGATP32_MODE_SHIFT
 #endif

-#define TOPI_IID_SHIFT			16
-#define TOPI_IID_MASK			0xfff
-#define TOPI_IPRIO_MASK		0xff
-
-#if __riscv_xlen == 64
-#define MHPMEVENT_OF			(_UL(1) << 63)
-#define MHPMEVENT_MINH			(_UL(1) << 62)
-#define MHPMEVENT_SINH			(_UL(1) << 61)
-#define MHPMEVENT_UINH			(_UL(1) << 60)
-#define MHPMEVENT_VSINH			(_UL(1) << 59)
-#define MHPMEVENT_VUINH			(_UL(1) << 58)
-#else
-#define MHPMEVENTH_OF			(_ULL(1) << 31)
-#define MHPMEVENTH_MINH			(_ULL(1) << 30)
-#define MHPMEVENTH_SINH			(_ULL(1) << 29)
-#define MHPMEVENTH_UINH			(_ULL(1) << 28)
-#define MHPMEVENTH_VSINH		(_ULL(1) << 27)
-#define MHPMEVENTH_VUINH		(_ULL(1) << 26)
-
-#define MHPMEVENT_OF			(MHPMEVENTH_OF << 32)
-#define MHPMEVENT_MINH			(MHPMEVENTH_MINH << 32)
-#define MHPMEVENT_SINH			(MHPMEVENTH_SINH << 32)
-#define MHPMEVENT_UINH			(MHPMEVENTH_UINH << 32)
-#define MHPMEVENT_VSINH			(MHPMEVENTH_VSINH << 32)
-#define MHPMEVENT_VUINH			(MHPMEVENTH_VUINH << 32)
-
-#endif
-
-#define MHPMEVENT_SSCOF_MASK		_ULL(0xFFFF000000000000)
-
-#if __riscv_xlen > 32
-#define ENVCFG_STCE			(_ULL(1) << 63)
-#define ENVCFG_PBMTE			(_ULL(1) << 62)
-#else
-#define ENVCFGH_STCE			(_UL(1) << 31)
-#define ENVCFGH_PBMTE			(_UL(1) << 30)
-#endif
-#define ENVCFG_CBZE			(_UL(1) << 7)
-#define ENVCFG_CBCFE			(_UL(1) << 6)
-#define ENVCFG_CBIE_SHIFT		4
-#define ENVCFG_CBIE			(_UL(0x3) << ENVCFG_CBIE_SHIFT)
-#define ENVCFG_CBIE_ILL			_UL(0x0)
-#define ENVCFG_CBIE_FLUSH		_UL(0x1)
-#define ENVCFG_CBIE_INV			_UL(0x3)
-#define ENVCFG_FIOM			_UL(0x1)
-
 /* ===== User-level CSRs ===== */

 /* User Trap Setup (N-extension) */
@@ -312,13 +260,12 @@

 /* Supervisor Trap Setup */
 #define CSR_SSTATUS			0x100
+#define CSR_SEDELEG			0x102
+#define CSR_SIDELEG			0x103
 #define CSR_SIE				0x104
 #define CSR_STVEC			0x105
 #define CSR_SCOUNTEREN			0x106

-/* Supervisor Configuration */
-#define CSR_SENVCFG			0x10a
-
 /* Supervisor Trap Handling */
 #define CSR_SSCRATCH			0x140
 #define CSR_SEPC			0x141
@@ -326,31 +273,9 @@
 #define CSR_STVAL			0x143
 #define CSR_SIP				0x144

-/* Sstc extension */
-#define CSR_STIMECMP			0x14D
-#define CSR_STIMECMPH			0x15D
-
 /* Supervisor Protection and Translation */
 #define CSR_SATP			0x180

-/* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */
-#define CSR_SISELECT			0x150
-#define CSR_SIREG			0x151
-
-/* Supervisor-Level Interrupts (AIA) */
-#define CSR_STOPEI			0x15c
-#define CSR_STOPI			0xdb0
-
-/* Supervisor-Level High-Half CSRs (AIA) */
-#define CSR_SIEH			0x114
-#define CSR_SIPH			0x154
-
-/* Supervisor stateen CSRs */
-#define CSR_SSTATEEN0			0x10C
-#define CSR_SSTATEEN1			0x10D
-#define CSR_SSTATEEN2			0x10E
-#define CSR_SSTATEEN3			0x10F
-
 /* ===== Hypervisor-level CSRs ===== */

 /* Hypervisor Trap Setup (H-extension) */
@@ -361,10 +286,6 @@
 #define CSR_HCOUNTEREN			0x606
 #define CSR_HGEIE			0x607

-/* Hypervisor Configuration */
-#define CSR_HENVCFG			0x60a
-#define CSR_HENVCFGH			0x61a
-
 /* Hypervisor Trap Handling (H-extension) */
 #define CSR_HTVAL			0x643
 #define CSR_HIP				0x644
@@ -390,39 +311,6 @@
 #define CSR_VSIP			0x244
 #define CSR_VSATP			0x280

-/* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */
-#define CSR_HVIEN			0x608
-#define CSR_HVICTL			0x609
-#define CSR_HVIPRIO1			0x646
-#define CSR_HVIPRIO2			0x647
-
-/* VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) */
-#define CSR_VSISELECT			0x250
-#define CSR_VSIREG			0x251
-
-/* VS-Level Interrupts (H-extension with AIA) */
-#define CSR_VSTOPEI			0x25c
-#define CSR_VSTOPI			0xeb0
-
-/* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
-#define CSR_HIDELEGH			0x613
-#define CSR_HVIENH			0x618
-#define CSR_HVIPH			0x655
-#define CSR_HVIPRIO1H			0x656
-#define CSR_HVIPRIO2H			0x657
-#define CSR_VSIEH			0x214
-#define CSR_VSIPH			0x254
-
-/* Hypervisor stateen CSRs */
-#define CSR_HSTATEEN0			0x60C
-#define CSR_HSTATEEN0H			0x61C
-#define CSR_HSTATEEN1			0x60D
-#define CSR_HSTATEEN1H			0x61D
-#define CSR_HSTATEEN2			0x60E
-#define CSR_HSTATEEN2H			0x61E
-#define CSR_HSTATEEN3			0x60F
-#define CSR_HSTATEEN3H			0x61F
-
 /* ===== Machine-level CSRs ===== */

 /* Machine Information Registers */
@@ -441,10 +329,6 @@
 #define CSR_MCOUNTEREN			0x306
 #define CSR_MSTATUSH			0x310

-/* Machine Configuration */
-#define CSR_MENVCFG			0x30a
-#define CSR_MENVCFGH			0x31a
-
 /* Machine Trap Handling */
 #define CSR_MSCRATCH			0x340
 #define CSR_MEPC			0x341
@@ -632,40 +516,6 @@
 #define CSR_MHPMEVENT30			0x33e
 #define CSR_MHPMEVENT31			0x33f

-/* For RV32 */
-#define CSR_MHPMEVENT3H			0x723
-#define CSR_MHPMEVENT4H			0x724
-#define CSR_MHPMEVENT5H			0x725
-#define CSR_MHPMEVENT6H			0x726
-#define CSR_MHPMEVENT7H			0x727
-#define CSR_MHPMEVENT8H			0x728
-#define CSR_MHPMEVENT9H			0x729
-#define CSR_MHPMEVENT10H		0x72a
-#define CSR_MHPMEVENT11H		0x72b
-#define CSR_MHPMEVENT12H		0x72c
-#define CSR_MHPMEVENT13H		0x72d
-#define CSR_MHPMEVENT14H		0x72e
-#define CSR_MHPMEVENT15H		0x72f
-#define CSR_MHPMEVENT16H		0x730
-#define CSR_MHPMEVENT17H		0x731
-#define CSR_MHPMEVENT18H		0x732
-#define CSR_MHPMEVENT19H		0x733
-#define CSR_MHPMEVENT20H		0x734
-#define CSR_MHPMEVENT21H		0x735
-#define CSR_MHPMEVENT22H		0x736
-#define CSR_MHPMEVENT23H		0x737
-#define CSR_MHPMEVENT24H		0x738
-#define CSR_MHPMEVENT25H		0x739
-#define CSR_MHPMEVENT26H		0x73a
-#define CSR_MHPMEVENT27H		0x73b
-#define CSR_MHPMEVENT28H		0x73c
-#define CSR_MHPMEVENT29H		0x73d
-#define CSR_MHPMEVENT30H		0x73e
-#define CSR_MHPMEVENT31H		0x73f
-
-/* Counter Overflow CSR */
-#define CSR_SCOUNTOVF			0xda0
-
 /* Debug/Trace Registers */
 #define CSR_TSELECT			0x7a0
 #define CSR_TDATA1			0x7a1
@@ -678,36 +528,6 @@
 #define CSR_DSCRATCH0			0x7b2
 #define CSR_DSCRATCH1			0x7b3

-/* Machine-Level Window to Indirectly Accessed Registers (AIA) */
-#define CSR_MISELECT			0x350
-#define CSR_MIREG			0x351
-
-/* Machine-Level Interrupts (AIA) */
-#define CSR_MTOPEI			0x35c
-#define CSR_MTOPI			0xfb0
-
-/* Virtual Interrupts for Supervisor Level (AIA) */
-#define CSR_MVIEN			0x308
-#define CSR_MVIP			0x309
-
-/* Smstateen extension registers */
-/* Machine stateen CSRs */
-#define CSR_MSTATEEN0			0x30C
-#define CSR_MSTATEEN0H			0x31C
-#define CSR_MSTATEEN1			0x30D
-#define CSR_MSTATEEN1H			0x31D
-#define CSR_MSTATEEN2			0x30E
-#define CSR_MSTATEEN2H			0x31E
-#define CSR_MSTATEEN3			0x30F
-#define CSR_MSTATEEN3H			0x31F
-
-/* Machine-Level High-Half CSRs (AIA) */
-#define CSR_MIDELEGH			0x313
-#define CSR_MIEH			0x314
-#define CSR_MVIENH			0x318
-#define CSR_MVIPH			0x319
-#define CSR_MIPH			0x354
-
 /* ===== Trap/Exception Causes ===== */

 #define CAUSE_MISALIGNED_FETCH		0x0
@@ -730,23 +550,6 @@
 #define CAUSE_VIRTUAL_INST_FAULT	0x16
 #define CAUSE_STORE_GUEST_PAGE_FAULT	0x17

-/* Common defines for all smstateen */
-#define SMSTATEEN_MAX_COUNT		4
-#define SMSTATEEN0_CS_SHIFT		0
-#define SMSTATEEN0_CS			(_ULL(1) << SMSTATEEN0_CS_SHIFT)
-#define SMSTATEEN0_FCSR_SHIFT		1
-#define SMSTATEEN0_FCSR			(_ULL(1) << SMSTATEEN0_FCSR_SHIFT)
-#define SMSTATEEN0_IMSIC_SHIFT		58
-#define SMSTATEEN0_IMSIC		(_ULL(1) << SMSTATEEN0_IMSIC_SHIFT)
-#define SMSTATEEN0_AIA_SHIFT		59
-#define SMSTATEEN0_AIA			(_ULL(1) << SMSTATEEN0_AIA_SHIFT)
-#define SMSTATEEN0_SVSLCT_SHIFT		60
-#define SMSTATEEN0_SVSLCT		(_ULL(1) << SMSTATEEN0_SVSLCT_SHIFT)
-#define SMSTATEEN0_HSENVCFG_SHIFT	62
-#define SMSTATEEN0_HSENVCFG		(_ULL(1) << SMSTATEEN0_HSENVCFG_SHIFT)
-#define SMSTATEEN_STATEN_SHIFT		63
-#define SMSTATEEN_STATEN		(_ULL(1) << SMSTATEEN_STATEN_SHIFT)
-
 /* ===== Instruction Encodings ===== */

 #define INSN_MATCH_LB			0x3
@@ -822,29 +625,6 @@
 #define INSN_MASK_WFI			0xffffff00
 #define INSN_MATCH_WFI			0x10500000

-#define INSN_MASK_FENCE_TSO		0xffffffff
-#define INSN_MATCH_FENCE_TSO		0x8330000f
-
-#if __riscv_xlen == 64
-
-/* 64-bit read for VS-stage address translation (RV64) */
-#define INSN_PSEUDO_VS_LOAD		0x00003000
-
-/* 64-bit write for VS-stage address translation (RV64) */
-#define INSN_PSEUDO_VS_STORE	0x00003020
-
-#elif __riscv_xlen == 32
-
-/* 32-bit read for VS-stage address translation (RV32) */
-#define INSN_PSEUDO_VS_LOAD		0x00002000
-
-/* 32-bit write for VS-stage address translation (RV32) */
-#define INSN_PSEUDO_VS_STORE	0x00002020
-
-#else
-#error "Unexpected __riscv_xlen"
-#endif
-
 #define INSN_16BIT_MASK			0x3
 #define INSN_32BIT_MASK			0x1c

--- a/include/sbi/riscv_fp.h
+++ b/include/sbi/riscv_fp.h
@@ -42,28 +42,15 @@
 			: "t0");                                                                            \
 	})
 #define init_fp_reg(i) SET_F32_REG((i) << 3, 3, 0, 0)
-
-#if __riscv_xlen == 64
 #define GET_F64_REG(insn, pos, regs)                                                                    \
 	({                                                                                              \
-		register ulong value asm("a0") = SHIFT_RIGHT(insn, (pos)-3) & 0xf8;                     \
+		register ulong value asm("a0") =                                                        \
+			SHIFT_RIGHT(insn, (pos)-3) & 0xf8;                                              \
 		ulong tmp;                                                                              \
 		asm("1: auipc %0, %%pcrel_hi(get_f64_reg); add %0, %0, %1; jalr t0, %0, %%pcrel_lo(1b)" \
 		    : "=&r"(tmp), "+&r"(value)::"t0");                                                  \
-		value;                                                                                  \
+		sizeof(ulong) == 4 ? *(int64_t *)value : (int64_t)value;                                \
 	})
-#else
-#define GET_F64_REG(insn, pos, regs)                                                                     \
-	({                                                                                               \
-		u64 value;                                                                               \
-		ulong offset = SHIFT_RIGHT(insn, (pos)-3) & 0xf8;                                        \
-		register ulong ptr asm("a0") = (ulong)&value;                                            \
-		asm ("1: auipc t1, %%pcrel_hi(get_f64_reg); add t1, t1, %2; jalr t0, t1, %%pcrel_lo(1b)" \
-		    : "=m"(value) : "r"(ptr), "r"(offset) : "t0", "t1");                                 \
-		value;                                                                                   \
-	})
-#endif
-
 #define SET_F64_REG(insn, pos, regs, val)                                                                   \
 	({                                                                                                  \
 		uint64_t __val = (val);                                                                     \
--- a/include/sbi/riscv_locks.h
+++ b/include/sbi/riscv_locks.h
@@ -34,9 +34,9 @@ typedef struct {
 #define DEFINE_SPIN_LOCK(x)	\
 	spinlock_t SPIN_LOCK_INIT(x)

-bool spin_lock_check(spinlock_t *lock);
+int spin_lock_check(spinlock_t *lock);

-bool spin_trylock(spinlock_t *lock);
+int spin_trylock(spinlock_t *lock);

 void spin_lock(spinlock_t *lock);

--- a/include/sbi/sbi_bitops.h
+++ b/include/sbi/sbi_bitops.h
@@ -37,12 +37,47 @@
 	(((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h))))

 /**
- * sbi_ffs - find first (less-significant) set bit in a long word.
+ * ffs - Find first bit set
+ * @x: the word to search
+ *
+ * This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+static inline int ffs(int x)
+{
+	int r = 1;
+
+	if (!x)
+		return 0;
+	if (!(x & 0xffff)) {
+		x >>= 16;
+		r += 16;
+	}
+	if (!(x & 0xff)) {
+		x >>= 8;
+		r += 8;
+	}
+	if (!(x & 0xf)) {
+		x >>= 4;
+		r += 4;
+	}
+	if (!(x & 3)) {
+		x >>= 2;
+		r += 2;
+	}
+	if (!(x & 1))
+		r += 1;
+	return r;
+}
+
+/**
+ * __ffs - find first bit in word.
 * @word: The word to search
 *
 * Undefined if no bit exists, so code should check against 0 first.
 */
-static inline int sbi_ffs(unsigned long word)
+static inline int __ffs(unsigned long word)
 {
 	int num = 0;

@@ -74,20 +109,55 @@ static inline int sbi_ffs(unsigned long word)
 }

 /*
- * sbi_ffz - find first zero in word.
+ * ffz - find first zero in word.
 * @word: The word to search
 *
 * Undefined if no zero exists, so code should check against ~0UL first.
 */
-#define sbi_ffz(x) sbi_ffs(~(x))
+#define ffz(x) __ffs(~(x))

 /**
- * sbi_fls - find last (most-significant) set bit in a long word
+ * fls - find last (most-significant) bit set
+ * @x: the word to search
+ *
+ * This is defined the same way as ffs.
+ * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
+ */
+
+static inline int fls(int x)
+{
+	int r = 32;
+
+	if (!x)
+		return 0;
+	if (!(x & 0xffff0000u)) {
+		x <<= 16;
+		r -= 16;
+	}
+	if (!(x & 0xff000000u)) {
+		x <<= 8;
+		r -= 8;
+	}
+	if (!(x & 0xf0000000u)) {
+		x <<= 4;
+		r -= 4;
+	}
+	if (!(x & 0xc0000000u)) {
+		x <<= 2;
+		r -= 2;
+	}
+	if (!(x & 0x80000000u))
+		r -= 1;
+	return r;
+}
+
+/**
+ * __fls - find last (most-significant) set bit in a long word
 * @word: the word to search
 *
 * Undefined if no set bit exists, so code should check against 0 first.
 */
-static inline unsigned long sbi_fls(unsigned long word)
+static inline unsigned long __fls(unsigned long word)
 {
 	int num = BITS_PER_LONG - 1;

--- a/include/sbi/sbi_console.h
+++ b/include/sbi/sbi_console.h
@@ -43,8 +43,6 @@ int __printf(1, 2) sbi_printf(const char *format, ...);

 int __printf(1, 2) sbi_dprintf(const char *format, ...);

-void __printf(1, 2) __attribute__((noreturn)) sbi_panic(const char *format, ...);
-
 const struct sbi_console_device *sbi_console_get_device(void);

 void sbi_console_set_device(const struct sbi_console_device *dev);
@@ -53,9 +51,4 @@ struct sbi_scratch;

 int sbi_console_init(struct sbi_scratch *scratch);

-#define SBI_ASSERT(cond, args) do { \
-	if (unlikely(!(cond))) \
-		sbi_panic args; \
-} while (0)
-
 #endif
--- a/include/sbi/sbi_domain.h
+++ b/include/sbi/sbi_domain.h
@@ -78,6 +78,8 @@ struct sbi_domain {
 	unsigned long next_mode;
 	/** Is domain allowed to reset the system */
 	bool system_reset_allowed;
+	/** Is domain allowed to suspend the system */
+	bool system_suspend_allowed;
 };

 /** The root domain instance */
@@ -174,26 +176,10 @@ int sbi_domain_register(struct sbi_domain *dom,
 * Add a memory region to the root domain
 * @param reg pointer to the memory region to be added
 *
- * @return 0 on success
- * @return SBI_EALREADY if memory region conflicts with the existing one
- * @return SBI_EINVAL otherwise
+ * @return 0 on success and negative error code on failure
 */
 int sbi_domain_root_add_memregion(const struct sbi_domain_memregion *reg);

-/**
- * Add a memory range with its flags to the root domain
- * @param addr start physical address of memory range
- * @param size physical size of memory range
- * @param align alignment of memory region
- * @param region_flags memory range flags
- *
- * @return 0 on success
- * @return SBI_EALREADY if memory region conflicts with the existing one
- * @return SBI_EINVAL otherwise
- */
-int sbi_domain_root_add_memrange(unsigned long addr, unsigned long size,
-			   unsigned long align, unsigned long region_flags);
-
 /** Finalize domain tables and startup non-root domains */
 int sbi_domain_finalize(struct sbi_scratch *scratch, u32 cold_hartid);

--- a/include/sbi/sbi_ecall.h
+++ b/include/sbi/sbi_ecall.h
@@ -13,8 +13,8 @@
 #include <sbi/sbi_types.h>
 #include <sbi/sbi_list.h>

-#define SBI_ECALL_VERSION_MAJOR		1
-#define SBI_ECALL_VERSION_MINOR		0
+#define SBI_ECALL_VERSION_MAJOR		0
+#define SBI_ECALL_VERSION_MINOR		3
 #define SBI_OPENSBI_IMPID		1

 struct sbi_trap_regs;
@@ -31,6 +31,16 @@ struct sbi_ecall_extension {
 		       struct sbi_trap_info *out_trap);
 };

+extern struct sbi_ecall_extension ecall_base;
+extern struct sbi_ecall_extension ecall_legacy;
+extern struct sbi_ecall_extension ecall_time;
+extern struct sbi_ecall_extension ecall_rfence;
+extern struct sbi_ecall_extension ecall_ipi;
+extern struct sbi_ecall_extension ecall_vendor;
+extern struct sbi_ecall_extension ecall_hsm;
+extern struct sbi_ecall_extension ecall_srst;
+extern struct sbi_ecall_extension ecall_susp;
+
 u16 sbi_ecall_version_major(void);

 u16 sbi_ecall_version_minor(void);
--- a/include/sbi/sbi_ecall_interface.h
+++ b/include/sbi/sbi_ecall_interface.h
@@ -28,7 +28,7 @@
 #define SBI_EXT_RFENCE				0x52464E43
 #define SBI_EXT_HSM				0x48534D
 #define SBI_EXT_SRST				0x53525354
-#define SBI_EXT_PMU				0x504D55
+#define SBI_EXT_SUSP				0x53555350

 /* SBI function IDs for BASE extension*/
 #define SBI_EXT_BASE_GET_SPEC_VERSION		0x0
@@ -38,6 +38,9 @@
 #define SBI_EXT_BASE_GET_MVENDORID		0x4
 #define SBI_EXT_BASE_GET_MARCHID		0x5
 #define SBI_EXT_BASE_GET_MIMPID			0x6
+#define SBI_EXT_BASE_RESET_C906L		0x7
+#define SBI_EXT_BASE_RST_C906L			0x8
+#define SBI_EXT_BASE_UNRST_C906L		0x9

 /* SBI function IDs for TIME extension*/
 #define SBI_EXT_TIME_SET_TIMER			0x0
@@ -92,145 +95,6 @@
 #define SBI_SRST_RESET_REASON_NONE	0x0
 #define SBI_SRST_RESET_REASON_SYSFAIL	0x1

-/* SBI function IDs for PMU extension */
-#define SBI_EXT_PMU_NUM_COUNTERS	0x0
-#define SBI_EXT_PMU_COUNTER_GET_INFO	0x1
-#define SBI_EXT_PMU_COUNTER_CFG_MATCH	0x2
-#define SBI_EXT_PMU_COUNTER_START	0x3
-#define SBI_EXT_PMU_COUNTER_STOP	0x4
-#define SBI_EXT_PMU_COUNTER_FW_READ	0x5
-
-/** General pmu event codes specified in SBI PMU extension */
-enum sbi_pmu_hw_generic_events_t {
-	SBI_PMU_HW_NO_EVENT			= 0,
-	SBI_PMU_HW_CPU_CYCLES			= 1,
-	SBI_PMU_HW_INSTRUCTIONS			= 2,
-	SBI_PMU_HW_CACHE_REFERENCES		= 3,
-	SBI_PMU_HW_CACHE_MISSES			= 4,
-	SBI_PMU_HW_BRANCH_INSTRUCTIONS		= 5,
-	SBI_PMU_HW_BRANCH_MISSES		= 6,
-	SBI_PMU_HW_BUS_CYCLES			= 7,
-	SBI_PMU_HW_STALLED_CYCLES_FRONTEND	= 8,
-	SBI_PMU_HW_STALLED_CYCLES_BACKEND	= 9,
-	SBI_PMU_HW_REF_CPU_CYCLES		= 10,
-
-	SBI_PMU_HW_GENERAL_MAX,
-};
-
-/**
- * Generalized hardware cache events:
- *
- *       { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x
- *       { read, write, prefetch } x
- *       { accesses, misses }
- */
-enum sbi_pmu_hw_cache_id {
-	SBI_PMU_HW_CACHE_L1D		= 0,
-	SBI_PMU_HW_CACHE_L1I		= 1,
-	SBI_PMU_HW_CACHE_LL		= 2,
-	SBI_PMU_HW_CACHE_DTLB		= 3,
-	SBI_PMU_HW_CACHE_ITLB		= 4,
-	SBI_PMU_HW_CACHE_BPU		= 5,
-	SBI_PMU_HW_CACHE_NODE		= 6,
-
-	SBI_PMU_HW_CACHE_MAX,
-};
-
-enum sbi_pmu_hw_cache_op_id {
-	SBI_PMU_HW_CACHE_OP_READ	= 0,
-	SBI_PMU_HW_CACHE_OP_WRITE	= 1,
-	SBI_PMU_HW_CACHE_OP_PREFETCH	= 2,
-
-	SBI_PMU_HW_CACHE_OP_MAX,
-};
-
-enum sbi_pmu_hw_cache_op_result_id {
-	SBI_PMU_HW_CACHE_RESULT_ACCESS	= 0,
-	SBI_PMU_HW_CACHE_RESULT_MISS	= 1,
-
-	SBI_PMU_HW_CACHE_RESULT_MAX,
-};
-
-/**
- * Special "firmware" events provided by the OpenSBI, even if the hardware
- * does not support performance events. These events are encoded as a raw
- * event type in Linux kernel perf framework.
- */
-enum sbi_pmu_fw_event_code_id {
-	SBI_PMU_FW_MISALIGNED_LOAD	= 0,
-	SBI_PMU_FW_MISALIGNED_STORE	= 1,
-	SBI_PMU_FW_ACCESS_LOAD		= 2,
-	SBI_PMU_FW_ACCESS_STORE		= 3,
-	SBI_PMU_FW_ILLEGAL_INSN		= 4,
-	SBI_PMU_FW_SET_TIMER		= 5,
-	SBI_PMU_FW_IPI_SENT		= 6,
-	SBI_PMU_FW_IPI_RECVD		= 7,
-	SBI_PMU_FW_FENCE_I_SENT		= 8,
-	SBI_PMU_FW_FENCE_I_RECVD	= 9,
-	SBI_PMU_FW_SFENCE_VMA_SENT	= 10,
-	SBI_PMU_FW_SFENCE_VMA_RCVD	= 11,
-	SBI_PMU_FW_SFENCE_VMA_ASID_SENT	= 12,
-	SBI_PMU_FW_SFENCE_VMA_ASID_RCVD	= 13,
-
-	SBI_PMU_FW_HFENCE_GVMA_SENT	= 14,
-	SBI_PMU_FW_HFENCE_GVMA_RCVD	= 15,
-	SBI_PMU_FW_HFENCE_GVMA_VMID_SENT = 16,
-	SBI_PMU_FW_HFENCE_GVMA_VMID_RCVD = 17,
-
-	SBI_PMU_FW_HFENCE_VVMA_SENT	= 18,
-	SBI_PMU_FW_HFENCE_VVMA_RCVD	= 19,
-	SBI_PMU_FW_HFENCE_VVMA_ASID_SENT = 20,
-	SBI_PMU_FW_HFENCE_VVMA_ASID_RCVD = 21,
-	SBI_PMU_FW_MAX,
-};
-
-/** SBI PMU event idx type */
-enum sbi_pmu_event_type_id {
-	SBI_PMU_EVENT_TYPE_HW				= 0x0,
-	SBI_PMU_EVENT_TYPE_HW_CACHE			= 0x1,
-	SBI_PMU_EVENT_TYPE_HW_RAW			= 0x2,
-	SBI_PMU_EVENT_TYPE_FW				= 0xf,
-	SBI_PMU_EVENT_TYPE_MAX,
-};
-
-/** SBI PMU counter type */
-enum sbi_pmu_ctr_type {
-	SBI_PMU_CTR_TYPE_HW = 0,
-	SBI_PMU_CTR_TYPE_FW,
-};
-
-/* Helper macros to decode event idx */
-#define SBI_PMU_EVENT_IDX_OFFSET 20
-#define SBI_PMU_EVENT_IDX_MASK 0xFFFFF
-#define SBI_PMU_EVENT_IDX_CODE_MASK 0xFFFF
-#define SBI_PMU_EVENT_IDX_TYPE_MASK 0xF0000
-#define SBI_PMU_EVENT_RAW_IDX 0x20000
-
-#define SBI_PMU_EVENT_IDX_INVALID 0xFFFFFFFF
-
-#define SBI_PMU_EVENT_HW_CACHE_OPS_RESULT	0x1
-#define SBI_PMU_EVENT_HW_CACHE_OPS_ID_MASK	0x6
-#define SBI_PMU_EVENT_HW_CACHE_OPS_ID_OFFSET	1
-#define SBI_PMU_EVENT_HW_CACHE_ID_MASK		0xfff8
-#define SBI_PMU_EVENT_HW_CACHE_ID_OFFSET	3
-
-/* Flags defined for config matching function */
-#define SBI_PMU_CFG_FLAG_SKIP_MATCH	(1 << 0)
-#define SBI_PMU_CFG_FLAG_CLEAR_VALUE	(1 << 1)
-#define SBI_PMU_CFG_FLAG_AUTO_START	(1 << 2)
-#define SBI_PMU_CFG_FLAG_SET_VUINH	(1 << 3)
-#define SBI_PMU_CFG_FLAG_SET_VSINH	(1 << 4)
-#define SBI_PMU_CFG_FLAG_SET_UINH	(1 << 5)
-#define SBI_PMU_CFG_FLAG_SET_SINH	(1 << 6)
-#define SBI_PMU_CFG_FLAG_SET_MINH	(1 << 7)
-
-/* Flags defined for counter start function */
-#define SBI_PMU_START_FLAG_SET_INIT_VALUE (1 << 0)
-
-/* Flags defined for counter stop function */
-#define SBI_PMU_STOP_FLAG_RESET (1 << 0)
-
-/* SBI base specification related macros */
 #define SBI_SPEC_VERSION_MAJOR_OFFSET		24
 #define SBI_SPEC_VERSION_MAJOR_MASK		0x7f
 #define SBI_SPEC_VERSION_MINOR_MASK		0xffffff
@@ -247,10 +111,15 @@ enum sbi_pmu_ctr_type {
 #define SBI_ERR_DENIED				-4
 #define SBI_ERR_INVALID_ADDRESS			-5
 #define SBI_ERR_ALREADY_AVAILABLE		-6
-#define SBI_ERR_ALREADY_STARTED			-7
-#define SBI_ERR_ALREADY_STOPPED			-8

-#define SBI_LAST_ERR				SBI_ERR_ALREADY_STOPPED
+/* SBI function IDs for SUSP extension */
+#define SBI_EXT_SUSP_SUSPEND                   0x0
+
+#define SBI_SUSP_SLEEP_TYPE_SUSPEND            0x0
+#define SBI_SUSP_SLEEP_TYPE_LAST               SBI_SUSP_SLEEP_TYPE_SUSPEND
+#define SBI_SUSP_PLATFORM_SLEEP_START          0x80000000
+
+#define SBI_LAST_ERR				SBI_ERR_ALREADY_AVAILABLE

 /* clang-format on */

--- a/include/sbi/sbi_error.h
+++ b/include/sbi/sbi_error.h
@@ -21,8 +21,6 @@
 #define SBI_EDENIED		SBI_ERR_DENIED
 #define SBI_EINVALID_ADDR	SBI_ERR_INVALID_ADDRESS
 #define SBI_EALREADY		SBI_ERR_ALREADY_AVAILABLE
-#define SBI_EALREADY_STARTED	SBI_ERR_ALREADY_STARTED
-#define SBI_EALREADY_STOPPED	SBI_ERR_ALREADY_STOPPED

 #define SBI_ENODEV		-1000
 #define SBI_ENOSYS		-1001
--- a/include/sbi/sbi_fifo.h
+++ b/include/sbi/sbi_fifo.h
@@ -33,8 +33,8 @@ int sbi_fifo_dequeue(struct sbi_fifo *fifo, void *data);
 int sbi_fifo_enqueue(struct sbi_fifo *fifo, void *data);
 void sbi_fifo_init(struct sbi_fifo *fifo, void *queue_mem, u16 entries,
 		   u16 entry_size);
-int sbi_fifo_is_empty(struct sbi_fifo *fifo);
-int sbi_fifo_is_full(struct sbi_fifo *fifo);
+bool sbi_fifo_is_empty(struct sbi_fifo *fifo);
+bool sbi_fifo_is_full(struct sbi_fifo *fifo);
 int sbi_fifo_inplace_update(struct sbi_fifo *fifo, void *in,
 			    int (*fptr)(void *in, void *data));
 u16 sbi_fifo_avail(struct sbi_fifo *fifo);
--- a/include/sbi/sbi_hart.h
+++ b/include/sbi/sbi_hart.h
@@ -12,44 +12,17 @@

 #include <sbi/sbi_types.h>

-/** Possible privileged specification versions of a hart */
-enum sbi_hart_priv_versions {
-	/** Unknown privileged specification */
-	SBI_HART_PRIV_VER_UNKNOWN = 0,
-	/** Privileged specification v1.10 */
-	SBI_HART_PRIV_VER_1_10 = 1,
-	/** Privileged specification v1.11 */
-	SBI_HART_PRIV_VER_1_11 = 2,
-	/** Privileged specification v1.12 */
-	SBI_HART_PRIV_VER_1_12 = 3,
-};
+/** Possible feature flags of a hart */
+enum sbi_hart_features {
+	/** Hart has S-mode counter enable */
+	SBI_HART_HAS_SCOUNTEREN = (1 << 0),
+	/** Hart has M-mode counter enable */
+	SBI_HART_HAS_MCOUNTEREN = (1 << 1),
+	/** HART has timer csr implementation in hardware */
+	SBI_HART_HAS_TIME = (1 << 2),

-/** Possible ISA extensions of a hart */
-enum sbi_hart_extensions {
-	/** Hart has Sscofpmt extension */
-	SBI_HART_EXT_SSCOFPMF = 0,
-	/** HART has HW time CSR (extension name not available) */
-	SBI_HART_EXT_TIME,
-	/** HART has AIA M-mode CSRs */
-	SBI_HART_EXT_SMAIA,
-	/** HART has Smstateen CSR **/
-	SBI_HART_EXT_SMSTATEEN,
-	/** HART has Sstc extension */
-	SBI_HART_EXT_SSTC,
-
-	/** Maximum index of Hart extension */
-	SBI_HART_EXT_MAX,
-};
-
-struct sbi_hart_features {
-	bool detected;
-	int priv_version;
-	unsigned long extensions;
-	unsigned int pmp_count;
-	unsigned int pmp_addr_bits;
-	unsigned long pmp_gran;
-	unsigned int mhpm_count;
-	unsigned int mhpm_bits;
+	/** Last index of Hart features*/
+	SBI_HART_HAS_LAST_FEATURE = SBI_HART_HAS_TIME,
 };

 struct sbi_scratch;
@@ -69,18 +42,10 @@ void sbi_hart_delegation_dump(struct sbi_scratch *scratch,
 unsigned int sbi_hart_pmp_count(struct sbi_scratch *scratch);
 unsigned long sbi_hart_pmp_granularity(struct sbi_scratch *scratch);
 unsigned int sbi_hart_pmp_addrbits(struct sbi_scratch *scratch);
-unsigned int sbi_hart_mhpm_bits(struct sbi_scratch *scratch);
 int sbi_hart_pmp_configure(struct sbi_scratch *scratch);
-int sbi_hart_priv_version(struct sbi_scratch *scratch);
-void sbi_hart_get_priv_version_str(struct sbi_scratch *scratch,
-				   char *version_str, int nvstr);
-void sbi_hart_update_extension(struct sbi_scratch *scratch,
-			       enum sbi_hart_extensions ext,
-			       bool enable);
-bool sbi_hart_has_extension(struct sbi_scratch *scratch,
-			    enum sbi_hart_extensions ext);
-void sbi_hart_get_extensions_str(struct sbi_scratch *scratch,
-				 char *extension_str, int nestr);
+bool sbi_hart_has_feature(struct sbi_scratch *scratch, unsigned long feature);
+void sbi_hart_get_features_str(struct sbi_scratch *scratch,
+			       char *features_str, int nfstr);

 void __attribute__((noreturn)) sbi_hart_hang(void);

--- a/include/sbi/sbi_hfence.h
+++ b/include/sbi/sbi_hfence.h
@@ -12,14 +12,13 @@
 #define __SBI_FENCE_H__

 /** Invalidate Stage2 TLBs for given VMID and guest physical address */
-void __sbi_hfence_gvma_vmid_gpa(unsigned long gpa_divby_4,
-				unsigned long vmid);
+void __sbi_hfence_gvma_vmid_gpa(unsigned long gpa, unsigned long vmid);

 /** Invalidate Stage2 TLBs for given VMID */
 void __sbi_hfence_gvma_vmid(unsigned long vmid);

 /** Invalidate Stage2 TLBs for given guest physical address */
-void __sbi_hfence_gvma_gpa(unsigned long gpa_divby_4);
+void __sbi_hfence_gvma_gpa(unsigned long gpa);

 /** Invalidate all possible Stage2 TLBs */
 void __sbi_hfence_gvma_all(void);
--- a/include/sbi/sbi_hsm.h
+++ b/include/sbi/sbi_hsm.h
@@ -34,17 +34,9 @@ struct sbi_hsm_device {
 	 * the hart resumes normal execution.
 	 *
 	 * For successful non-retentive suspend, the hart will resume from
-	 * the warm boot entry point.
+	 * specified resume address
 	 */
-	int (*hart_suspend)(u32 suspend_type);
-
-	/**
-	 * Perform platform-specific actions to resume from a suspended state.
-	 *
-	 * This includes restoring any platform state that was lost during
-	 * non-retentive suspend.
-	 */
-	void (*hart_resume)(void);
+	int (*hart_suspend)(u32 suspend_type, ulong raddr);
 };

 struct sbi_domain;
@@ -65,9 +57,13 @@ void sbi_hsm_hart_resume_start(struct sbi_scratch *scratch);
 void sbi_hsm_hart_resume_finish(struct sbi_scratch *scratch);
 int sbi_hsm_hart_suspend(struct sbi_scratch *scratch, u32 suspend_type,
 			 ulong raddr, ulong rmode, ulong priv);
+int sbi_hsm_hart_change_state(struct sbi_scratch *scratch, long oldstate,
+				long newstate);
+int __sbi_hsm_hart_get_state(u32 hartid);
 int sbi_hsm_hart_get_state(const struct sbi_domain *dom, u32 hartid);
 int sbi_hsm_hart_interruptible_mask(const struct sbi_domain *dom,
 				    ulong hbase, ulong *out_hmask);
+void __sbi_hsm_suspend_non_ret_save(struct sbi_scratch *scratch);
 void sbi_hsm_prepare_next_jump(struct sbi_scratch *scratch, u32 hartid);

 #endif
--- a/include/sbi/sbi_ipi.h
+++ b/include/sbi/sbi_ipi.h
@@ -75,7 +75,7 @@ int sbi_ipi_send_halt(ulong hmask, ulong hbase);

 void sbi_ipi_process(void);

-int sbi_ipi_raw_send(u32 target_hart);
+void sbi_ipi_raw_send(u32 target_hart);

 const struct sbi_ipi_device *sbi_ipi_get_device(void);

--- a/include/sbi/sbi_irqchip.h
+++ b/include/sbi/sbi_irqchip.h
@@ -1,44 +0,0 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2022 Ventana Micro Systems Inc.
- *
- * Authors:
- *   Anup Patel <apatel@ventanamicro.com>
- */
-
-#ifndef __SBI_IRQCHIP_H__
-#define __SBI_IRQCHIP_H__
-
-#include <sbi/sbi_types.h>
-
-struct sbi_scratch;
-struct sbi_trap_regs;
-
-/**
- * Set external interrupt handling function
- *
- * This function is called by OpenSBI platform code to set a handler for
- * external interrupts
- *
- * @param fn function pointer for handling external irqs
- */
-void sbi_irqchip_set_irqfn(int (*fn)(struct sbi_trap_regs *regs));
-
-/**
- * Process external interrupts
- *
- * This function is called by sbi_trap_handler() to handle external
- * interrupts.
- *
- * @param regs pointer for trap registers
- */
-int sbi_irqchip_process(struct sbi_trap_regs *regs);
-
-/** Initialize interrupt controllers */
-int sbi_irqchip_init(struct sbi_scratch *scratch, bool cold_boot);
-
-/** Exit interrupt controllers */
-void sbi_irqchip_exit(struct sbi_scratch *scratch);
-
-#endif
--- a/include/sbi/sbi_list.h
+++ b/include/sbi/sbi_list.h
@@ -43,17 +43,6 @@ static inline void __sbi_list_add(struct sbi_dlist *new,
 	next->prev = new;
 }

-/**
- * Checks if the list is empty or not.
- * @param head List head
- *
- * Retruns TRUE if list is empty, FALSE otherwise.
- */
-static inline bool sbi_list_empty(struct sbi_dlist *head)
-{
-	return head->next == head;
-}
-
 /**
 * Adds the new node after the given head.
 * @param new New node that needs to be added to list.
--- a/include/sbi/sbi_platform.h
+++ b/include/sbi/sbi_platform.h
@@ -48,7 +48,6 @@
 struct sbi_domain_memregion;
 struct sbi_trap_info;
 struct sbi_trap_regs;
-struct sbi_hart_features;

 /** Possible feature flags of a platform */
 enum sbi_platform_features {
@@ -65,9 +64,6 @@ enum sbi_platform_features {

 /** Platform functions */
 struct sbi_platform_operations {
-	/* Platform nascent initialization */
-	int (*nascent_init)(void);
-
 	/** Platform early initialization */
 	int (*early_init)(bool cold_boot);
 	/** Platform final initialization */
@@ -90,18 +86,9 @@ struct sbi_platform_operations {
 	 */
 	int (*misa_get_xlen)(void);

-	/** Initialize (or populate) HART extensions for the platform */
-	int (*extensions_init)(struct sbi_hart_features *hfeatures);
-
 	/** Initialize (or populate) domains for the platform */
 	int (*domains_init)(void);

-	/** Initialize hw performance counters */
-	int (*pmu_init)(void);
-
-	/** Get platform specific mhpmevent value */
-	uint64_t (*pmu_xlate_to_mhpmevent)(uint32_t event_idx, uint64_t data);
-
 	/** Initialize the platform console */
 	int (*console_init)(void);

@@ -179,56 +166,6 @@ struct sbi_platform {
 	const u32 *hart_index2id;
 };

-/**
- * Prevent modification of struct sbi_platform from affecting
- * SBI_PLATFORM_xxx_OFFSET
- */
-_Static_assert(
-	offsetof(struct sbi_platform, opensbi_version)
-		== SBI_PLATFORM_OPENSBI_VERSION_OFFSET,
-	"struct sbi_platform definition has changed, please redefine "
-	"SBI_PLATFORM_OPENSBI_VERSION_OFFSET");
-_Static_assert(
-	offsetof(struct sbi_platform, platform_version)
-		== SBI_PLATFORM_VERSION_OFFSET,
-	"struct sbi_platform definition has changed, please redefine "
-	"SBI_PLATFORM_VERSION_OFFSET");
-_Static_assert(
-	offsetof(struct sbi_platform, name)
-		== SBI_PLATFORM_NAME_OFFSET,
-	"struct sbi_platform definition has changed, please redefine "
-	"SBI_PLATFORM_NAME_OFFSET");
-_Static_assert(
-	offsetof(struct sbi_platform, features)
-		== SBI_PLATFORM_FEATURES_OFFSET,
-	"struct sbi_platform definition has changed, please redefine "
-	"SBI_PLATFORM_FEATURES_OFFSET");
-_Static_assert(
-	offsetof(struct sbi_platform, hart_count)
-		== SBI_PLATFORM_HART_COUNT_OFFSET,
-	"struct sbi_platform definition has changed, please redefine "
-	"SBI_PLATFORM_HART_COUNT_OFFSET");
-_Static_assert(
-	offsetof(struct sbi_platform, hart_stack_size)
-		== SBI_PLATFORM_HART_STACK_SIZE_OFFSET,
-	"struct sbi_platform definition has changed, please redefine "
-	"SBI_PLATFORM_HART_STACK_SIZE_OFFSET");
-_Static_assert(
-	offsetof(struct sbi_platform, platform_ops_addr)
-		== SBI_PLATFORM_OPS_OFFSET,
-	"struct sbi_platform definition has changed, please redefine "
-	"SBI_PLATFORM_OPS_OFFSET");
-_Static_assert(
-	offsetof(struct sbi_platform, firmware_context)
-		== SBI_PLATFORM_FIRMWARE_CONTEXT_OFFSET,
-	"struct sbi_platform definition has changed, please redefine "
-	"SBI_PLATFORM_FIRMWARE_CONTEXT_OFFSET");
-_Static_assert(
-	offsetof(struct sbi_platform, hart_index2id)
-		== SBI_PLATFORM_HART_INDEX2ID_OFFSET,
-	"struct sbi_platform definition has changed, please redefine "
-	"SBI_PLATFORM_HART_INDEX2ID_OFFSET");
-
 /** Get pointer to sbi_platform for sbi_scratch pointer */
 #define sbi_platform_ptr(__s) \
 	((const struct sbi_platform *)((__s)->platform_addr))
@@ -356,23 +293,6 @@ static inline bool sbi_platform_hart_invalid(const struct sbi_platform *plat,
 	return FALSE;
 }

-/**
- * Nascent (very early) initialization for current HART
- *
- * NOTE: This function can be used to do very early initialization of
- * platform specific per-HART CSRs and devices.
- *
- * @param plat pointer to struct sbi_platform
- *
- * @return 0 on success and negative error code on failure
- */
-static inline int sbi_platform_nascent_init(const struct sbi_platform *plat)
-{
-	if (plat && sbi_platform_ops(plat)->nascent_init)
-		return sbi_platform_ops(plat)->nascent_init();
-	return 0;
-}
-
 /**
 * Early initialization for current HART
 *
@@ -457,22 +377,6 @@ static inline int sbi_platform_misa_xlen(const struct sbi_platform *plat)
 	return -1;
 }

-/**
- * Initialize (or populate) HART extensions for the platform
- *
- * @param plat pointer to struct sbi_platform
- *
- * @return 0 on success and negative error code on failure
- */
-static inline int sbi_platform_extensions_init(
-					const struct sbi_platform *plat,
-					struct sbi_hart_features *hfeatures)
-{
-	if (plat && sbi_platform_ops(plat)->extensions_init)
-		return sbi_platform_ops(plat)->extensions_init(hfeatures);
-	return 0;
-}
-
 /**
 * Initialize (or populate) domains for the platform
 *
@@ -487,39 +391,6 @@ static inline int sbi_platform_domains_init(const struct sbi_platform *plat)
 	return 0;
 }

-/**
- * Setup hw PMU events for the platform
- *
- * @param plat pointer to struct sbi_platform
- *
- * @return 0 on success and negative error code on failure
- */
-static inline int sbi_platform_pmu_init(const struct sbi_platform *plat)
-{
-	if (plat && sbi_platform_ops(plat)->pmu_init)
-		return sbi_platform_ops(plat)->pmu_init();
-	return 0;
-}
-
-/**
- * Get the value to be written in mhpmeventx for event_idx
- *
- * @param plat pointer to struct sbi_platform
- * @param event_idx ID of the PMU event
- * @param data Additional configuration data passed from supervisor software
- *
- * @return expected value by the platform or 0 if platform doesn't know about
- * the event
- */
-static inline uint64_t sbi_platform_pmu_xlate_to_mhpmevent(const struct sbi_platform *plat,
-						      uint32_t event_idx, uint64_t data)
-{
-	if (plat && sbi_platform_ops(plat)->pmu_xlate_to_mhpmevent)
-		return sbi_platform_ops(plat)->pmu_xlate_to_mhpmevent(event_idx,
-								      data);
-	return 0;
-}
-
 /**
 * Initialize the platform console
 *
--- a/include/sbi/sbi_pmu.h
+++ b/include/sbi/sbi_pmu.h
@@ -1,135 +0,0 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2021 Western Digital Corporation or its affiliates.
- *
- * Authors:
- *   Atish Patra <atish.patra@wdc.com>
- */
-
-#ifndef __SBI_PMU_H__
-#define __SBI_PMU_H__
-
-#include <sbi/sbi_types.h>
-
-struct sbi_scratch;
-
-/* Event related macros */
-/* Maximum number of hardware events that can mapped by OpenSBI */
-#define SBI_PMU_HW_EVENT_MAX 256
-
-/* Counter related macros */
-#define SBI_PMU_FW_CTR_MAX 16
-#define SBI_PMU_HW_CTR_MAX 32
-#define SBI_PMU_CTR_MAX	   (SBI_PMU_HW_CTR_MAX + SBI_PMU_FW_CTR_MAX)
-#define SBI_PMU_FIXED_CTR_MASK 0x07
-
-struct sbi_pmu_device {
-	/** Name of the PMU platform device */
-	char name[32];
-
-	/**
-	 * Validate event code of custom firmware event
-	 * Note: SBI_PMU_FW_MAX <= event_idx_code
-	 */
-	int (*fw_event_validate_code)(uint32_t event_idx_code);
-
-	/**
-	 * Match custom firmware counter with custom firmware event
-	 * Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX
-	 */
-	bool (*fw_counter_match_code)(uint32_t counter_index,
-				      uint32_t event_idx_code);
-
-	/**
-	 * Read value of custom firmware counter
-	 * Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX
-	 */
-	uint64_t (*fw_counter_read_value)(uint32_t counter_index);
-
-	/**
-	 * Start custom firmware counter
-	 * Note: SBI_PMU_FW_MAX <= event_idx_code
-	 * Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX
-	 */
-	int (*fw_counter_start)(uint32_t counter_index,
-				uint32_t event_idx_code,
-				uint64_t init_val, bool init_val_update);
-
-	/**
-	 * Stop custom firmware counter
-	 * Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX
-	 */
-	int (*fw_counter_stop)(uint32_t counter_index);
-
-	/**
-	 * Custom enable irq for hardware counter
-	 * Note: 0 <= counter_index < SBI_PMU_HW_CTR_MAX
-	 */
-	void (*hw_counter_enable_irq)(uint32_t counter_index);
-
-	/**
-	 * Custom disable irq for hardware counter
-	 * Note: 0 <= counter_index < SBI_PMU_HW_CTR_MAX
-	 */
-	void (*hw_counter_disable_irq)(uint32_t counter_index);
-
-	/**
-	 * Custom function returning the machine-specific irq-bit.
-	 */
-	int (*hw_counter_irq_bit)(void);
-};
-
-/** Get the PMU platform device */
-const struct sbi_pmu_device *sbi_pmu_get_device(void);
-
-/** Set the PMU platform device */
-void sbi_pmu_set_device(const struct sbi_pmu_device *dev);
-
-/** Initialize PMU */
-int sbi_pmu_init(struct sbi_scratch *scratch, bool cold_boot);
-
-/** Reset PMU during hart exit */
-void sbi_pmu_exit(struct sbi_scratch *scratch);
-
-/** Return the pmu irq bit depending on extension existence */
-int sbi_pmu_irq_bit(void);
-
-/**
- * Add the hardware event to counter mapping information. This should be called
- * from the platform code to update the mapping table.
- * @param eidx_start Start of the event idx range for supported counters
- * @param eidx_end   End of the event idx range for supported counters
- * @param cmap       A bitmap representing counters supporting the event range
- * @return 0 on success, error otherwise.
- */
-int sbi_pmu_add_hw_event_counter_map(u32 eidx_start, u32 eidx_end, u32 cmap);
-
-/**
- * Add the raw hardware event selector and supported counter information. This
- * should be called from the platform code to update the mapping table.
- * @param info  a pointer to the hardware event info
- * @return 0 on success, error otherwise.
- */
-
-int sbi_pmu_add_raw_event_counter_map(uint64_t select, uint64_t select_mask, u32 cmap);
-
-int sbi_pmu_ctr_fw_read(uint32_t cidx, uint64_t *cval);
-
-int sbi_pmu_ctr_stop(unsigned long cidx_base, unsigned long cidx_mask,
-		     unsigned long flag);
-
-int sbi_pmu_ctr_start(unsigned long cidx_base, unsigned long cidx_mask,
-		      unsigned long flags, uint64_t ival);
-
-int sbi_pmu_ctr_get_info(uint32_t cidx, unsigned long *ctr_info);
-
-unsigned long sbi_pmu_num_ctr(void);
-
-int sbi_pmu_ctr_cfg_match(unsigned long cidx_base, unsigned long cidx_mask,
-			  unsigned long flags, unsigned long event_idx,
-			  uint64_t event_data);
-
-int sbi_pmu_ctr_incr_fw(enum sbi_pmu_fw_event_code_id fw_id);
-
-#endif
--- a/include/sbi/sbi_scratch.h
+++ b/include/sbi/sbi_scratch.h
@@ -57,7 +57,7 @@ struct sbi_scratch {
 	unsigned long next_arg1;
 	/** Address of next booting stage for this HART */
 	unsigned long next_addr;
-	/** Privilege mode of next booting stage for this HART */
+	/** Priviledge mode of next booting stage for this HART */
 	unsigned long next_mode;
 	/** Warm boot entry point address for this HART */
 	unsigned long warmboot_addr;
@@ -73,66 +73,6 @@ struct sbi_scratch {
 	unsigned long options;
 };

-/**
- * Prevent modification of struct sbi_scratch from affecting
- * SBI_SCRATCH_xxx_OFFSET
- */
-_Static_assert(
-	offsetof(struct sbi_scratch, fw_start)
-		== SBI_SCRATCH_FW_START_OFFSET,
-	"struct sbi_scratch definition has changed, please redefine "
-	"SBI_SCRATCH_FW_START_OFFSET");
-_Static_assert(
-	offsetof(struct sbi_scratch, fw_size)
-		== SBI_SCRATCH_FW_SIZE_OFFSET,
-	"struct sbi_scratch definition has changed, please redefine "
-	"SBI_SCRATCH_FW_SIZE_OFFSET");
-_Static_assert(
-	offsetof(struct sbi_scratch, next_arg1)
-		== SBI_SCRATCH_NEXT_ARG1_OFFSET,
-	"struct sbi_scratch definition has changed, please redefine "
-	"SBI_SCRATCH_NEXT_ARG1_OFFSET");
-_Static_assert(
-	offsetof(struct sbi_scratch, next_addr)
-		== SBI_SCRATCH_NEXT_ADDR_OFFSET,
-	"struct sbi_scratch definition has changed, please redefine "
-	"SBI_SCRATCH_NEXT_ADDR_OFFSET");
-_Static_assert(
-	offsetof(struct sbi_scratch, next_mode)
-		== SBI_SCRATCH_NEXT_MODE_OFFSET,
-	"struct sbi_scratch definition has changed, please redefine "
-	"SBI_SCRATCH_NEXT_MODE_OFFSET");
-_Static_assert(
-	offsetof(struct sbi_scratch, warmboot_addr)
-		== SBI_SCRATCH_WARMBOOT_ADDR_OFFSET,
-	"struct sbi_scratch definition has changed, please redefine "
-	"SBI_SCRATCH_WARMBOOT_ADDR_OFFSET");
-_Static_assert(
-	offsetof(struct sbi_scratch, platform_addr)
-		== SBI_SCRATCH_PLATFORM_ADDR_OFFSET,
-	"struct sbi_scratch definition has changed, please redefine "
-	"SBI_SCRATCH_PLATFORM_ADDR_OFFSET");
-_Static_assert(
-	offsetof(struct sbi_scratch, hartid_to_scratch)
-		== SBI_SCRATCH_HARTID_TO_SCRATCH_OFFSET,
-	"struct sbi_scratch definition has changed, please redefine "
-	"SBI_SCRATCH_HARTID_TO_SCRATCH_OFFSET");
-_Static_assert(
-	offsetof(struct sbi_scratch, trap_exit)
-		== SBI_SCRATCH_TRAP_EXIT_OFFSET,
-	"struct sbi_scratch definition has changed, please redefine "
-	"SBI_SCRATCH_TRAP_EXIT_OFFSET");
-_Static_assert(
-	offsetof(struct sbi_scratch, tmp0)
-		== SBI_SCRATCH_TMP0_OFFSET,
-	"struct sbi_scratch definition has changed, please redefine "
-	"SBI_SCRATCH_TMP0_OFFSET");
-_Static_assert(
-	offsetof(struct sbi_scratch, options)
-		== SBI_SCRATCH_OPTIONS_OFFSET,
-	"struct sbi_scratch definition has changed, please redefine "
-	"SBI_SCRATCH_OPTIONS_OFFSET");
-
 /** Possible options for OpenSBI library */
 enum sbi_scratch_options {
 	/** Disable prints during boot */
@@ -158,17 +98,17 @@ int sbi_scratch_init(struct sbi_scratch *scratch);
 * @return zero on failure and non-zero (>= SBI_SCRATCH_EXTRA_SPACE_OFFSET)
 * on success
 */
-unsigned long sbi_scratch_alloc_offset(unsigned long size);
+unsigned long sbi_scratch_alloc_offset(unsigned long size, const char *owner);

 /** Free-up extra space in sbi_scratch */
 void sbi_scratch_free_offset(unsigned long offset);

 /** Get pointer from offset in sbi_scratch */
-#define sbi_scratch_offset_ptr(scratch, offset)	(void *)((char *)(scratch) + (offset))
+#define sbi_scratch_offset_ptr(scratch, offset)	((void *)scratch + (offset))

 /** Get pointer from offset in sbi_scratch for current HART */
 #define sbi_scratch_thishart_offset_ptr(offset)	\
-	(void *)((char *)sbi_scratch_thishart_ptr() + (offset))
+	((void *)sbi_scratch_thishart_ptr() + (offset))

 /** HART id to scratch table */
 extern struct sbi_scratch *hartid_to_scratch_table[];
--- a/include/sbi/sbi_system.h
+++ b/include/sbi/sbi_system.h
@@ -11,7 +11,6 @@
 #define __SBI_SYSTEM_H__

 #include <sbi/sbi_types.h>
-#include <sbi/sbi_list.h>

 /** System reset hardware device */
 struct sbi_system_reset_device {
@@ -23,24 +22,40 @@ struct sbi_system_reset_device {

 	/** Reset the system */
 	void (*system_reset)(u32 reset_type, u32 reset_reason);
-
-	/** List */
-	struct sbi_dlist node;
 };

-static inline struct sbi_system_reset_device *to_system_reset_device(
-						struct sbi_dlist *node)
-{
-	return container_of(node, struct sbi_system_reset_device, node);
-}
+const struct sbi_system_reset_device *sbi_system_reset_get_device(void);

-const struct sbi_system_reset_device *sbi_system_reset_get_device(
-					u32 reset_type, u32 reset_reason);
-
-void sbi_system_reset_add_device(struct sbi_system_reset_device *dev);
+void sbi_system_reset_set_device(const struct sbi_system_reset_device *dev);

 bool sbi_system_reset_supported(u32 reset_type, u32 reset_reason);

 void __noreturn sbi_system_reset(u32 reset_type, u32 reset_reason);

+/** System suspend device */
+struct sbi_system_suspend_device {
+	/** Name of the system suspend device */
+	char name[32];
+
+	/* Check whether sleep type is supported by the device */
+	int (*system_suspend_check)(u32 sleep_type);
+
+	/**
+	 * Suspend the system
+	 *
+	 * @sleep_type: The sleep type identifier passed to the SBI call.
+	 * @mmode_resume_addr:
+	 *     This is the same as sbi_scratch.warmboot_addr. Some platforms
+	 *     may not be able to return from system_suspend(), so they will
+	 *     jump directly to this address instead. Platforms which can
+	 *     return from system_suspend() may ignore this parameter.
+	 */
+	int (*system_suspend)(u32 sleep_type, unsigned long mmode_resume_addr);
+};
+
+const struct sbi_system_suspend_device *sbi_system_suspend_get_device(void);
+void sbi_system_suspend_set_device(struct sbi_system_suspend_device *dev);
+bool sbi_system_suspend_supported(u32 sleep_type);
+int sbi_system_suspend(u32 sleep_type, ulong resume_addr, ulong opaque);
+
 #endif
--- a/include/sbi/sbi_timer.h
+++ b/include/sbi/sbi_timer.h
@@ -17,9 +17,6 @@ struct sbi_timer_device {
 	/** Name of the timer operations */
 	char name[32];

-	/** Frequency of timer in HZ */
-	unsigned long timer_freq;
-
 	/** Get free-running timer value */
 	u64 (*timer_value)(void);

@@ -32,40 +29,6 @@ struct sbi_timer_device {

 struct sbi_scratch;

-/** Generic delay loop of desired granularity */
-void sbi_timer_delay_loop(ulong units, u64 unit_freq,
-			  void (*delay_fn)(void *), void *opaque);
-
-/** Provide delay in terms of milliseconds */
-static inline void sbi_timer_mdelay(ulong msecs)
-{
-	sbi_timer_delay_loop(msecs, 1000, NULL, NULL);
-}
-
-/** Provide delay in terms of microseconds */
-static inline void sbi_timer_udelay(ulong usecs)
-{
-	sbi_timer_delay_loop(usecs, 1000000, NULL, NULL);
-}
-
-/**
- * A blocking function that will wait until @p predicate returns true or
- * @p timeout_ms milliseconds elapsed. @p arg will be passed as argument to
- * @p predicate function.
- *
- * @param predicate Pointer to a function that returns true if certain
- * condition is met. It shouldn't block the code execution.
- * @param arg Argument to pass to @p predicate.
- * @param timeout_ms Timeout value in milliseconds. The function will return
- * false if @p timeout_ms time period elapsed but still @p predicate doesn't
- * return true.
- *
- * @return true if @p predicate returns true within @p timeout_ms, false
- * otherwise.
- */
-bool sbi_timer_waitms_until(bool (*predicate)(void *), void *arg,
-			    uint64_t timeout_ms);
-
 /** Get timer value for current HART */
 u64 sbi_timer_value(void);

--- a/include/sbi/sbi_trap.h
+++ b/include/sbi/sbi_trap.h
@@ -10,8 +10,6 @@
 #ifndef __SBI_TRAP_H__
 #define __SBI_TRAP_H__

-#include <sbi/riscv_encoding.h>
-
 /* clang-format off */

 /** Index of zero member in sbi_trap_regs */
@@ -97,10 +95,8 @@
 #define SBI_TRAP_INFO_tval2			3
 /** Index of tinst member in sbi_trap_info */
 #define SBI_TRAP_INFO_tinst			4
-/** Index of gva member in sbi_trap_info */
-#define SBI_TRAP_INFO_gva			5
 /** Last member index in sbi_trap_info */
-#define SBI_TRAP_INFO_last			6
+#define SBI_TRAP_INFO_last			5

 /* clang-format on */

@@ -204,26 +200,8 @@ struct sbi_trap_info {
 	unsigned long tval2;
 	/** tinst Trap instruction */
 	unsigned long tinst;
-	/** gva Guest virtual address in tval flag */
-	unsigned long gva;
 };

-static inline unsigned long sbi_regs_gva(const struct sbi_trap_regs *regs)
-{
-	/*
-	 * If the hypervisor extension is not implemented, mstatus[h].GVA is a
-	 * WPRI field, which is guaranteed to read as zero. In addition, in this
-	 * case we don't read mstatush and instead pretend it is zero, which
-	 * handles privileged spec version < 1.12.
-	 */
-
-#if __riscv_xlen == 32
-	return (regs->mstatusH & MSTATUSH_GVA) ? 1 : 0;
-#else
-	return (regs->mstatus & MSTATUS_GVA) ? 1 : 0;
-#endif
-}
-
 int sbi_trap_redirect(struct sbi_trap_regs *regs,
 		      struct sbi_trap_info *trap);

--- a/include/sbi/sbi_types.h
+++ b/include/sbi/sbi_types.h
@@ -68,14 +68,8 @@ typedef unsigned long		physical_size_t;
 #define likely(x) __builtin_expect((x), 1)
 #define unlikely(x) __builtin_expect((x), 0)

-#ifndef __has_builtin
-#define __has_builtin(...) 0
-#endif
-
 #undef offsetof
-#if __has_builtin(__builtin_offsetof)
-#define offsetof(TYPE, MEMBER) __builtin_offsetof(TYPE,MEMBER)
-#elif defined(__compiler_offsetof)
+#ifdef __compiler_offsetof
 #define offsetof(TYPE, MEMBER) __compiler_offsetof(TYPE,MEMBER)
 #else
 #define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
--- a/include/sbi/sbi_version.h
+++ b/include/sbi/sbi_version.h
@@ -10,8 +10,8 @@
 #ifndef __SBI_VERSION_H__
 #define __SBI_VERSION_H__

-#define OPENSBI_VERSION_MAJOR 1
-#define OPENSBI_VERSION_MINOR 2
+#define OPENSBI_VERSION_MAJOR 0
+#define OPENSBI_VERSION_MINOR 9

 /**
 * OpenSBI 32-bit version with:
--- a/include/sbi_utils/fdt/fdt_domain.h
+++ b/include/sbi_utils/fdt/fdt_domain.h
@@ -13,8 +13,6 @@

 #include <sbi/sbi_types.h>

-#ifdef CONFIG_FDT_DOMAIN
-
 struct sbi_domain;

 /**
@@ -72,11 +70,4 @@ void fdt_domain_fixup(void *fdt);
 */
 int fdt_domains_populate(void *fdt);

-#else
-
-static inline void fdt_domain_fixup(void *fdt) { }
-static inline int fdt_domains_populate(void *fdt) { return 0; }
-
-#endif
-
 #endif /* __FDT_DOMAIN_H__ */
--- a/include/sbi_utils/fdt/fdt_fixup.h
+++ b/include/sbi_utils/fdt/fdt_fixup.h
@@ -21,30 +21,6 @@
 */
 void fdt_cpu_fixup(void *fdt);

-/**
- * Fix up the APLIC nodes in the device tree
- *
- * This routine disables APLIC nodes which are not accessible to the next
- * booting stage based on currently assigned domain.
- *
- * It is recommended that platform codes call this helper in their final_init()
- *
- * @param fdt: device tree blob
- */
-void fdt_aplic_fixup(void *fdt);
-
-/**
- * Fix up the IMSIC nodes in the device tree
- *
- * This routine disables IMSIC nodes which are not accessible to the next
- * booting stage based on currently assigned domain.
- *
- * It is recommended that platform codes call this helper in their final_init()
- *
- * @param fdt: device tree blob
- */
-void fdt_imsic_fixup(void *fdt);
-
 /**
 * Fix up the PLIC node in the device tree
 *
@@ -88,9 +64,8 @@ int fdt_reserved_memory_nomap_fixup(void *fdt);
 * General device tree fix-up
 *
 * This routine do all required device tree fix-ups for a typical platform.
- * It fixes up the PLIC node, IMSIC nodes, APLIC nodes, and the reserved
- * memory node in the device tree by calling the corresponding helper
- * routines to accomplish the task.
+ * It fixes up the PLIC node and the reserved memory node in the device tree
+ * by calling the corresponding helper routines to accomplish the task.
 *
 * It is recommended that platform codes call this helper in their final_init()
 *
--- a/include/sbi_utils/fdt/fdt_helper.h
+++ b/include/sbi_utils/fdt/fdt_helper.h
@@ -11,18 +11,10 @@
 #define __FDT_HELPER_H__

 #include <sbi/sbi_types.h>
-#include <sbi/sbi_scratch.h>

 struct fdt_match {
 	const char *compatible;
-	const void *data;
-};
-
-#define FDT_MAX_PHANDLE_ARGS 16
-struct fdt_phandle_args {
-	int node_offset;
-	int args_count;
-	u32 args[FDT_MAX_PHANDLE_ARGS];
+	void *data;
 };

 struct platform_uart_data {
@@ -31,7 +23,6 @@ struct platform_uart_data {
 	unsigned long baud;
 	unsigned long reg_shift;
 	unsigned long reg_io_width;
-	unsigned long reg_offset;
 };

 const struct fdt_match *fdt_match_node(void *fdt, int nodeoff,
@@ -41,26 +32,12 @@ int fdt_find_match(void *fdt, int startoff,
 		   const struct fdt_match *match_table,
 		   const struct fdt_match **out_match);

-int fdt_parse_phandle_with_args(void *fdt, int nodeoff,
-				const char *prop, const char *cells_prop,
-				int index, struct fdt_phandle_args *out_args);
-
-int fdt_get_node_addr_size(void *fdt, int node, int index,
-			   uint64_t *addr, uint64_t *size);
-
-bool fdt_node_is_enabled(void *fdt, int nodeoff);
+int fdt_get_node_addr_size(void *fdt, int node, unsigned long *addr,
+			   unsigned long *size);

 int fdt_parse_hart_id(void *fdt, int cpu_offset, u32 *hartid);

-int fdt_parse_max_enabled_hart_id(void *fdt, u32 *max_hartid);
-
-int fdt_parse_timebase_frequency(void *fdt, unsigned long *freq);
-
-int fdt_parse_gaisler_uart_node(void *fdt, int nodeoffset,
-				struct platform_uart_data *uart);
-
-int fdt_parse_renesas_scif_node(void *fdt, int nodeoffset,
-				struct platform_uart_data *uart);
+int fdt_parse_max_hart_id(void *fdt, u32 *max_hartid);

 int fdt_parse_shakti_uart_node(void *fdt, int nodeoffset,
 			       struct platform_uart_data *uart);
@@ -68,48 +45,24 @@ int fdt_parse_shakti_uart_node(void *fdt, int nodeoffset,
 int fdt_parse_sifive_uart_node(void *fdt, int nodeoffset,
 			       struct platform_uart_data *uart);

-int fdt_parse_uart_node(void *fdt, int nodeoffset,
-			struct platform_uart_data *uart);
+int fdt_parse_uart8250_node(void *fdt, int nodeoffset,
+			    struct platform_uart_data *uart);

 int fdt_parse_uart8250(void *fdt, struct platform_uart_data *uart,
 		       const char *compatible);

-int fdt_parse_xlnx_uartlite_node(void *fdt, int nodeoffset,
-			       struct platform_uart_data *uart);
-
-struct aplic_data;
-
-int fdt_parse_aplic_node(void *fdt, int nodeoff, struct aplic_data *aplic);
-
-struct imsic_data;
-
-bool fdt_check_imsic_mlevel(void *fdt);
-
-int fdt_parse_imsic_node(void *fdt, int nodeoff, struct imsic_data *imsic);
-
 struct plic_data;

 int fdt_parse_plic_node(void *fdt, int nodeoffset, struct plic_data *plic);

 int fdt_parse_plic(void *fdt, struct plic_data *plic, const char *compat);

-int fdt_parse_aclint_node(void *fdt, int nodeoffset, bool for_timer,
-			  unsigned long *out_addr1, unsigned long *out_size1,
-			  unsigned long *out_addr2, unsigned long *out_size2,
-			  u32 *out_first_hartid, u32 *out_hart_count);
+struct clint_data;

-int fdt_parse_plmt_node(void *fdt, int nodeoffset, unsigned long *plmt_base,
-			  unsigned long *plmt_size, u32 *hart_count);
+int fdt_parse_clint_node(void *fdt, int nodeoffset, bool for_timer,
+			 struct clint_data *clint);

-int fdt_parse_plicsw_node(void *fdt, int nodeoffset, unsigned long *plicsw_base,
-			  unsigned long *size, u32 *hart_count);
-
-int fdt_parse_compat_addr(void *fdt, uint64_t *addr,
+int fdt_parse_compat_addr(void *fdt, unsigned long *addr,
 			  const char *compatible);

-static inline void *fdt_get_address(void)
-{
-	return sbi_scratch_thishart_arg1_ptr();
-}
-
 #endif /* __FDT_HELPER_H__ */
--- a/include/sbi_utils/fdt/fdt_pmu.h
+++ b/include/sbi_utils/fdt/fdt_pmu.h
@@ -1,56 +0,0 @@
-// SPDX-License-Identifier: BSD-2-Clause
-/*
- * fdt_pmu.c - Flat Device Tree PMU helper routines
- *
- * Copyright (c) 2021 Western Digital Corporation or its affiliates.
- *
- * Authors:
- *   Atish Patra <atish.patra@wdc.com>
- */
-
-#ifndef __FDT_PMU_H__
-#define __FDT_PMU_H__
-
-#include <sbi/sbi_types.h>
-
-#ifdef CONFIG_FDT_PMU
-
-/**
- * Fix up the PMU node in the device tree
- *
- * This routine:
- * 1. Disables opensbi specific properties from the DT
- *
- * It is recommended that platform support call this function in
- * their final_init() platform operation.
- *
- * @param fdt device tree blob
- */
-void fdt_pmu_fixup(void *fdt);
-
-/**
- * Setup PMU data from device tree
- *
- * @param fdt device tree blob
- *
- * @return 0 on success and negative error code on failure
- */
-int fdt_pmu_setup(void *fdt);
-
-/**
- * Get the mhpmevent select value read from DT for a given event
- * @param event_idx Event ID of the given event
- *
- * @return The select value read from DT or 0 if given index was not found
- */
-uint64_t fdt_pmu_get_select_value(uint32_t event_idx);
-
-#else
-
-static inline void fdt_pmu_fixup(void *fdt) { }
-static inline int fdt_pmu_setup(void *fdt) { return 0; }
-static inline uint64_t fdt_pmu_get_select_value(uint32_t event_idx) { return 0; }
-
-#endif
-
-#endif
--- a/include/sbi_utils/gpio/fdt_gpio.h
+++ b/include/sbi_utils/gpio/fdt_gpio.h
@@ -1,36 +0,0 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2021 Western Digital Corporation or its affiliates.
- *
- * Authors:
- *   Anup Patel <anup.patel@wdc.com>
- */
-
-#ifndef __FDT_GPIO_H__
-#define __FDT_GPIO_H__
-
-#include <sbi_utils/gpio/gpio.h>
-
-struct fdt_phandle_args;
-
-/** FDT based GPIO driver */
-struct fdt_gpio {
-	const struct fdt_match *match_table;
-	int (*xlate)(struct gpio_chip *chip,
-		     const struct fdt_phandle_args *pargs,
-		     struct gpio_pin *out_pin);
-	int (*init)(void *fdt, int nodeoff, u32 phandle,
-		    const struct fdt_match *match);
-};
-
-/** Get a GPIO pin using "gpios" DT property of client DT node */
-int fdt_gpio_pin_get(void *fdt, int nodeoff, int index,
-		     struct gpio_pin *out_pin);
-
-/** Simple xlate function to convert two GPIO FDT cells into GPIO pin */
-int fdt_gpio_simple_xlate(struct gpio_chip *chip,
-			  const struct fdt_phandle_args *pargs,
-			  struct gpio_pin *out_pin);
-
-#endif
--- a/include/sbi_utils/gpio/gpio.h
+++ b/include/sbi_utils/gpio/gpio.h
@@ -1,107 +0,0 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2021 Western Digital Corporation or its affiliates.
- *
- * Authors:
- *   Anup Patel <anup.patel@wdc.com>
- */
-
-#ifndef __GPIO_H__
-#define __GPIO_H__
-
-#include <sbi/sbi_types.h>
-#include <sbi/sbi_list.h>
-
-#define GPIO_LINE_DIRECTION_IN	1
-#define GPIO_LINE_DIRECTION_OUT	0
-
-/** Representation of a GPIO pin */
-struct gpio_pin {
-	/** Pointer to the GPIO chip */
-	struct gpio_chip *chip;
-	/** Identification of GPIO pin within GPIO chip */
-	unsigned int offset;
-	/**
-	 * Additional configuration flags of the GPIO pin desired
-	 * by GPIO clients.
-	 *
-	 * NOTE: GPIO chip can have custom configuration flags.
-	 */
-	unsigned int flags;
-#define GPIO_FLAG_ACTIVE_LOW	0x1
-#define GPIO_FLAG_SINGLE_ENDED	0x2
-#define GPIO_FLAG_OPEN_DRAIN	0x4
-#define GPIO_FLAG_TRANSITORY	0x8
-#define GPIO_FLAG_PULL_UP	0x10
-#define GPIO_FLAG_PULL_DOWN	0x20
-};
-
-/** Representation of a GPIO chip */
-struct gpio_chip {
-	/** Pointer to GPIO driver owning this GPIO chip */
-	void *driver;
-	/** Uniquie ID of the GPIO chip assigned by the driver */
-	unsigned int id;
-	/** Number of GPIOs supported by the GPIO chip */
-	unsigned int ngpio;
-	/**
-	 * Get current direction of GPIO pin
-	 *
-	 * @return 0=output, 1=input, or negative error
-	 */
-	int (*get_direction)(struct gpio_pin *gp);
-	/**
-	 * Set input direction of GPIO pin
-	 *
-	 * @return 0 on success and negative error code on failure
-	 */
-	int (*direction_input)(struct gpio_pin *gp);
-	/**
-	 * Set output direction of GPIO pin with given output value
-	 *
-	 * @return 0 on success and negative error code on failure
-	 */
-	int (*direction_output)(struct gpio_pin *gp, int value);
-	/**
-	 * Get current value of GPIO pin
-	 *
-	 * @return 0=low, 1=high, or negative error
-	 */
-	int (*get)(struct gpio_pin *gp);
-	/** Set output value for GPIO pin */
-	void (*set)(struct gpio_pin *gp, int value);
-	/** List */
-	struct sbi_dlist node;
-};
-
-static inline struct gpio_chip *to_gpio_chip(struct sbi_dlist *node)
-{
-	return container_of(node, struct gpio_chip, node);
-}
-
-/** Find a registered GPIO chip */
-struct gpio_chip *gpio_chip_find(unsigned int id);
-
-/** Register GPIO chip */
-int gpio_chip_add(struct gpio_chip *gc);
-
-/** Un-register GPIO chip */
-void gpio_chip_remove(struct gpio_chip *gc);
-
-/** Get current direction of GPIO pin */
-int gpio_get_direction(struct gpio_pin *gp);
-
-/** Set input direction of GPIO pin */
-int gpio_direction_input(struct gpio_pin *gp);
-
-/** Set output direction of GPIO pin */
-int gpio_direction_output(struct gpio_pin *gp, int value);
-
-/** Get current value of GPIO pin */
-int gpio_get(struct gpio_pin *gp);
-
-/** Set output value of GPIO pin */
-int gpio_set(struct gpio_pin *gp, int value);
-
-#endif
--- a/include/sbi_utils/i2c/fdt_i2c.h
+++ b/include/sbi_utils/i2c/fdt_i2c.h
@@ -1,26 +0,0 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2021 YADRO
- *
- * Authors:
- *   Nikita Shubin <n.shubin@yadro.com>
- */
-
-#ifndef __FDT_I2C_H__
-#define __FDT_I2C_H__
-
-#include <sbi_utils/i2c/i2c.h>
-
-/** FDT based I2C adapter driver */
-struct fdt_i2c_adapter {
-	const struct fdt_match *match_table;
-	int (*init)(void *fdt, int nodeoff,
-		    const struct fdt_match *match);
-};
-
-/** Get I2C adapter identified by nodeoff */
-int fdt_i2c_adapter_get(void *fdt, int nodeoff,
-			struct i2c_adapter **out_adapter);
-
-#endif
--- a/include/sbi_utils/i2c/i2c.h
+++ b/include/sbi_utils/i2c/i2c.h
@@ -1,85 +0,0 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2021 YADRO
- *
- * Authors:
- *   Nikita Shubin <n.shubin@yadro.com>
- */
-
-#ifndef __I2C_H__
-#define __I2C_H__
-
-#include <sbi/sbi_types.h>
-#include <sbi/sbi_list.h>
-
-/** Representation of a I2C adapter */
-struct i2c_adapter {
-	/** Pointer to I2C driver owning this I2C adapter */
-	void *driver;
-
-	/** Unique ID of the I2C adapter assigned by the driver */
-	int id;
-
-	/**
-	 * Send buffer to given address, register
-	 *
-	 * @return 0 on success and negative error code on failure
-	 */
-	int (*write)(struct i2c_adapter *ia, uint8_t addr, uint8_t reg,
-		    uint8_t *buffer, int len);
-
-	/**
-	 * Read buffer from given address, register
-	 *
-	 * @return 0 on success and negative error code on failure
-	 */
-	int (*read)(struct i2c_adapter *ia, uint8_t addr, uint8_t reg,
-		    uint8_t *buffer, int len);
-
-	/** List */
-	struct sbi_dlist node;
-};
-
-static inline struct i2c_adapter *to_i2c_adapter(struct sbi_dlist *node)
-{
-	return container_of(node, struct i2c_adapter, node);
-}
-
-/** Find a registered I2C adapter */
-struct i2c_adapter *i2c_adapter_find(int id);
-
-/** Register I2C adapter */
-int i2c_adapter_add(struct i2c_adapter *ia);
-
-/** Un-register I2C adapter */
-void i2c_adapter_remove(struct i2c_adapter *ia);
-
-/** Send to device on I2C adapter bus */
-int i2c_adapter_write(struct i2c_adapter *ia, uint8_t addr, uint8_t reg,
-		      uint8_t *buffer, int len);
-
-/** Read from device on I2C adapter bus */
-int i2c_adapter_read(struct i2c_adapter *ia, uint8_t addr, uint8_t reg,
-		     uint8_t *buffer, int len);
-
-static inline int i2c_adapter_reg_write(struct i2c_adapter *ia, uint8_t addr,
-				 uint8_t reg, uint8_t val)
-{
-	return i2c_adapter_write(ia, addr, reg, &val, 1);
-}
-
-static inline int i2c_adapter_reg_read(struct i2c_adapter *ia, uint8_t addr,
-				       uint8_t reg, uint8_t *val)
-{
-	uint8_t buf;
-	int ret = i2c_adapter_read(ia, addr, reg, &buf, 1);
-
-	if (ret)
-		return ret;
-
-	*val = buf;
-	return 0;
-}
-
-#endif
--- a/include/sbi_utils/ipi/aclint_mswi.h
+++ b/include/sbi_utils/ipi/aclint_mswi.h
@@ -1,33 +0,0 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2021 Western Digital Corporation or its affiliates.
- *
- * Authors:
- *   Anup Patel <anup.patel@wdc.com>
- */
-
-#ifndef __IPI_ACLINT_MSWI_H__
-#define __IPI_ACLINT_MSWI_H__
-
-#include <sbi/sbi_types.h>
-
-#define ACLINT_MSWI_ALIGN		0x1000
-#define ACLINT_MSWI_SIZE		0x4000
-#define ACLINT_MSWI_MAX_HARTS		4095
-
-#define CLINT_MSWI_OFFSET		0x0000
-
-struct aclint_mswi_data {
-	/* Public details */
-	unsigned long addr;
-	unsigned long size;
-	u32 first_hartid;
-	u32 hart_count;
-};
-
-int aclint_mswi_warm_init(void);
-
-int aclint_mswi_cold_init(struct aclint_mswi_data *mswi);
-
-#endif
--- a/include/sbi_utils/ipi/andes_plicsw.h
+++ b/include/sbi_utils/ipi/andes_plicsw.h
@@ -1,46 +0,0 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2022 Andes Technology Corporation
- *
- * Authors:
- *   Zong Li <zong@andestech.com>
- *   Nylon Chen <nylon7@andestech.com>
- *   Leo Yu-Chi Liang <ycliang@andestech.com>
- *   Yu Chien Peter Lin <peterlin@andestech.com>
- */
-
-#ifndef _IPI_ANDES_PLICSW_H_
-#define _IPI_ANDES_PLICSW_H_
-
-#define PLICSW_PRIORITY_BASE 0x4
-
-#define PLICSW_PENDING_BASE 0x1000
-#define PLICSW_PENDING_STRIDE 0x8
-
-#define PLICSW_ENABLE_BASE 0x2000
-#define PLICSW_ENABLE_STRIDE 0x80
-
-#define PLICSW_CONTEXT_BASE 0x200000
-#define PLICSW_CONTEXT_STRIDE 0x1000
-#define PLICSW_CONTEXT_CLAIM 0x4
-
-#define PLICSW_HART_MASK 0x01010101
-
-#define PLICSW_HART_MAX_NR 8
-
-#define PLICSW_REGION_ALIGN 0x1000
-
-struct plicsw_data {
-	unsigned long addr;
-	unsigned long size;
-	uint32_t hart_count;
-	/* hart id to source id table */
-	uint32_t source_id[PLICSW_HART_MAX_NR];
-};
-
-int plicsw_warm_ipi_init(void);
-
-int plicsw_cold_ipi_init(struct plicsw_data *plicsw);
-
-#endif /* _IPI_ANDES_PLICSW_H_ */
--- a/include/sbi_utils/ipi/fdt_ipi.h
+++ b/include/sbi_utils/ipi/fdt_ipi.h
@@ -12,8 +12,6 @@

 #include <sbi/sbi_types.h>

-#ifdef CONFIG_FDT_IPI
-
 struct fdt_ipi {
 	const struct fdt_match *match_table;
 	int (*cold_init)(void *fdt, int nodeoff, const struct fdt_match *match);
@@ -25,11 +23,4 @@ void fdt_ipi_exit(void);

 int fdt_ipi_init(bool cold_boot);

-#else
-
-static inline void fdt_ipi_exit(void) { }
-static inline int fdt_ipi_init(bool cold_boot) { return 0; }
-
-#endif
-
 #endif
--- a/include/sbi_utils/irqchip/aplic.h
+++ b/include/sbi_utils/irqchip/aplic.h
@@ -1,47 +0,0 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2021 Western Digital Corporation or its affiliates.
- * Copyright (c) 2022 Ventana Micro Systems Inc.
- *
- * Authors:
- *   Anup Patel <anup.patel@wdc.com>
- */
-
-#ifndef __IRQCHIP_APLIC_H__
-#define __IRQCHIP_APLIC_H__
-
-#include <sbi/sbi_types.h>
-
-#define APLIC_MAX_DELEGATE	16
-
-struct aplic_msicfg_data {
-	unsigned long lhxs;
-	unsigned long lhxw;
-	unsigned long hhxs;
-	unsigned long hhxw;
-	unsigned long base_addr;
-};
-
-struct aplic_delegate_data {
-	u32 first_irq;
-	u32 last_irq;
-	u32 child_index;
-};
-
-struct aplic_data {
-	unsigned long addr;
-	unsigned long size;
-	unsigned long num_idc;
-	unsigned long num_source;
-	bool targets_mmode;
-	bool has_msicfg_mmode;
-	struct aplic_msicfg_data msicfg_mmode;
-	bool has_msicfg_smode;
-	struct aplic_msicfg_data msicfg_smode;
-	struct aplic_delegate_data delegate[APLIC_MAX_DELEGATE];
-};
-
-int aplic_cold_irqchip_init(struct aplic_data *aplic);
-
-#endif
--- a/include/sbi_utils/irqchip/fdt_irqchip.h
+++ b/include/sbi_utils/irqchip/fdt_irqchip.h
@@ -12,8 +12,6 @@

 #include <sbi/sbi_types.h>

-#ifdef CONFIG_FDT_IRQCHIP
-
 struct fdt_irqchip {
 	const struct fdt_match *match_table;
 	int (*cold_init)(void *fdt, int nodeoff, const struct fdt_match *match);
@@ -25,12 +23,4 @@ void fdt_irqchip_exit(void);

 int fdt_irqchip_init(bool cold_boot);

-#else
-
-static inline void fdt_irqchip_exit(void) { }
-
-static inline int fdt_irqchip_init(bool cold_boot) { return 0; }
-
-#endif
-
 #endif
--- a/include/sbi_utils/irqchip/fdt_irqchip_plic.h
+++ b/include/sbi_utils/irqchip/fdt_irqchip_plic.h
@@ -1,33 +0,0 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2022 Samuel Holland <samuel@sholland.org>
- */
-
-#ifndef __IRQCHIP_FDT_IRQCHIP_PLIC_H__
-#define __IRQCHIP_FDT_IRQCHIP_PLIC_H__
-
-#include <sbi/sbi_types.h>
-
-/**
- * Save the PLIC priority state
- * @param priority pointer to the memory region for the saved priority
- * @param num size of the memory region including interrupt source 0
- */
-void fdt_plic_priority_save(u8 *priority, u32 num);
-
-/**
- * Restore the PLIC priority state
- * @param priority pointer to the memory region for the saved priority
- * @param num size of the memory region including interrupt source 0
- */
-void fdt_plic_priority_restore(const u8 *priority, u32 num);
-
-void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold, u32 num);
-
-void fdt_plic_context_restore(bool smode, const u32 *enable, u32 threshold,
-			      u32 num);
-
-void thead_plic_restore(void);
-
-#endif
--- a/include/sbi_utils/irqchip/imsic.h
+++ b/include/sbi_utils/irqchip/imsic.h
@@ -1,60 +0,0 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2021 Western Digital Corporation or its affiliates.
- * Copyright (c) 2022 Ventana Micro Systems Inc.
- *
- * Authors:
- *   Anup Patel <anup.patel@wdc.com>
- */
-
-#ifndef __IRQCHIP_IMSIC_H__
-#define __IRQCHIP_IMSIC_H__
-
-#include <sbi/sbi_types.h>
-
-#define IMSIC_MMIO_PAGE_SHIFT		12
-#define IMSIC_MMIO_PAGE_SZ		(1UL << IMSIC_MMIO_PAGE_SHIFT)
-
-#define IMSIC_MAX_REGS			16
-
-struct imsic_regs {
-	unsigned long addr;
-	unsigned long size;
-};
-
-struct imsic_data {
-	bool targets_mmode;
-	u32 guest_index_bits;
-	u32 hart_index_bits;
-	u32 group_index_bits;
-	u32 group_index_shift;
-	unsigned long num_ids;
-	struct imsic_regs regs[IMSIC_MAX_REGS];
-};
-
-#ifdef CONFIG_IRQCHIP_IMSIC
-
-int imsic_map_hartid_to_data(u32 hartid, struct imsic_data *imsic, int file);
-
-struct imsic_data *imsic_get_data(u32 hartid);
-
-int imsic_get_target_file(u32 hartid);
-
-void imsic_local_irqchip_init(void);
-
-int imsic_warm_irqchip_init(void);
-
-int imsic_data_check(struct imsic_data *imsic);
-
-int imsic_cold_irqchip_init(struct imsic_data *imsic);
-
-#else
-
-static inline void imsic_local_irqchip_init(void) { }
-
-static inline int imsic_data_check(struct imsic_data *imsic) { return 0; }
-
-#endif
-
-#endif
--- a/include/sbi_utils/irqchip/plic.h
+++ b/include/sbi_utils/irqchip/plic.h
@@ -17,24 +17,13 @@ struct plic_data {
 	unsigned long num_src;
 };

-/* So far, priorities on all consumers of these functions fit in 8 bits. */
-void plic_priority_save(const struct plic_data *plic, u8 *priority, u32 num);
-
-void plic_priority_restore(const struct plic_data *plic, const u8 *priority,
-			   u32 num);
-
-void plic_context_save(const struct plic_data *plic, int context_id,
-		       u32 *enable, u32 *threshold, u32 num);
-
-void plic_context_restore(const struct plic_data *plic, int context_id,
-			  const u32 *enable, u32 threshold, u32 num);
-
-int plic_context_init(const struct plic_data *plic, int context_id,
-		      bool enable, u32 threshold);
-
-int plic_warm_irqchip_init(const struct plic_data *plic,
+int plic_warm_irqchip_init(struct plic_data *plic,
 			   int m_cntx_id, int s_cntx_id);

-int plic_cold_irqchip_init(const struct plic_data *plic);
+int plic_cold_irqchip_init(struct plic_data *plic);
+
+void plic_set_thresh(struct plic_data *plic, u32 cntxid, u32 val);
+
+void plic_set_ie(struct plic_data *plic, u32 cntxid, u32 word_index, u32 val);

 #endif
--- a/include/sbi_utils/reset/fdt_reset.h
+++ b/include/sbi_utils/reset/fdt_reset.h
@@ -17,28 +17,6 @@ struct fdt_reset {
 	int (*init)(void *fdt, int nodeoff, const struct fdt_match *match);
 };

-#ifdef CONFIG_FDT_RESET
-
-/**
- * fdt_reset_driver_init() - initialize reset driver based on the device-tree
- */
-int fdt_reset_driver_init(void *fdt, struct fdt_reset *drv);
-
-/**
- * fdt_reset_init() - initialize reset drivers based on the device-tree
- *
- * This function shall be invoked in final init.
- */
-void fdt_reset_init(void);
-
-#else
-
-static inline int fdt_reset_driver_init(void *fdt, struct fdt_reset *drv)
-{
-	return 0;
-}
-static inline void fdt_reset_init(void) { }
-
-#endif
+int fdt_reset_init(void);

 #endif
--- a/include/sbi_utils/serial/cadence-uart.h
+++ b/include/sbi_utils/serial/cadence-uart.h
@@ -1,16 +0,0 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2022 StarFive Technology Co., Ltd.
- *
- * Author: Jun Liang Tan <junliang.tan@linux.starfivetech.com>
- */
-
-#ifndef __SERIAL_CADENCE_UART_H__
-#define __SERIAL_CADENCE_UART_H__
-
-#include <sbi/sbi_types.h>
-
-int cadence_uart_init(unsigned long base, u32 in_freq, u32 baudrate);
-
-#endif
--- a/include/sbi_utils/serial/fdt_serial.h
+++ b/include/sbi_utils/serial/fdt_serial.h
@@ -12,8 +12,6 @@

 #include <sbi/sbi_types.h>

-#ifdef CONFIG_FDT_SERIAL
-
 struct fdt_serial {
 	const struct fdt_match *match_table;
 	int (*init)(void *fdt, int nodeoff, const struct fdt_match *match);
@@ -21,10 +19,4 @@ struct fdt_serial {

 int fdt_serial_init(void);

-#else
-
-static inline int fdt_serial_init(void) { return 0; }
-
-#endif
-
 #endif
--- a/include/sbi_utils/serial/gaisler-uart.h
+++ b/include/sbi_utils/serial/gaisler-uart.h
@@ -1,17 +0,0 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2021 Cobham Gaisler AB.
- *
- * Authors:
- *   Daniel Cederman <cederman@gaisler.com>
- */
-
-#ifndef __SERIAL_GAISLER_APBUART_H__
-#define __SERIAL_GAISLER_APBUART_H__
-
-#include <sbi/sbi_types.h>
-
-int gaisler_uart_init(unsigned long base, u32 in_freq, u32 baudrate);
-
-#endif
--- a/include/sbi_utils/serial/litex-uart.h
+++ b/include/sbi_utils/serial/litex-uart.h
@@ -1,17 +0,0 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2021 Gabriel Somlo
- *
- * Authors:
- *   Gabriel Somlo <gsomlo@gmail.com>
- */
-
-#ifndef __SERIAL_LITEX_UART_H__
-#define __SERIAL_LITEX_UART_H__
-
-#include <sbi/sbi_types.h>
-
-int litex_uart_init(unsigned long base);
-
-#endif
--- a/include/sbi_utils/serial/renesas-scif.h
+++ b/include/sbi_utils/serial/renesas-scif.h
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause */
-/*
- * Copyright (C) 2022 Renesas Electronics Corporation
- */
-
-#ifndef __SERIAL_RENESAS_SCIF_H__
-#define __SERIAL_RENESAS_SCIF_H__
-
-int renesas_scif_init(unsigned long base, u32 in_freq, u32 baudrate);
-
-#endif /* __SERIAL_RENESAS_SCIF_H__ */
--- a/include/sbi_utils/serial/semihosting.h
+++ b/include/sbi_utils/serial/semihosting.h
@@ -1,47 +0,0 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2022 Ventana Micro Systems Inc.
- *
- * Authors:
- *   Anup Patel <apatel@ventanamicro.com>
- *   Kautuk Consul <kconsul@ventanamicro.com>
- */
-
-#ifndef __SERIAL_SEMIHOSTING_H__
-#define __SERIAL_SEMIHOSTING_H__
-
-#include <sbi/sbi_types.h>
-
-/**
- * enum semihosting_open_mode - Numeric file modes for use with semihosting_open()
- * MODE_READ: 'r'
- * MODE_BINARY: 'b'
- * MODE_PLUS: '+'
- * MODE_WRITE: 'w'
- * MODE_APPEND: 'a'
- *
- * These modes represent the mode string used by fopen(3) in a form which can
- * be passed to semihosting_open(). These do NOT correspond directly to %O_RDONLY,
- * %O_CREAT, etc; see fopen(3) for details. In particular, @MODE_PLUS
- * effectively results in adding %O_RDWR, and @MODE_WRITE will add %O_TRUNC.
- * For compatibility, @MODE_BINARY should be added when opening non-text files
- * (such as images).
- */
-enum semihosting_open_mode {
-	MODE_READ	= 0x0,
-	MODE_BINARY	= 0x1,
-	MODE_PLUS	= 0x2,
-	MODE_WRITE	= 0x4,
-	MODE_APPEND	= 0x8,
-};
-
-#ifdef CONFIG_SERIAL_SEMIHOSTING
-int semihosting_init(void);
-int semihosting_enabled(void);
-#else
-static inline int semihosting_init(void) { return SBI_ENODEV; }
-static inline int semihosting_enabled(void) { return 0; }
-#endif
-
-#endif
--- a/include/sbi_utils/serial/uart8250.h
+++ b/include/sbi_utils/serial/uart8250.h
@@ -13,6 +13,6 @@
 #include <sbi/sbi_types.h>

 int uart8250_init(unsigned long base, u32 in_freq, u32 baudrate, u32 reg_shift,
-		  u32 reg_width, u32 reg_offset);
+		  u32 reg_width);

 #endif
--- a/include/sbi_utils/serial/xlnx_uartlite.h
+++ b/include/sbi_utils/serial/xlnx_uartlite.h
@@ -1,16 +0,0 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2022 Western Digital Corporation or its affiliates.
- *
- * Authors:
- *   Alistair Francis <alistair.francis@wdc.com>
- */
-#ifndef __SERIAL_XLNX_UARTLITE_H__
-#define __SERIAL_XLNX_UARTLITE_H__
-
-#include <sbi/sbi_types.h>
-
-int xlnx_uartlite_init(unsigned long base);
-
-#endif
--- a/include/sbi_utils/sys/clint.h
+++ b/include/sbi_utils/sys/clint.h
@@ -0,0 +1,41 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel <anup.patel@wdc.com>
+ */
+
+#ifndef __SYS_CLINT_H__
+#define __SYS_CLINT_H__
+
+#include <sbi/sbi_types.h>
+
+struct clint_data {
+	/* Public details */
+	unsigned long addr;
+	u32 first_hartid;
+	u32 hart_count;
+	bool has_64bit_mmio;
+	/* Private details (initialized and used by CLINT library)*/
+	u32 *ipi;
+	struct clint_data *time_delta_reference;
+	unsigned long time_delta_computed;
+	u64 time_delta;
+	u64 *time_val;
+	u64 *time_cmp;
+	u64 (*time_rd)(volatile u64 *addr);
+	void (*time_wr)(u64 value, volatile u64 *addr);
+};
+
+int clint_warm_ipi_init(void);
+
+int clint_cold_ipi_init(struct clint_data *clint);
+
+int clint_warm_timer_init(void);
+
+int clint_cold_timer_init(struct clint_data *clint,
+			  struct clint_data *reference);
+
+#endif
--- a/include/sbi_utils/sys/htif.h
+++ b/include/sbi_utils/sys/htif.h
@@ -10,12 +10,8 @@

 #include <sbi/sbi_types.h>

-int htif_serial_init(bool custom_addr,
-		     unsigned long custom_fromhost_addr,
-		     unsigned long custom_tohost_addr);
+int htif_serial_init(void);

-int htif_system_reset_init(bool custom_addr,
-			   unsigned long custom_fromhost_addr,
-			   unsigned long custom_tohost_addr);
+int htif_system_reset_init(void);

 #endif
--- a/include/sbi_utils/timer/aclint_mtimer.h
+++ b/include/sbi_utils/timer/aclint_mtimer.h
@@ -1,55 +0,0 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2021 Western Digital Corporation or its affiliates.
- *
- * Authors:
- *   Anup Patel <anup.patel@wdc.com>
- */
-
-#ifndef __TIMER_ACLINT_MTIMER_H__
-#define __TIMER_ACLINT_MTIMER_H__
-
-#include <sbi/sbi_types.h>
-
-#define ACLINT_MTIMER_ALIGN		0x8
-#define ACLINT_MTIMER_MAX_HARTS		4095
-
-#define ACLINT_DEFAULT_MTIME_OFFSET	0x7ff8
-#define ACLINT_DEFAULT_MTIME_SIZE	0x8
-#define ACLINT_DEFAULT_MTIMECMP_OFFSET	0x0000
-#define ACLINT_DEFAULT_MTIMECMP_SIZE	0x7ff8
-
-#define CLINT_MTIMER_OFFSET		0x4000
-
-#define MTIMER_REGION_ALIGN		0x1000
-
-struct aclint_mtimer_data {
-	/* Public details */
-	unsigned long mtime_freq;
-	unsigned long mtime_addr;
-	unsigned long mtime_size;
-	unsigned long mtimecmp_addr;
-	unsigned long mtimecmp_size;
-	u32 first_hartid;
-	u32 hart_count;
-	bool has_64bit_mmio;
-	bool has_shared_mtime;
-	/* Private details (initialized and used by ACLINT MTIMER library) */
-	struct aclint_mtimer_data *time_delta_reference;
-	unsigned long time_delta_computed;
-	u64 (*time_rd)(volatile u64 *addr);
-	void (*time_wr)(bool timecmp, u64 value, volatile u64 *addr);
-};
-
-void aclint_mtimer_sync(struct aclint_mtimer_data *mt);
-
-void aclint_mtimer_set_reference(struct aclint_mtimer_data *mt,
-				 struct aclint_mtimer_data *ref);
-
-int aclint_mtimer_warm_init(void);
-
-int aclint_mtimer_cold_init(struct aclint_mtimer_data *mt,
-			    struct aclint_mtimer_data *reference);
-
-#endif
--- a/include/sbi_utils/timer/andes_plmt.h
+++ b/include/sbi_utils/timer/andes_plmt.h
@@ -1,29 +0,0 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2022 Andes Technology Corporation
- *
- * Authors:
- *   Zong Li <zong@andestech.com>
- *   Nylon Chen <nylon7@andestech.com>
- *   Yu Chien Peter Lin <peterlin@andestech.com>
- */
-
-#ifndef __TIMER_ANDES_PLMT_H__
-#define __TIMER_ANDES_PLMT_H__
-
-#define DEFAULT_AE350_PLMT_FREQ 60000000
-#define PLMT_REGION_ALIGN 0x1000
-
-struct plmt_data {
-	u32 hart_count;
-	unsigned long size;
-	unsigned long timer_freq;
-	volatile u64 *time_val;
-	volatile u64 *time_cmp;
-};
-
-int plmt_cold_timer_init(struct plmt_data *plmt);
-int plmt_warm_timer_init(void);
-
-#endif /* __TIMER_ANDES_PLMT_H__ */
--- a/include/sbi_utils/timer/fdt_timer.h
+++ b/include/sbi_utils/timer/fdt_timer.h
@@ -12,8 +12,6 @@

 #include <sbi/sbi_types.h>

-#ifdef CONFIG_FDT_TIMER
-
 struct fdt_timer {
 	const struct fdt_match *match_table;
 	int (*cold_init)(void *fdt, int nodeoff, const struct fdt_match *match);
@@ -25,11 +23,4 @@ void fdt_timer_exit(void);

 int fdt_timer_init(bool cold_boot);

-#else
-
-static inline void fdt_timer_exit(void) { }
-static inline int fdt_timer_init(bool cold_boot) { return 0; }
-
-#endif
-
 #endif
--- a/lib/sbi/Kconfig
+++ b/lib/sbi/Kconfig
@@ -1,37 +0,0 @@
-# SPDX-License-Identifier: BSD-2-Clause
-
-menu "SBI Extension Support"
-
-config SBI_ECALL_TIME
-	bool "Timer extension"
-	default y
-
-config SBI_ECALL_RFENCE
-	bool "RFENCE extension"
-	default y
-
-config SBI_ECALL_IPI
-	bool "IPI extension"
-	default y
-
-config SBI_ECALL_HSM
-	bool "Hart State Management extension"
-	default y
-
-config SBI_ECALL_SRST
-	bool "System Reset extension"
-	default y
-
-config SBI_ECALL_PMU
-	bool "Performance Monitoring Unit extension"
-	default y
-
-config SBI_ECALL_LEGACY
-	bool "SBI v0.1 legacy extensions"
-	default y
-
-config SBI_ECALL_VENDOR
-	bool "Platform-defined vendor extensions"
-	default y
-
-endmenu
--- a/lib/sbi/objects.mk
+++ b/lib/sbi/objects.mk
@@ -12,41 +12,17 @@ libsbi-objs-y += riscv_atomic.o
 libsbi-objs-y += riscv_hardfp.o
 libsbi-objs-y += riscv_locks.o

-libsbi-objs-y += sbi_ecall.o
-libsbi-objs-y += sbi_ecall_exts.o
-
-# The order of below extensions is performance optimized
-carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_TIME) += ecall_time
-libsbi-objs-$(CONFIG_SBI_ECALL_TIME) += sbi_ecall_time.o
-
-carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_RFENCE) += ecall_rfence
-libsbi-objs-$(CONFIG_SBI_ECALL_RFENCE) += sbi_ecall_rfence.o
-
-carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_IPI) += ecall_ipi
-libsbi-objs-$(CONFIG_SBI_ECALL_IPI) += sbi_ecall_ipi.o
-
-carray-sbi_ecall_exts-y += ecall_base
-libsbi-objs-y += sbi_ecall_base.o
-
-carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_HSM) += ecall_hsm
-libsbi-objs-$(CONFIG_SBI_ECALL_HSM) += sbi_ecall_hsm.o
-
-carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_SRST) += ecall_srst
-libsbi-objs-$(CONFIG_SBI_ECALL_SRST) += sbi_ecall_srst.o
-
-carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_PMU) += ecall_pmu
-libsbi-objs-$(CONFIG_SBI_ECALL_PMU) += sbi_ecall_pmu.o
-
-carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_LEGACY) += ecall_legacy
-libsbi-objs-$(CONFIG_SBI_ECALL_LEGACY) += sbi_ecall_legacy.o
-
-carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_VENDOR) += ecall_vendor
-libsbi-objs-$(CONFIG_SBI_ECALL_VENDOR) += sbi_ecall_vendor.o
-
 libsbi-objs-y += sbi_bitmap.o
 libsbi-objs-y += sbi_bitops.o
 libsbi-objs-y += sbi_console.o
 libsbi-objs-y += sbi_domain.o
+libsbi-objs-y += sbi_ecall.o
+libsbi-objs-y += sbi_ecall_base.o
+libsbi-objs-y += sbi_ecall_hsm.o
+libsbi-objs-y += sbi_ecall_legacy.o
+libsbi-objs-y += sbi_ecall_replace.o
+libsbi-objs-y += sbi_ecall_vendor.o
+libsbi-objs-y += sbi_ecall_susp.o
 libsbi-objs-y += sbi_emulate_csr.o
 libsbi-objs-y += sbi_fifo.o
 libsbi-objs-y += sbi_hart.o
@@ -56,10 +32,8 @@ libsbi-objs-y += sbi_hsm.o
 libsbi-objs-y += sbi_illegal_insn.o
 libsbi-objs-y += sbi_init.o
 libsbi-objs-y += sbi_ipi.o
-libsbi-objs-y += sbi_irqchip.o
 libsbi-objs-y += sbi_misaligned_ldst.o
 libsbi-objs-y += sbi_platform.o
-libsbi-objs-y += sbi_pmu.o
 libsbi-objs-y += sbi_scratch.o
 libsbi-objs-y += sbi_string.o
 libsbi-objs-y += sbi_system.o
--- a/lib/sbi/riscv_asm.c
+++ b/lib/sbi/riscv_asm.c
@@ -11,7 +11,6 @@
 #include <sbi/riscv_encoding.h>
 #include <sbi/sbi_error.h>
 #include <sbi/sbi_platform.h>
-#include <sbi/sbi_console.h>

 /* determine CPU extension, return non-zero support */
 int misa_extension_imp(char ext)
@@ -53,7 +52,7 @@ int misa_xlen(void)
 void misa_string(int xlen, char *out, unsigned int out_sz)
 {
 	unsigned int i, pos = 0;
-	const char valid_isa_order[] = "iemafdqclbjtpvnhkorwxyzg";
+	const char valid_isa_order[] = "iemafdqclbjtpvnsuhkorwxyzg";

 	if (!out)
 		return;
@@ -76,8 +75,6 @@ void misa_string(int xlen, char *out, unsigned int out_sz)
 			out[pos++] = '8';
 			break;
 		default:
-			sbi_panic("%s: Unknown misa.MXL encoding %d",
-				   __func__, xlen);
 			return;
 		}
 	}
@@ -121,36 +118,7 @@ unsigned long csr_read_num(int csr_num)
 	switch (csr_num) {
 	switchcase_csr_read_16(CSR_PMPCFG0, ret)
 	switchcase_csr_read_64(CSR_PMPADDR0, ret)
-	switchcase_csr_read(CSR_MCYCLE, ret)
-	switchcase_csr_read(CSR_MINSTRET, ret)
-	switchcase_csr_read(CSR_MHPMCOUNTER3, ret)
-	switchcase_csr_read_4(CSR_MHPMCOUNTER4, ret)
-	switchcase_csr_read_8(CSR_MHPMCOUNTER8, ret)
-	switchcase_csr_read_16(CSR_MHPMCOUNTER16, ret)
-	switchcase_csr_read(CSR_MCOUNTINHIBIT, ret)
-	switchcase_csr_read(CSR_MHPMEVENT3, ret)
-	switchcase_csr_read_4(CSR_MHPMEVENT4, ret)
-	switchcase_csr_read_8(CSR_MHPMEVENT8, ret)
-	switchcase_csr_read_16(CSR_MHPMEVENT16, ret)
-#if __riscv_xlen == 32
-	switchcase_csr_read(CSR_MCYCLEH, ret)
-	switchcase_csr_read(CSR_MINSTRETH, ret)
-	switchcase_csr_read(CSR_MHPMCOUNTER3H, ret)
-	switchcase_csr_read_4(CSR_MHPMCOUNTER4H, ret)
-	switchcase_csr_read_8(CSR_MHPMCOUNTER8H, ret)
-	switchcase_csr_read_16(CSR_MHPMCOUNTER16H, ret)
-	/**
-	 * The CSR range MHPMEVENT[3-16]H are available only if sscofpmf
-	 * extension is present. The caller must ensure that.
-	 */
-	switchcase_csr_read(CSR_MHPMEVENT3H, ret)
-	switchcase_csr_read_4(CSR_MHPMEVENT4H, ret)
-	switchcase_csr_read_8(CSR_MHPMEVENT8H, ret)
-	switchcase_csr_read_16(CSR_MHPMEVENT16H, ret)
-#endif
-
 	default:
-		sbi_panic("%s: Unknown CSR %#x", __func__, csr_num);
 		break;
 	};

@@ -193,32 +161,7 @@ void csr_write_num(int csr_num, unsigned long val)
 	switch (csr_num) {
 	switchcase_csr_write_16(CSR_PMPCFG0, val)
 	switchcase_csr_write_64(CSR_PMPADDR0, val)
-	switchcase_csr_write(CSR_MCYCLE, val)
-	switchcase_csr_write(CSR_MINSTRET, val)
-	switchcase_csr_write(CSR_MHPMCOUNTER3, val)
-	switchcase_csr_write_4(CSR_MHPMCOUNTER4, val)
-	switchcase_csr_write_8(CSR_MHPMCOUNTER8, val)
-	switchcase_csr_write_16(CSR_MHPMCOUNTER16, val)
-#if __riscv_xlen == 32
-	switchcase_csr_write(CSR_MCYCLEH, val)
-	switchcase_csr_write(CSR_MINSTRETH, val)
-	switchcase_csr_write(CSR_MHPMCOUNTER3H, val)
-	switchcase_csr_write_4(CSR_MHPMCOUNTER4H, val)
-	switchcase_csr_write_8(CSR_MHPMCOUNTER8H, val)
-	switchcase_csr_write_16(CSR_MHPMCOUNTER16H, val)
-	switchcase_csr_write(CSR_MHPMEVENT3H, val)
-	switchcase_csr_write_4(CSR_MHPMEVENT4H, val)
-	switchcase_csr_write_8(CSR_MHPMEVENT8H, val)
-	switchcase_csr_write_16(CSR_MHPMEVENT16H, val)
-#endif
-	switchcase_csr_write(CSR_MCOUNTINHIBIT, val)
-	switchcase_csr_write(CSR_MHPMEVENT3, val)
-	switchcase_csr_write_4(CSR_MHPMEVENT4, val)
-	switchcase_csr_write_8(CSR_MHPMEVENT8, val)
-	switchcase_csr_write_16(CSR_MHPMEVENT16, val)
-
 	default:
-		sbi_panic("%s: Unknown CSR %#x", __func__, csr_num);
 		break;
 	};

@@ -235,9 +178,6 @@ static unsigned long ctz(unsigned long x)
 {
 	unsigned long ret = 0;

-	if (x == 0)
-		return 8 * sizeof(x);
-
 	while (!(x & 1UL)) {
 		ret++;
 		x = x >> 1;
@@ -265,12 +205,14 @@ int pmp_set(unsigned int n, unsigned long prot, unsigned long addr,
 	pmpcfg_csr   = (CSR_PMPCFG0 + (n >> 2)) & ~1;
 	pmpcfg_shift = (n & 7) << 3;
 #else
-# error "Unexpected __riscv_xlen"
+	pmpcfg_csr   = -1;
+	pmpcfg_shift = -1;
 #endif
 	pmpaddr_csr = CSR_PMPADDR0 + n;
+	if (pmpcfg_csr < 0 || pmpcfg_shift < 0)
+		return SBI_ENOTSUPP;

 	/* encode PMP config */
-	prot &= ~PMP_A;
 	prot |= (log2len == PMP_SHIFT) ? PMP_A_NA4 : PMP_A_NAPOT;
 	cfgmask = ~(0xffUL << pmpcfg_shift);
 	pmpcfg	= (csr_read_num(pmpcfg_csr) & cfgmask);
@@ -316,9 +258,12 @@ int pmp_get(unsigned int n, unsigned long *prot_out, unsigned long *addr_out,
 	pmpcfg_csr   = (CSR_PMPCFG0 + (n >> 2)) & ~1;
 	pmpcfg_shift = (n & 7) << 3;
 #else
-# error "Unexpected __riscv_xlen"
+	pmpcfg_csr   = -1;
+	pmpcfg_shift = -1;
 #endif
 	pmpaddr_csr = CSR_PMPADDR0 + n;
+	if (pmpcfg_csr < 0 || pmpcfg_shift < 0)
+		return SBI_ENOTSUPP;

 	/* decode PMP config */
 	cfgmask = (0xffUL << pmpcfg_shift);
--- a/lib/sbi/riscv_locks.c
+++ b/lib/sbi/riscv_locks.c
@@ -8,7 +8,7 @@
 #include <sbi/riscv_barrier.h>
 #include <sbi/riscv_locks.h>

-static inline bool spin_lock_unlocked(spinlock_t lock)
+static inline int spin_lock_unlocked(spinlock_t lock)
 {
 	return lock.owner == lock.next;
 }
@@ -19,7 +19,7 @@ bool spin_lock_check(spinlock_t *lock)
 	return !spin_lock_unlocked(*lock);
 }

-bool spin_trylock(spinlock_t *lock)
+int spin_trylock(spinlock_t *lock)
 {
 	unsigned long inc = 1u << TICKET_SHIFT;
 	unsigned long mask = 0xffffu << TICKET_SHIFT;
@@ -42,7 +42,7 @@ bool spin_trylock(spinlock_t *lock)
 		: "r"(inc), "r"(mask), "I"(TICKET_SHIFT)
 		: "memory");

-	return l0 == 0;
+	return !l0;
 }

 void spin_lock(spinlock_t *lock)
--- a/lib/sbi/sbi_bitops.c
+++ b/lib/sbi/sbi_bitops.c
@@ -39,7 +39,7 @@ unsigned long find_first_bit(const unsigned long *addr,
 	if (tmp == 0UL)		/* Are any bits set? */
 		return result + size;	/* Nope. */
 found:
-	return result + sbi_ffs(tmp);
+	return result + __ffs(tmp);
 }

 /**
@@ -69,7 +69,7 @@ unsigned long find_first_zero_bit(const unsigned long *addr,
 	if (tmp == ~0UL)	/* Are any bits zero? */
 		return result + size;	/* Nope. */
 found:
-	return result + sbi_ffz(tmp);
+	return result + ffz(tmp);
 }

 /**
@@ -100,7 +100,7 @@ unsigned long find_last_bit(const unsigned long *addr,
 		tmp = addr[--words];
 		if (tmp) {
 found:
-			return words * BITS_PER_LONG + sbi_fls(tmp);
+			return words * BITS_PER_LONG + __fls(tmp);
 		}
 	}

@@ -150,7 +150,7 @@ found_first:
 	if (tmp == 0UL)		/* Are any bits set? */
 		return result + size;	/* Nope. */
 found_middle:
-	return result + sbi_ffs(tmp);
+	return result + __ffs(tmp);
 }

 /**
@@ -196,5 +196,5 @@ found_first:
 	if (tmp == ~0UL)	/* Are any bits zero? */
 		return result + size;	/* Nope. */
 found_middle:
-	return result + sbi_ffz(tmp);
+	return result + ffz(tmp);
 }
--- a/lib/sbi/sbi_console.c
+++ b/lib/sbi/sbi_console.c
@@ -9,7 +9,6 @@

 #include <sbi/riscv_locks.h>
 #include <sbi/sbi_console.h>
-#include <sbi/sbi_hart.h>
 #include <sbi/sbi_platform.h>
 #include <sbi/sbi_scratch.h>

@@ -76,22 +75,20 @@ typedef __builtin_va_list va_list;

 static void printc(char **out, u32 *out_len, char ch)
 {
-	if (!out) {
+	if (out) {
+		if (*out) {
+			if (out_len && (0 < *out_len)) {
+				**out = ch;
+				++(*out);
+				(*out_len)--;
+			} else {
+				**out = ch;
+				++(*out);
+			}
+		}
+	} else {
 		sbi_putc(ch);
-		return;
 	}
-
-	/*
-	 * The *printf entry point functions have enforced that (*out) can
-	 * only be null when out_len is non-null and its value is zero.
-	 */
-	if (!out_len || *out_len > 1) {
-		*(*out)++ = ch;
-		**out = '\0';
-	}
-
-	if (out_len && *out_len > 0)
-		--(*out_len);
 }

 static int prints(char **out, u32 *out_len, const char *string, int width,
@@ -183,7 +180,7 @@ static int printi(char **out, u32 *out_len, long long i, int b, int sg,

 static int print(char **out, u32 *out_len, const char *format, va_list args)
 {
-	int width, flags;
+	int width, flags, acnt = 0;
 	int pc = 0;
 	char scr[2];
 	unsigned long long tmp;
@@ -195,7 +192,7 @@ static int print(char **out, u32 *out_len, const char *format, va_list args)
 			if (*format == '\0')
 				break;
 			if (*format == '%')
-				goto literal;
+				goto out;
 			/* Get flags */
 			if (*format == '-') {
 				++format;
@@ -216,6 +213,7 @@ static int print(char **out, u32 *out_len, const char *format, va_list args)
 			}
 			if (*format == 's') {
 				char *s = va_arg(args, char *);
+				acnt += sizeof(char *);
 				pc += prints(out, out_len, s ? s : "(null)",
 					     width, flags);
 				continue;
@@ -223,40 +221,61 @@ static int print(char **out, u32 *out_len, const char *format, va_list args)
 			if ((*format == 'd') || (*format == 'i')) {
 				pc += printi(out, out_len, va_arg(args, int),
 					     10, 1, width, flags, '0');
+				acnt += sizeof(int);
 				continue;
 			}
 			if (*format == 'x') {
 				pc += printi(out, out_len,
 					     va_arg(args, unsigned int), 16, 0,
 					     width, flags, 'a');
+				acnt += sizeof(unsigned int);
 				continue;
 			}
 			if (*format == 'X') {
 				pc += printi(out, out_len,
 					     va_arg(args, unsigned int), 16, 0,
 					     width, flags, 'A');
+				acnt += sizeof(unsigned int);
 				continue;
 			}
 			if (*format == 'u') {
 				pc += printi(out, out_len,
 					     va_arg(args, unsigned int), 10, 0,
 					     width, flags, 'a');
+				acnt += sizeof(unsigned int);
 				continue;
 			}
 			if (*format == 'p') {
 				pc += printi(out, out_len,
 					     va_arg(args, unsigned long), 16, 0,
 					     width, flags, 'a');
+				acnt += sizeof(unsigned long);
 				continue;
 			}
 			if (*format == 'P') {
 				pc += printi(out, out_len,
 					     va_arg(args, unsigned long), 16, 0,
 					     width, flags, 'A');
+				acnt += sizeof(unsigned long);
 				continue;
 			}
 			if (*format == 'l' && *(format + 1) == 'l') {
-				tmp = va_arg(args, unsigned long long);
+				while (acnt &
+				       (sizeof(unsigned long long) - 1)) {
+					va_arg(args, int);
+					acnt += sizeof(int);
+				}
+				if (sizeof(unsigned long long) ==
+				    sizeof(unsigned long)) {
+					tmp = va_arg(args, unsigned long long);
+					acnt += sizeof(unsigned long long);
+				} else {
+					((unsigned long *)&tmp)[0] =
+						va_arg(args, unsigned long);
+					((unsigned long *)&tmp)[1] =
+						va_arg(args, unsigned long);
+					acnt += 2 * sizeof(unsigned long);
+				}
 				if (*(format + 2) == 'u') {
 					format += 2;
 					pc += printi(out, out_len, tmp, 10, 0,
@@ -288,16 +307,19 @@ static int print(char **out, u32 *out_len, const char *format, va_list args)
 						out, out_len,
 						va_arg(args, unsigned long), 16,
 						0, width, flags, 'a');
+					acnt += sizeof(unsigned long);
 				} else if (*(format + 1) == 'X') {
 					format += 1;
 					pc += printi(
 						out, out_len,
 						va_arg(args, unsigned long), 16,
 						0, width, flags, 'A');
+					acnt += sizeof(unsigned long);
 				} else {
 					pc += printi(out, out_len,
 						     va_arg(args, long), 10, 1,
 						     width, flags, '0');
+					acnt += sizeof(long);
 				}
 			}
 			if (*format == 'c') {
@@ -305,14 +327,17 @@ static int print(char **out, u32 *out_len, const char *format, va_list args)
 				scr[0] = va_arg(args, int);
 				scr[1] = '\0';
 				pc += prints(out, out_len, scr, width, flags);
+				acnt += sizeof(int);
 				continue;
 			}
 		} else {
-literal:
+		out:
 			printc(out, out_len, *format);
 			++pc;
 		}
 	}
+	if (out)
+		**out = '\0';

 	return pc;
 }
@@ -322,9 +347,6 @@ int sbi_sprintf(char *out, const char *format, ...)
 	va_list args;
 	int retval;

-	if (unlikely(!out))
-		sbi_panic("sbi_sprintf called with NULL output string\n");
-
 	va_start(args, format);
 	retval = print(&out, NULL, format, args);
 	va_end(args);
@@ -337,10 +359,6 @@ int sbi_snprintf(char *out, u32 out_sz, const char *format, ...)
 	va_list args;
 	int retval;

-	if (unlikely(!out && out_sz != 0))
-		sbi_panic("sbi_snprintf called with NULL output string and "
-			  "output size is not zero\n");
-
 	va_start(args, format);
 	retval = print(&out, &out_sz, format, args);
 	va_end(args);
@@ -369,29 +387,13 @@ int sbi_dprintf(const char *format, ...)
 	struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();

 	va_start(args, format);
-	if (scratch->options & SBI_SCRATCH_DEBUG_PRINTS) {
-		spin_lock(&console_out_lock);
+	if (scratch->options & SBI_SCRATCH_DEBUG_PRINTS)
 		retval = print(NULL, NULL, format, args);
-		spin_unlock(&console_out_lock);
-	}
 	va_end(args);

 	return retval;
 }

-void sbi_panic(const char *format, ...)
-{
-	va_list args;
-
-	spin_lock(&console_out_lock);
-	va_start(args, format);
-	print(NULL, NULL, format, args);
-	va_end(args);
-	spin_unlock(&console_out_lock);
-
-	sbi_hart_hang();
-}
-
 const struct sbi_console_device *sbi_console_get_device(void)
 {
 	return console_dev;
--- a/lib/sbi/sbi_domain.c
+++ b/lib/sbi/sbi_domain.c
@@ -34,6 +34,7 @@ struct sbi_domain root = {
 	.possible_harts = &root_hmask,
 	.regions = root_memregs,
 	.system_reset_allowed = TRUE,
+	.system_suspend_allowed = TRUE,
 };

 bool sbi_domain_is_assigned_hart(const struct sbi_domain *dom, u32 hartid)
@@ -105,7 +106,7 @@ bool sbi_domain_check_addr(const struct sbi_domain *dom,
 			   unsigned long addr, unsigned long mode,
 			   unsigned long access_flags)
 {
-	bool rmmio, mmio = FALSE;
+	bool mmio = FALSE;
 	struct sbi_domain_memregion *reg;
 	unsigned long rstart, rend, rflags, rwx = 0;

@@ -130,8 +131,8 @@ bool sbi_domain_check_addr(const struct sbi_domain *dom,
 		rend = (reg->order < __riscv_xlen) ?
 			rstart + ((1UL << reg->order) - 1) : -1UL;
 		if (rstart <= addr && addr <= rend) {
-			rmmio = (rflags & SBI_DOMAIN_MEMREGION_MMIO) ? TRUE : FALSE;
-			if (mmio != rmmio)
+			if ((mmio && !(rflags & SBI_DOMAIN_MEMREGION_MMIO)) ||
+			    (!mmio && (rflags & SBI_DOMAIN_MEMREGION_MMIO)))
 				return FALSE;
 			return ((rflags & rwx) == rwx) ? TRUE : FALSE;
 		}
@@ -146,10 +147,7 @@ static bool is_region_valid(const struct sbi_domain_memregion *reg)
 	if (reg->order < 3 || __riscv_xlen < reg->order)
 		return FALSE;

-	if (reg->order == __riscv_xlen && reg->base != 0)
-		return FALSE;
-
-	if (reg->order < __riscv_xlen && (reg->base & (BIT(reg->order) - 1)))
+	if (reg->base & (BIT(reg->order) - 1))
 		return FALSE;

 	return TRUE;
@@ -162,7 +160,7 @@ static bool is_region_subset(const struct sbi_domain_memregion *regA,
 	ulong regA_start = regA->base;
 	ulong regA_end = regA->base + (BIT(regA->order) - 1);
 	ulong regB_start = regB->base;
-	ulong regB_end = regB->base + (BIT(regB->order) - 1);
+	ulong regB_end = regB->base + (BIT(regA->order) - 1);

 	if ((regB_start <= regA_start) &&
 	    (regA_start < regB_end) &&
@@ -298,7 +296,7 @@ static int sanitize_domain(const struct sbi_platform *plat,
 	/* Check next address and next mode*/
 	if (!sbi_domain_check_addr(dom, dom->next_addr, dom->next_mode,
 				   SBI_DOMAIN_EXECUTE)) {
-		sbi_printf("%s: %s next booting stage address 0x%lx can't "
+		sbi_printf("%s: %s next booting stage addres 0x%lx can't "
 			   "execute\n", __func__, dom->name, dom->next_addr);
 		return SBI_EINVAL;
 	}
@@ -331,7 +329,11 @@ void sbi_domain_dump(const struct sbi_domain *dom, const char *suffix)
 		rend = (reg->order < __riscv_xlen) ?
 			rstart + ((1UL << reg->order) - 1) : -1UL;

-		sbi_printf("Domain%d Region%02d    %s: 0x%" PRILX "-0x%" PRILX " ",
+#if __riscv_xlen == 32
+		sbi_printf("Domain%d Region%02d    %s: 0x%08lx-0x%08lx ",
+#else
+		sbi_printf("Domain%d Region%02d    %s: 0x%016lx-0x%016lx ",
+#endif
 			   dom->index, i, suffix, rstart, rend);

 		k = 0;
@@ -350,10 +352,18 @@ void sbi_domain_dump(const struct sbi_domain *dom, const char *suffix)
 		i++;
 	}

-	sbi_printf("Domain%d Next Address%s: 0x%" PRILX "\n",
+#if __riscv_xlen == 32
+	sbi_printf("Domain%d Next Address%s: 0x%08lx\n",
+#else
+	sbi_printf("Domain%d Next Address%s: 0x%016lx\n",
+#endif
 		   dom->index, suffix, dom->next_addr);

-	sbi_printf("Domain%d Next Arg1   %s: 0x%" PRILX "\n",
+#if __riscv_xlen == 32
+	sbi_printf("Domain%d Next Arg1   %s: 0x%08lx\n",
+#else
+	sbi_printf("Domain%d Next Arg1   %s: 0x%016lx\n",
+#endif
 		   dom->index, suffix, dom->next_arg1);

 	sbi_printf("Domain%d Next Mode   %s: ", dom->index, suffix);
@@ -374,6 +384,8 @@ void sbi_domain_dump(const struct sbi_domain *dom, const char *suffix)

 	sbi_printf("Domain%d SysReset    %s: %s\n",
 		   dom->index, suffix, (dom->system_reset_allowed) ? "yes" : "no");
+	sbi_printf("Domain%d SysSuspend  %s: %s\n",
+		   dom->index, suffix, (dom->system_suspend_allowed) ? "yes" : "no");
 }

 void sbi_domain_dump_all(const char *suffix)
@@ -474,12 +486,8 @@ int sbi_domain_root_add_memregion(const struct sbi_domain_memregion *reg)

 	/* Check for conflicts */
 	sbi_domain_for_each_memregion(&root, nreg) {
-		if (is_region_conflict(reg, nreg)) {
-			sbi_printf("%s: is_region_conflict check failed"
-			" 0x%lx conflicts existing 0x%lx\n", __func__,
-				   reg->base, nreg->base);
-			return SBI_EALREADY;
-		}
+		if (is_region_conflict(reg, nreg))
+			return SBI_EINVAL;
 	}

 	/* Append the memregion to root memregions */
@@ -506,8 +514,7 @@ int sbi_domain_root_add_memregion(const struct sbi_domain_memregion *reg)
 			if (!nreg1->order)
 				continue;

-			if (!(nreg->base & (BIT(nreg->order + 1) - 1)) &&
-			    (nreg->base + BIT(nreg->order)) == nreg1->base &&
+			if ((nreg->base + BIT(nreg->order)) == nreg1->base &&
 			    nreg->order == nreg1->order &&
 			    nreg->flags == nreg1->flags) {
 				nreg->order++;
@@ -525,33 +532,6 @@ int sbi_domain_root_add_memregion(const struct sbi_domain_memregion *reg)
 	return 0;
 }

-int sbi_domain_root_add_memrange(unsigned long addr, unsigned long size,
-			   unsigned long align, unsigned long region_flags)
-{
-	int rc;
-	unsigned long pos, end, rsize;
-	struct sbi_domain_memregion reg;
-
-	pos = addr;
-	end = addr + size;
-	while (pos < end) {
-		rsize = pos & (align - 1);
-		if (rsize)
-			rsize = 1UL << sbi_ffs(pos);
-		else
-			rsize = ((end - pos) < align) ?
-				(end - pos) : align;
-
-		sbi_domain_memregion_init(pos, rsize, region_flags, &reg);
-		rc = sbi_domain_root_add_memregion(&reg);
-		if (rc)
-			return rc;
-		pos += rsize;
-	}
-
-	return 0;
-}
-
 int sbi_domain_finalize(struct sbi_scratch *scratch, u32 cold_hartid)
 {
 	int rc;
--- a/lib/sbi/sbi_ecall.c
+++ b/lib/sbi/sbi_ecall.c
@@ -13,9 +13,6 @@
 #include <sbi/sbi_error.h>
 #include <sbi/sbi_trap.h>

-extern struct sbi_ecall_extension *sbi_ecall_exts[];
-extern unsigned long sbi_ecall_exts_size;
-
 u16 sbi_ecall_version_major(void)
 {
 	return SBI_ECALL_VERSION_MAJOR;
@@ -147,15 +144,35 @@ int sbi_ecall_handler(struct sbi_trap_regs *regs)
 int sbi_ecall_init(void)
 {
 	int ret;
-	struct sbi_ecall_extension *ext;
-	unsigned long i;

-	for (i = 0; i < sbi_ecall_exts_size; i++) {
-		ext = sbi_ecall_exts[i];
-		ret = sbi_ecall_register_extension(ext);
-		if (ret)
-			return ret;
-	}
+	/* The order of below registrations is performance optimized */
+	ret = sbi_ecall_register_extension(&ecall_time);
+	if (ret)
+		return ret;
+	ret = sbi_ecall_register_extension(&ecall_rfence);
+	if (ret)
+		return ret;
+	ret = sbi_ecall_register_extension(&ecall_ipi);
+	if (ret)
+		return ret;
+	ret = sbi_ecall_register_extension(&ecall_base);
+	if (ret)
+		return ret;
+	ret = sbi_ecall_register_extension(&ecall_hsm);
+	if (ret)
+		return ret;
+	ret = sbi_ecall_register_extension(&ecall_srst);
+	if (ret)
+		return ret;
+	ret = sbi_ecall_register_extension(&ecall_legacy);
+	if (ret)
+		return ret;
+	ret = sbi_ecall_register_extension(&ecall_vendor);
+	if (ret)
+		return ret;
+	ret = sbi_ecall_register_extension(&ecall_susp);
+	if (ret)
+		return ret;

 	return 0;
 }
--- a/lib/sbi/sbi_ecall_base.c
+++ b/lib/sbi/sbi_ecall_base.c
@@ -14,6 +14,7 @@
 #include <sbi/sbi_trap.h>
 #include <sbi/sbi_version.h>
 #include <sbi/riscv_asm.h>
+#include <sbi/riscv_io.h>

 static int sbi_ecall_base_probe(unsigned long extid, unsigned long *out_val)
 {
@@ -32,6 +33,41 @@ static int sbi_ecall_base_probe(unsigned long extid, unsigned long *out_val)
 	return 0;
 }

+#define SEC_SYS_BASE (0x020B0000)
+static int sbi_ecall_base_rst_c906l(void)
+{
+	unsigned int value;
+
+	value = readl((void *)0x3003024);
+	writel((value & (~(1 << 6))), (void *)0x3003024);
+
+	return 0;
+}
+
+static int sbi_ecall_base_unrst_c906l(const unsigned long address)
+{
+	unsigned int value;
+
+	value = readl((void *)SEC_SYS_BASE + 0x04);
+	writel((value | (1 << 13)), (void *)SEC_SYS_BASE + 0x04);
+	writel(address, (void *)SEC_SYS_BASE + 0x20);
+	writel((address >> 32), (void *)SEC_SYS_BASE + 0x24);
+
+	value = readl((void *)0x3003024);
+	writel((value | (1 << 6)), (void *)0x3003024);
+
+	return 0;
+}
+
+static int sbi_ecall_base_reset_c906l(const unsigned long address)
+{
+	sbi_ecall_base_rst_c906l();
+
+	sbi_ecall_base_unrst_c906l(address);
+
+	return 0;
+}
+
 static int sbi_ecall_base_handler(unsigned long extid, unsigned long funcid,
 				  const struct sbi_trap_regs *regs,
 				  unsigned long *out_val,
@@ -65,6 +101,16 @@ static int sbi_ecall_base_handler(unsigned long extid, unsigned long funcid,
 	case SBI_EXT_BASE_PROBE_EXT:
 		ret = sbi_ecall_base_probe(regs->a0, out_val);
 		break;
+	case SBI_EXT_BASE_RESET_C906L:
+		ret = sbi_ecall_base_reset_c906l(regs->a0);
+		*out_val = regs->a0;
+		break;
+	case SBI_EXT_BASE_RST_C906L:
+		ret = sbi_ecall_base_rst_c906l();
+		break;
+	case SBI_EXT_BASE_UNRST_C906L:
+		ret = sbi_ecall_base_unrst_c906l(regs->a0);
+		break;
 	default:
 		ret = SBI_ENOTSUPP;
 	}
--- a/lib/sbi/sbi_ecall_exts.carray
+++ b/lib/sbi/sbi_ecall_exts.carray
@@ -1,3 +0,0 @@
-HEADER: sbi/sbi_ecall.h
-TYPE: struct sbi_ecall_extension
-NAME: sbi_ecall_exts
--- a/lib/sbi/sbi_ecall_ipi.c
+++ b/lib/sbi/sbi_ecall_ipi.c
@@ -1,36 +0,0 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2020 Western Digital Corporation or its affiliates.
- *
- * Authors:
- *   Anup Patel <anup.patel@wdc.com>
- *   Atish Patra <atish.patra@wdc.com>
- */
-
-#include <sbi/sbi_error.h>
-#include <sbi/sbi_ecall.h>
-#include <sbi/sbi_ecall_interface.h>
-#include <sbi/sbi_trap.h>
-#include <sbi/sbi_ipi.h>
-
-static int sbi_ecall_ipi_handler(unsigned long extid, unsigned long funcid,
-				 const struct sbi_trap_regs *regs,
-				 unsigned long *out_val,
-				 struct sbi_trap_info *out_trap)
-{
-	int ret = 0;
-
-	if (funcid == SBI_EXT_IPI_SEND_IPI)
-		ret = sbi_ipi_send_smode(regs->a0, regs->a1);
-	else
-		ret = SBI_ENOTSUPP;
-
-	return ret;
-}
-
-struct sbi_ecall_extension ecall_ipi = {
-	.extid_start = SBI_EXT_IPI,
-	.extid_end = SBI_EXT_IPI,
-	.handle = sbi_ecall_ipi_handler,
-};
--- a/lib/sbi/sbi_ecall_pmu.c
+++ b/lib/sbi/sbi_ecall_pmu.c
@@ -1,88 +0,0 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2021 Western Digital Corporation or its affiliates.
- *
- * Authors:
- *   Atish Patra <atish.patra@wdc.com>
- */
-
-#include <sbi/sbi_ecall.h>
-#include <sbi/sbi_ecall_interface.h>
-#include <sbi/sbi_error.h>
-#include <sbi/sbi_hart.h>
-#include <sbi/sbi_trap.h>
-#include <sbi/sbi_version.h>
-#include <sbi/sbi_pmu.h>
-#include <sbi/sbi_scratch.h>
-#include <sbi/riscv_asm.h>
-
-static int sbi_ecall_pmu_handler(unsigned long extid, unsigned long funcid,
-				 const struct sbi_trap_regs *regs,
-				 unsigned long *out_val,
-				 struct sbi_trap_info *out_trap)
-{
-	int ret = 0;
-	uint64_t temp;
-
-	switch (funcid) {
-	case SBI_EXT_PMU_NUM_COUNTERS:
-		ret = sbi_pmu_num_ctr();
-		if (ret >= 0) {
-			*out_val = ret;
-			ret = 0;
-		}
-		break;
-	case SBI_EXT_PMU_COUNTER_GET_INFO:
-		ret = sbi_pmu_ctr_get_info(regs->a0, out_val);
-		break;
-	case SBI_EXT_PMU_COUNTER_CFG_MATCH:
-#if __riscv_xlen == 32
-		temp = ((uint64_t)regs->a5 << 32) | regs->a4;
-#else
-		temp = regs->a4;
-#endif
-		ret = sbi_pmu_ctr_cfg_match(regs->a0, regs->a1, regs->a2,
-					    regs->a3, temp);
-		if (ret >= 0) {
-			*out_val = ret;
-			ret = 0;
-		}
-
-		break;
-	case SBI_EXT_PMU_COUNTER_FW_READ:
-		ret = sbi_pmu_ctr_fw_read(regs->a0, &temp);
-		*out_val = temp;
-		break;
-	case SBI_EXT_PMU_COUNTER_START:
-
-#if __riscv_xlen == 32
-		temp = ((uint64_t)regs->a4 << 32) | regs->a3;
-#else
-		temp = regs->a3;
-#endif
-		ret = sbi_pmu_ctr_start(regs->a0, regs->a1, regs->a2, temp);
-		break;
-	case SBI_EXT_PMU_COUNTER_STOP:
-		ret = sbi_pmu_ctr_stop(regs->a0, regs->a1, regs->a2);
-		break;
-	default:
-		ret = SBI_ENOTSUPP;
-	};
-
-	return ret;
-}
-
-static int sbi_ecall_pmu_probe(unsigned long extid, unsigned long *out_val)
-{
-	/* PMU extension is always enabled */
-	*out_val = 1;
-	return 0;
-}
-
-struct sbi_ecall_extension ecall_pmu = {
-	.extid_start = SBI_EXT_PMU,
-	.extid_end = SBI_EXT_PMU,
-	.handle = sbi_ecall_pmu_handler,
-	.probe = sbi_ecall_pmu_probe,
-};
--- a/lib/sbi/sbi_ecall_replace.c
+++ b/lib/sbi/sbi_ecall_replace.c
@@ -9,11 +9,40 @@
 */

 #include <sbi/riscv_asm.h>
-#include <sbi/sbi_error.h>
 #include <sbi/sbi_ecall.h>
 #include <sbi/sbi_ecall_interface.h>
-#include <sbi/sbi_trap.h>
+#include <sbi/sbi_error.h>
+#include <sbi/sbi_hart.h>
+#include <sbi/sbi_ipi.h>
+#include <sbi/sbi_system.h>
+#include <sbi/sbi_timer.h>
 #include <sbi/sbi_tlb.h>
+#include <sbi/sbi_trap.h>
+
+static int sbi_ecall_time_handler(unsigned long extid, unsigned long funcid,
+				  const struct sbi_trap_regs *regs,
+				  unsigned long *out_val,
+				  struct sbi_trap_info *out_trap)
+{
+	int ret = 0;
+
+	if (funcid == SBI_EXT_TIME_SET_TIMER) {
+#if __riscv_xlen == 32
+		sbi_timer_event_start((((u64)regs->a1 << 32) | (u64)regs->a0));
+#else
+		sbi_timer_event_start((u64)regs->a0);
+#endif
+	} else
+		ret = SBI_ENOTSUPP;
+
+	return ret;
+}
+
+struct sbi_ecall_extension ecall_time = {
+	.extid_start = SBI_EXT_TIME,
+	.extid_end = SBI_EXT_TIME,
+	.handle = sbi_ecall_time_handler,
+};

 static int sbi_ecall_rfence_handler(unsigned long extid, unsigned long funcid,
 				    const struct sbi_trap_regs *regs,
@@ -25,8 +54,8 @@ static int sbi_ecall_rfence_handler(unsigned long extid, unsigned long funcid,
 	struct sbi_tlb_info tlb_info;
 	u32 source_hart = current_hartid();

-	if (funcid >= SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID &&
-	    funcid <= SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA)
+	if (funcid >= SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA &&
+	    funcid <= SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID)
 		if (!misa_extension('H'))
 			return SBI_ENOTSUPP;

@@ -84,3 +113,84 @@ struct sbi_ecall_extension ecall_rfence = {
 	.extid_end = SBI_EXT_RFENCE,
 	.handle = sbi_ecall_rfence_handler,
 };
+
+static int sbi_ecall_ipi_handler(unsigned long extid, unsigned long funcid,
+				 const struct sbi_trap_regs *regs,
+				 unsigned long *out_val,
+				 struct sbi_trap_info *out_trap)
+{
+	int ret = 0;
+
+	if (funcid == SBI_EXT_IPI_SEND_IPI)
+		ret = sbi_ipi_send_smode(regs->a0, regs->a1);
+	else
+		ret = SBI_ENOTSUPP;
+
+	return ret;
+}
+
+struct sbi_ecall_extension ecall_ipi = {
+	.extid_start = SBI_EXT_IPI,
+	.extid_end = SBI_EXT_IPI,
+	.handle = sbi_ecall_ipi_handler,
+};
+
+static int sbi_ecall_srst_handler(unsigned long extid, unsigned long funcid,
+				  const struct sbi_trap_regs *regs,
+				  unsigned long *out_val,
+				  struct sbi_trap_info *out_trap)
+{
+	if (funcid == SBI_EXT_SRST_RESET) {
+		if ((((u32)-1U) <= ((u64)regs->a0)) ||
+		    (((u32)-1U) <= ((u64)regs->a1)))
+			return SBI_EINVAL;
+
+		switch (regs->a0) {
+		case SBI_SRST_RESET_TYPE_SHUTDOWN:
+		case SBI_SRST_RESET_TYPE_COLD_REBOOT:
+		case SBI_SRST_RESET_TYPE_WARM_REBOOT:
+			break;
+		default:
+			return SBI_ENOTSUPP;
+		}
+
+		switch (regs->a1) {
+		case SBI_SRST_RESET_REASON_NONE:
+		case SBI_SRST_RESET_REASON_SYSFAIL:
+			break;
+		default:
+			return SBI_ENOTSUPP;
+		}
+
+		if (sbi_system_reset_supported(regs->a0, regs->a1))
+			sbi_system_reset(regs->a0, regs->a1);
+	}
+
+	return SBI_ENOTSUPP;
+}
+
+static int sbi_ecall_srst_probe(unsigned long extid, unsigned long *out_val)
+{
+	u32 type, count = 0;
+
+	/*
+	 * At least one standard reset types should be supported by
+	 * the platform for SBI SRST extension to be usable.
+	 */
+
+	for (type = 0; type <= SBI_SRST_RESET_TYPE_LAST; type++) {
+		if (sbi_system_reset_supported(type,
+					SBI_SRST_RESET_REASON_NONE))
+			count++;
+	}
+
+	*out_val = (count) ? 1 : 0;
+	return 0;
+}
+
+struct sbi_ecall_extension ecall_srst = {
+	.extid_start = SBI_EXT_SRST,
+	.extid_end = SBI_EXT_SRST,
+	.handle = sbi_ecall_srst_handler,
+	.probe = sbi_ecall_srst_probe,
+};
--- a/lib/sbi/sbi_ecall_srst.c
+++ b/lib/sbi/sbi_ecall_srst.c
@@ -1,75 +0,0 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2020 Western Digital Corporation or its affiliates.
- *
- * Authors:
- *   Anup Patel <anup.patel@wdc.com>
- *   Atish Patra <atish.patra@wdc.com>
- */
-
-#include <sbi/sbi_error.h>
-#include <sbi/sbi_ecall.h>
-#include <sbi/sbi_ecall_interface.h>
-#include <sbi/sbi_trap.h>
-#include <sbi/sbi_system.h>
-
-static int sbi_ecall_srst_handler(unsigned long extid, unsigned long funcid,
-				  const struct sbi_trap_regs *regs,
-				  unsigned long *out_val,
-				  struct sbi_trap_info *out_trap)
-{
-	if (funcid == SBI_EXT_SRST_RESET) {
-		if ((((u32)-1U) <= ((u64)regs->a0)) ||
-		    (((u32)-1U) <= ((u64)regs->a1)))
-			return SBI_EINVAL;
-
-		switch (regs->a0) {
-		case SBI_SRST_RESET_TYPE_SHUTDOWN:
-		case SBI_SRST_RESET_TYPE_COLD_REBOOT:
-		case SBI_SRST_RESET_TYPE_WARM_REBOOT:
-			break;
-		default:
-			return SBI_EINVAL;
-		}
-
-		switch (regs->a1) {
-		case SBI_SRST_RESET_REASON_NONE:
-		case SBI_SRST_RESET_REASON_SYSFAIL:
-			break;
-		default:
-			return SBI_EINVAL;
-		}
-
-		if (sbi_system_reset_supported(regs->a0, regs->a1))
-			sbi_system_reset(regs->a0, regs->a1);
-	}
-
-	return SBI_ENOTSUPP;
-}
-
-static int sbi_ecall_srst_probe(unsigned long extid, unsigned long *out_val)
-{
-	u32 type, count = 0;
-
-	/*
-	 * At least one standard reset types should be supported by
-	 * the platform for SBI SRST extension to be usable.
-	 */
-
-	for (type = 0; type <= SBI_SRST_RESET_TYPE_LAST; type++) {
-		if (sbi_system_reset_supported(type,
-					SBI_SRST_RESET_REASON_NONE))
-			count++;
-	}
-
-	*out_val = (count) ? 1 : 0;
-	return 0;
-}
-
-struct sbi_ecall_extension ecall_srst = {
-	.extid_start = SBI_EXT_SRST,
-	.extid_end = SBI_EXT_SRST,
-	.handle = sbi_ecall_srst_handler,
-	.probe = sbi_ecall_srst_probe,
-};
--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
drholy	f879119605	Обновить platform/generic/cvitek_riscv.c	2026-02-11 02:19:45 +07:00
drholy	aedef73d12	Обновить platform/generic/cvitek_riscv.c	2026-02-11 01:41:03 +07:00
drholy	92ee61dae4	Обновить platform/generic/cvitek_riscv.c	2026-02-11 01:34:56 +07:00
sophgo-forum-service	6766e9cc96	opensbi: weekly rls 2025.01.24 daa470, [fix](opensbi): add rls_info.txt b21a54, [test](opensbi): opensbi tailoring (time optimizing) 6ff231, [fix](str): fix riscv suspend section which do not use varivales and functions beyond syspend section.	2025-01-24 14:50:56 +08:00
sophgo-forum-service	3b045ae374	opensbi: weekly rls 2025.01.10 daa470, [fix](opensbi): add rls_info.txt b21a54, [test](opensbi): opensbi tailoring (time optimizing) 6ff231, [fix](str): fix riscv suspend section which do not use varivales and functions beyond syspend section. Change-Id: I8c6e7698b475b2d14c02308121f621dafe9b9e36	2025-01-13 16:32:03 +08:00
sophgo-forum-service	fffb4754ee	opensbi: weekly rls 2024.10.14 -0f5edb, [fix](str):fix chip id miss and fix suspend bug on rtc -a068cd, [fix](str): refine rtc suspend/resume process Change-Id: Ice28701d616192d7d6a6f13621d739dd07424571	2024-10-14 19:27:45 +08:00
sophgo-forum-service	ab9b8f8d10	opensbi: weekly rls 2024.07.20 -0aa741, support cv181x/cv180x suspend to ram. Change-Id: I64dcb0ff942aa7238a88ef3bd1da2c67f5d089b4	2024-07-20 21:40:47 +08:00
sophgo-forum-service	3fd99912a6	opensbi: weekly rls 2024.06.6 -2da720, Add rst/unrst/reset c906l ecall. Change-Id: Id1b2de0c5cb4607d46fd4397a78e77109790cc49	2024-06-06 15:17:01 +08:00
sophgo-forum-service	216793f112	(opensbi): Init branch sg200x-dev Change-Id: If4dd4f7d55a714cff21c4ead4376a4137ee03330	2024-02-14 16:36:52 +08:00
sophgo-forum-service	ba54b0038e	note: sync patch from T-Head. https://github.com/T-head-Semi/opensbi commit: 89182b257c8798e15e4c685c1af0c2862d528d2a	2024-02-14 16:31:42 +08:00
Guo Ren	ba85a8ec52	platform/generic/platform.c: Support qemu poweroff Signed-off-by: Guo Ren <guoren@linux.alibaba.com>	2024-01-10 17:35:55 +08:00
Guo Ren	885df4577a	utils: irqchip: Fixup priority init overwrite zero Signed-off-by: Guo Ren <guoren@linux.alibaba.com>	2024-01-10 17:35:47 +08:00
Guo Ren	f67338cc74	thead PMU supported Signed-off-by: Guo Ren <guoren@linux.alibaba.com>	2024-01-10 17:35:39 +08:00