Обновить platform/generic/cvitek_riscv.c

daa470, [fix](opensbi): add rls_info.txt
b21a54, [test](opensbi): opensbi tailoring (time optimizing)
6ff231, [fix](str): fix riscv suspend section which do not use varivales and functions beyond syspend section.

.clang-format

@@ -1,16 +0,0 @@
-AlignConsecutiveAssignments: true
-AlignEscapedNewlines: Left
-AlignTrailingComments: true
-AllowShortFunctionsOnASingleLine: None
-BraceWrapping:
-  AfterFunction: true
-BreakBeforeBraces: Custom
-BreakStringLiterals: false
-ContinuationIndentWidth: 8
-Cpp11BracedListStyle: false
-IndentWidth: 8
-ReflowComments: false
-SortIncludes: false
-SpacesInContainerLiterals: false
-TabWidth: 8
-UseTab: Always

Makefile

@@ -94,6 +94,8 @@ DTC		=	dtc
 
 # Guess the compillers xlen
 OPENSBI_CC_XLEN := $(shell TMP=`$(CC) -dumpmachine | sed 's/riscv\([0-9][0-9]\).*/\1/'`; echo $${TMP})
+OPENSBI_CC_ABI := $(shell TMP=`$(CC) -v 2>&1 | sed -n 's/.*\(with\-abi=\([a-zA-Z0-9]*\)\).*/\2/p'`; echo $${TMP})
+OPENSBI_CC_ISA := $(shell TMP=`$(CC) -v 2>&1 | sed -n 's/.*\(with\-arch=\([a-zA-Z0-9]*\)\).*/\2/p'`; echo $${TMP})
 
 # Setup platform XLEN
 ifndef PLATFORM_RISCV_XLEN
@@ -130,7 +132,6 @@ libsbi-objs-path-y=$(foreach obj,$(libsbi-objs-y),$(build_dir)/lib/sbi/$(obj))
 libsbiutils-objs-path-y=$(foreach obj,$(libsbiutils-objs-y),$(build_dir)/lib/utils/$(obj))
 ifdef PLATFORM
 platform-objs-path-y=$(foreach obj,$(platform-objs-y),$(platform_build_dir)/$(obj))
-platform-dtb-path-y=$(foreach obj,$(platform-dtb-y),$(platform_build_dir)/$(obj))
 firmware-bins-path-y=$(foreach bin,$(firmware-bins-y),$(platform_build_dir)/firmware/$(bin))
 endif
 firmware-elfs-path-y=$(firmware-bins-path-y:.bin=.elf)
@@ -142,16 +143,38 @@ deps-y+=$(libsbi-objs-path-y:.o=.dep)
 deps-y+=$(libsbiutils-objs-path-y:.o=.dep)
 deps-y+=$(firmware-objs-path-y:.o=.dep)
 
+ifeq (,$(wildcard ${PM_SRAM_BIN_PATH}))
+	ifeq (${CHIP_ARCH},CV180X)
+		PM_SRAM_BIN_PATH=${OPENSBI_PATH}/pm_default_cv180x.bin
+	endif
+	ifeq (${CHIP_ARCH},CV181X)
+		PM_SRAM_BIN_PATH=${OPENSBI_PATH}/pm_default_cv181x.bin
+	endif
+else
+ifeq ($(filter clean %clean clean%,$(MAKECMDGOALS)),)
+$(shell touch -c platform\generic\cvitek_riscv.c > /dev/null)
+endif
+endif
+$(info PM_SRAM_BIN_PATH is '${PM_SRAM_BIN_PATH}')
+
 # Setup platform ABI, ISA and Code Model
 ifndef PLATFORM_RISCV_ABI
-  ifeq ($(PLATFORM_RISCV_XLEN), 32)
-    PLATFORM_RISCV_ABI = ilp$(PLATFORM_RISCV_XLEN)
+  ifneq ($(PLATFORM_RISCV_TOOLCHAIN_DEFAULT), 1)
+    ifeq ($(PLATFORM_RISCV_XLEN), 32)
+      PLATFORM_RISCV_ABI = ilp$(PLATFORM_RISCV_XLEN)
+    else
+      PLATFORM_RISCV_ABI = lp$(PLATFORM_RISCV_XLEN)
+    endif
   else
-    PLATFORM_RISCV_ABI = lp$(PLATFORM_RISCV_XLEN)
+    PLATFORM_RISCV_ABI = $(OPENSBI_CC_ABI)
   endif
 endif
 ifndef PLATFORM_RISCV_ISA
-  PLATFORM_RISCV_ISA = rv$(PLATFORM_RISCV_XLEN)imafdc
+  ifneq ($(PLATFORM_RISCV_TOOLCHAIN_DEFAULT), 1)
+    PLATFORM_RISCV_ISA = rv$(PLATFORM_RISCV_XLEN)imafdc
+  else
+    PLATFORM_RISCV_ISA = $(OPENSBI_CC_ISA)
+  endif
 endif
 ifndef PLATFORM_RISCV_CODE_MODEL
   PLATFORM_RISCV_CODE_MODEL = medany
@@ -194,6 +217,14 @@ GENFLAGS	+=	$(libsbiutils-genflags-y)
 GENFLAGS	+=	$(platform-genflags-y)
 GENFLAGS	+=	$(firmware-genflags-y)
 
+define add_define
+    GENFLAGS	+=	-D$(1)$(if $(value $(1)),=$(value $(1)),)
+endef
+
+ifeq (${CONFIG_OPENSBI_FASTBOOT},y)
+$(eval $(call add_define,CONFIG_OPENSBI_FASTBOOT))
+endif
+
 CFLAGS		=	-g -Wall -Werror -ffreestanding -nostdlib -fno-strict-aliasing -O2
 CFLAGS		+=	-fno-omit-frame-pointer -fno-optimize-sibling-calls
 CFLAGS		+=	-mno-save-restore -mstrict-align
@@ -201,14 +232,21 @@ CFLAGS		+=	-mabi=$(PLATFORM_RISCV_ABI) -march=$(PLATFORM_RISCV_ISA)
 CFLAGS		+=	-mcmodel=$(PLATFORM_RISCV_CODE_MODEL)
 CFLAGS		+=	$(GENFLAGS)
 CFLAGS		+=	$(platform-cflags-y)
-CFLAGS		+=	$(firmware-cflags-y)
 CFLAGS		+=	-fno-pie -no-pie
+CFLAGS		+=	$(firmware-cflags-y)
+CFLAGS		+=	-DPM_SRAM_BIN_PATH=$(PM_SRAM_BIN_PATH)
+ifeq ($(CHIP_ARCH),CV180X)
+CFLAGS		+=	-DCONFIG_CV180X
+endif
+ifeq (${CHIP_ARCH},CV181X)
+CFLAGS		+=	-DCONFIG_CV181X
+endif
 
 CPPFLAGS	+=	$(GENFLAGS)
 CPPFLAGS	+=	$(platform-cppflags-y)
 CPPFLAGS	+=	$(firmware-cppflags-y)
 
-ASFLAGS		=	-g -Wall -nostdlib -D__ASSEMBLY__
+ASFLAGS		=	-g -Wall -nostdlib
 ASFLAGS		+=	-fno-omit-frame-pointer -fno-optimize-sibling-calls
 ASFLAGS		+=	-mno-save-restore -mstrict-align
 ASFLAGS		+=	-mabi=$(PLATFORM_RISCV_ABI) -march=$(PLATFORM_RISCV_ISA)
@@ -227,7 +265,7 @@ MERGEFLAGS	+=	-r
 MERGEFLAGS	+=	-b elf$(PLATFORM_RISCV_XLEN)-littleriscv
 MERGEFLAGS	+=	-m elf$(PLATFORM_RISCV_XLEN)lriscv
 
-DTCFLAGS	=	-O dtb
+DTSCPPFLAGS	=	$(CPPFLAGS) -nostdinc -nostdlib -fno-builtin -D__DTS__ -x assembler-with-cpp
 
 # Setup functions for compilation
 define dynamic_flags
@@ -289,13 +327,21 @@ compile_objcopy = $(CMD_PREFIX)mkdir -p `dirname $(1)`; \
 	     $(OBJCOPY) -S -O binary $(2) $(1)
 compile_dts = $(CMD_PREFIX)mkdir -p `dirname $(1)`; \
 	     echo " DTC       $(subst $(build_dir)/,,$(1))"; \
-	     $(DTC) $(DTCFLAGS) -o $(1) $(2)
+	     $(CPP) $(DTSCPPFLAGS) $(2) | $(DTC) -O dtb -i `dirname $(2)` -o $(1)
+compile_d2c = $(CMD_PREFIX)mkdir -p `dirname $(1)`; \
+	     echo " D2C       $(subst $(build_dir)/,,$(1))"; \
+	     $(if $($(2)-varalign-$(3)),$(eval D2C_ALIGN_BYTES := $($(2)-varalign-$(3))),$(eval D2C_ALIGN_BYTES := $(4))) \
+	     $(if $($(2)-varprefix-$(3)),$(eval D2C_NAME_PREFIX := $($(2)-varprefix-$(3))),$(eval D2C_NAME_PREFIX := $(5))) \
+	     $(if $($(2)-padding-$(3)),$(eval D2C_PADDING_BYTES := $($(2)-padding-$(3))),$(eval D2C_PADDING_BYTES := 0)) \
+	     $(src_dir)/scripts/d2c.sh -i $(6) -a $(D2C_ALIGN_BYTES) -p $(D2C_NAME_PREFIX) -t $(D2C_PADDING_BYTES) > $(1)
+compile_gen_dep = $(CMD_PREFIX)mkdir -p `dirname $(1)`; \
+	     echo " GEN-DEP   $(subst $(build_dir)/,,$(1))"; \
+	     echo "$(1:.dep=$(2)): $(3)" >> $(1)
 
 targets-y  = $(build_dir)/lib/libsbi.a
 targets-y  += $(build_dir)/lib/libsbiutils.a
 ifdef PLATFORM
 targets-y += $(platform_build_dir)/lib/libplatsbi.a
-targets-y += $(platform-dtb-path-y)
 endif
 targets-y += $(firmware-bins-path-y)
 
@@ -306,15 +352,6 @@ all: $(targets-y)
 # Preserve all intermediate files
 .SECONDARY:
 
-$(build_dir)/%.bin: $(build_dir)/%.elf
-	$(call compile_objcopy,$@,$<)
-
-$(build_dir)/%.elf: $(build_dir)/%.o $(build_dir)/%.elf.ld $(platform_build_dir)/lib/libplatsbi.a
-	$(call compile_elf,$@,$@.ld,$< $(platform_build_dir)/lib/libplatsbi.a)
-
-$(platform_build_dir)/%.ld: $(src_dir)/%.ldS
-	$(call compile_cpp,$@,$<)
-
 $(build_dir)/lib/libsbi.a: $(libsbi-objs-path-y)
 	$(call compile_ar,$@,$^)
 
@@ -336,18 +373,41 @@ $(build_dir)/%.dep: $(src_dir)/%.S
 $(build_dir)/%.o: $(src_dir)/%.S
 	$(call compile_as,$@,$<)
 
+$(platform_build_dir)/%.bin: $(platform_build_dir)/%.elf
+	$(call compile_objcopy,$@,$<)
+
+$(platform_build_dir)/%.elf: $(platform_build_dir)/%.o $(platform_build_dir)/%.elf.ld $(platform_build_dir)/lib/libplatsbi.a
+	$(call compile_elf,$@,$@.ld,$< $(platform_build_dir)/lib/libplatsbi.a)
+
+$(platform_build_dir)/%.ld: $(src_dir)/%.ldS
+	$(call compile_cpp,$@,$<)
+
 $(platform_build_dir)/%.dep: $(platform_src_dir)/%.c
 	$(call compile_cc_dep,$@,$<)
 
 $(platform_build_dir)/%.o: $(platform_src_dir)/%.c
 	$(call compile_cc,$@,$<)
 
+$(platform_build_dir)/%.o: $(platform_build_dir)/%.c
+	$(call compile_cc,$@,$<)
+
 $(platform_build_dir)/%.dep: $(platform_src_dir)/%.S
 	$(call compile_as_dep,$@,$<)
 
 $(platform_build_dir)/%.o: $(platform_src_dir)/%.S
 	$(call compile_as,$@,$<)
 
+$(platform_build_dir)/%.dep: $(platform_src_dir)/%.dts
+	$(call compile_gen_dep,$@,.dtb,$<)
+	$(call compile_gen_dep,$@,.c,$(@:.dep=.dtb))
+	$(call compile_gen_dep,$@,.o,$(@:.dep=.c))
+
+$(platform_build_dir)/%.c: $(platform_build_dir)/%.dtb
+	$(call compile_d2c,$@,platform,$(subst .dtb,.o,$(subst /,-,$(subst $(platform_build_dir)/,,$<))),16,dt,$<)
+
+$(platform_build_dir)/%.dtb: $(platform_src_dir)/%.dts
+	$(call compile_dts,$@,$<)
+
 $(platform_build_dir)/%.dep: $(src_dir)/%.c
 	$(call compile_cc_dep,$@,$<)
 
@@ -360,9 +420,6 @@ $(platform_build_dir)/%.dep: $(src_dir)/%.S
 $(platform_build_dir)/%.o: $(src_dir)/%.S
 	$(call compile_as,$@,$<)
 
-$(build_dir)/%.dtb: $(src_dir)/%.dts
-	$(call compile_dts,$@,$<)
-
 # Rule for "make docs"
 $(build_dir)/docs/latex/refman.pdf: $(build_dir)/docs/latex/refman.tex
 	$(CMD_PREFIX)mkdir -p $(build_dir)/docs
@@ -446,6 +503,8 @@ clean:
 	$(CMD_PREFIX)find $(build_dir) -type f -name "*.elf" -exec rm -rf {} +
 	$(if $(V), @echo " RM        $(build_dir)/*.bin")
 	$(CMD_PREFIX)find $(build_dir) -type f -name "*.bin" -exec rm -rf {} +
+	$(if $(V), @echo " RM        $(build_dir)/*.dtb")
+	$(CMD_PREFIX)find $(build_dir) -type f -name "*.dtb" -exec rm -rf {} +
 
 # Rule for "make distclean"
 .PHONY: distclean

README.md

@@ -1,9 +1,41 @@
-Copyright (c) 2019 Western Digital Corporation or its affiliates
-and other contributors.
-
 RISC-V Open Source Supervisor Binary Interface (OpenSBI)
 ========================================================
 
+Copyright and License
+---------------------
+
+The OpenSBI project is copyright (c) 2019 Western Digital Corporation
+or its affiliates and other contributors.
+
+It is distributed under the terms of the BSD 2-clause license
+("Simplified BSD License" or "FreeBSD License", SPDX: *BSD-2-Clause*).
+A copy of this license with OpenSBI copyright can be found in the file
+[COPYING.BSD].
+
+All source files in OpenSBI contain the 2-Clause BSD license SPDX short
+identifier in place of the full license text.
+
+```
+SPDX-License-Identifier:    BSD-2-Clause
+```
+
+This enables machine processing of license information based on the SPDX
+License Identifiers that are available on the [SPDX] web site.
+
+OpenSBI source code also contains code reused from other projects as listed
+below. The original license text of these projects is included in the source
+files where the reused code is present.
+
+* The libfdt source code is disjunctively dual licensed
+  (GPL-2.0+ OR BSD-2-Clause). Some of this project code is used in OpenSBI
+  under the terms of the BSD 2-Clause license. Any contributions to this
+  code must be made under the terms of both licenses.
+
+See also the [third party notices] file for more information.
+
+Introduction
+------------
+
 The **RISC-V Supervisor Binary Interface (SBI)** is the recommended interface
 between:
 
@@ -13,7 +45,7 @@ between:
    executing in VS-mode.
 
 The *RISC-V SBI specification* is maintained as an independent project by the
-RISC-V Foundation on [Github] (https://github.com/riscv/riscv-sbi-doc).
+RISC-V Foundation on [Github].
 
 The goal of the OpenSBI project is to provide an open-source reference
 implementation of the RISC-V SBI specifications for platform-specific firmwares
@@ -37,7 +69,7 @@ platform-dependent hardware manipulation functions. For all supported platforms,
 OpenSBI also provides several runtime firmware examples built using the platform
 *libplatsbi.a*. These example firmwares can be used to replace the legacy
 *riscv-pk* bootloader (aka BBL) and enable the use of well-known bootloaders
-such as [U-Boot] (https://git.denx.de/u-boot.git).
+such as [U-Boot].
 
 Supported SBI version
 ---------------------
@@ -65,8 +97,7 @@ Required Toolchain
 
 OpenSBI can be compiled natively or cross-compiled on a x86 host. For
 cross-compilation, you can build your own toolchain or just download
-a prebuilt one from the
-[Bootlin toolchain repository] (https://toolchains.bootlin.com/).
+a prebuilt one from the [Bootlin toolchain repository].
 
 Please note that only a 64-bit version of the toolchain is available in
 the Bootlin toolchain repository for now.
@@ -115,7 +146,7 @@ line, the platform-specific static library *libplatsbi.a* and firmware examples
 are built for the platform *<platform_subdir>* present in the directory
 *platform* in the OpenSBI top directory. For example, to compile the platform
 library and the firmware examples for the QEMU RISC-V *virt* machine,
-*<platform_subdir>* should be *qemu/virt*.
+*<platform_subdir>* should be *generic*.
 
 To build *libsbi.a*, *libplatsbi.a* and the firmware for one of the supported
 platforms, run:
@@ -171,35 +202,6 @@ export PLATFORM_RISCV_XLEN=32
 
 will generate 32-bit OpenSBI images. And vice vesa.
 
-License
--------
-
-OpenSBI is distributed under the terms of the BSD 2-clause license
-("Simplified BSD License" or "FreeBSD License", SPDX: *BSD-2-Clause*).
-A copy of this license with OpenSBI copyright can be found in the file
-[COPYING.BSD].
-
-All source files in OpenSBI contain the 2-Clause BSD license SPDX short
-identifier in place of the full license text.
-
-```
-SPDX-License-Identifier:    BSD-2-Clause
-```
-
-This enables machine processing of license information based on the SPDX
-License Identifiers that are available on the [SPDX] web site.
-
-OpenSBI source code also contains code reused from other projects as listed
-below. The original license text of these projects is included in the source
-files where the reused code is present.
-
-* The libfdt source code is disjunctively dual licensed
-  (GPL-2.0+ OR BSD-2-Clause). Some of this project code is used in OpenSBI
-  under the terms of the BSD 2-Clause license. Any contributions to this
-  code must be made under the terms of both licenses.
-
-See also the [third party notices] file for more information.
-
 Contributing to OpenSBI
 -----------------------
 
@@ -218,10 +220,13 @@ Detailed documentation of various aspects of OpenSBI can be found under the
 
 * [Contribution Guideline]: Guideline for contributing code to OpenSBI project
 * [Library Usage]: API documentation of OpenSBI static library *libsbi.a*
+* [Platform Requirements]: Requirements for using OpenSBI on a platform
 * [Platform Support Guide]: Guideline for implementing support for new platforms
 * [Platform Documentation]: Documentation of the platforms currently supported.
 * [Firmware Documentation]: Documentation for the different types of firmware
   examples build supported by OpenSBI.
+* [Domain Support]: Documentation for the OpenSBI domain support which helps
+  users achieve system-level partitioning using OpenSBI.
 
 OpenSBI source code is also well documented. For source level documentation,
 doxygen style is used. Please refer to the [Doxygen manual] for details on this
@@ -265,14 +270,17 @@ make I=<install_directory> install_docs
 
 [Github]: https://github.com/riscv/riscv-sbi-doc
 [U-Boot]: https://www.denx.de/wiki/U-Boot/SourceCode
+[Bootlin toolchain repository]: https://toolchains.bootlin.com/
 [COPYING.BSD]: COPYING.BSD
 [SPDX]: http://spdx.org/licenses/
 [Contribution Guideline]: docs/contributing.md
 [Contributors List]: CONTRIBUTORS.md
 [Library Usage]: docs/library_usage.md
+[Platform Requirements]: docs/platform_requirements.md
 [Platform Support Guide]: docs/platform_guide.md
 [Platform Documentation]: docs/platform/platform.md
 [Firmware Documentation]: docs/firmware/fw.md
+[Domain Support]: docs/domain_support.md
 [Doxygen manual]: http://www.doxygen.nl/manual/index.html
 [Kendryte standalone SDK]: https://github.com/kendryte/kendryte-standalone-sdk
 [third party notices]: ThirdPartyNotices.md

docs/domain_support.md

@@ -0,0 +1,319 @@
+OpenSBI Domain Support
+======================
+
+An OpenSBI domain is a system-level partition (subset) of underlying hardware
+having it's own memory regions (RAM and MMIO devices) and HARTs. The OpenSBI
+will try to achieve secure isolation between domains using RISC-V platform
+features such as PMP, ePMP, IOPMP, SiFive Shield, etc.
+
+Important entities which help implement OpenSBI domain support are:
+
+* **struct sbi_domain_memregion** - Representation of a domain memory region
+* **struct sbi_hartmask** - Representation of domain HART set
+* **struct sbi_domain** - Representation of a domain instance
+
+Each HART of a RISC-V platform must have an OpenSBI domain assigned to it.
+The OpenSBI platform support is responsible for populating domains and
+providing HART id to domain mapping. The OpenSBI domain support will by
+default assign **the ROOT domain** to all HARTs of a RISC-V platform so
+it is not mandatory for the OpenSBI platform support to populate domains.
+
+Domain Memory Region
+--------------------
+
+A domain memory region is represented by **struct sbi_domain_memregion** in
+OpenSBI and has following details:
+
+* **order** - The size of a memory region is **2 ^ order** where **order**
+  must be **3 <= order <= __riscv_xlen**
+* **base** - The base address of a memory region is **2 ^ order**
+  aligned start address
+* **flags** - The flags of a memory region represent memory type (i.e.
+  RAM or MMIO) and allowed accesses (i.e. READ, WRITE, EXECUTE, etc)
+
+Domain Instance
+---------------
+
+A domain instance is represented by **struct sbi_domain** in OpenSBI and
+has following details:
+
+* **index** - Logical index of this domain
+* **name** - Name of this domain
+* **assigned_harts** - HARTs assigned to this domain
+* **possible_harts** - HARTs possible in this domain
+* **regions** - Array of memory regions terminated by a memory region
+  with order zero
+* **boot_hartid** - HART id of the HART booting this domain. The domain
+  boot HART will be started at boot-time if boot HART is possible and
+  assigned for this domain.
+* **next_addr** - Address of the next booting stage for this domain
+* **next_arg1** - Arg1 (or 'a1' register) of the next booting stage for
+  this domain
+* **next_mode** - Privilege mode of the next booting stage for this
+  domain. This can be either S-mode or U-mode.
+* **system_reset_allowed** - Is domain allowed to reset the system?
+* **system_suspend_allowed** - Is domain allowed to suspend the system?
+
+The memory regions represented by **regions** in **struct sbi_domain** have
+following additional constraints to align with RISC-V PMP requirements:
+
+* A memory region to protect OpenSBI firmware from S-mode and U-mode
+  should always be present
+* For two overlapping memory regions, one should be sub-region of another
+* Two overlapping memory regions should not be of same size
+* Two overlapping memory regions cannot have same flags
+* Memory access checks on overlapping address should prefer smallest
+  overlapping memory region flags.
+
+ROOT Domain
+-----------
+
+**The ROOT domain** is the default OpenSBI domain which is assigned by
+default to all HARTs of a RISC-V platform. The OpenSBI domain support
+will hand-craft **the ROOT domain** very early at boot-time in the
+following manner:
+
+* **index** - Logical index of the ROOT domain is always zero
+* **name** - Name of the ROOT domain is "root"
+* **assigned_harts** - At boot-time all valid HARTs of a RISC-V platform
+  are assigned the ROOT domain which changes later based on OpenSBI
+  platform support
+* **possible_harts** - All valid HARTs of a RISC-V platform are possible
+  HARTs of the ROOT domain
+* **regions** - Two memory regions available to the ROOT domain:
+  **A)** A memory region to protect OpenSBI firmware from S-mode and U-mode
+  **B)** A memory region of **order=__riscv_xlen** allowing S-mode and
+  U-mode access to full memory address space
+* **boot_hartid** - Coldboot HART is the HART booting the ROOT domain
+* **next_addr** - Next booting stage address in coldboot HART scratch
+  space is the next address for the ROOT domain
+* **next_arg1** - Next booting stage arg1 in coldboot HART scratch space
+  is the next arg1 for the ROOT domain
+* **next_mode** - Next booting stage mode in coldboot HART scratch space
+  is the next mode for the ROOT domain
+* **system_reset_allowed** - The ROOT domain is allowed to reset the system
+* **system_suspend_allowed** - The ROOT domain is allowed to suspend the system
+
+Domain Effects
+--------------
+
+Few noteworthy effects of a system partitioned into domains are as follows:
+
+* At any point in time, a HART is running in exactly one OpenSBI domain context
+* The SBI IPI and RFENCE calls from HART A are restricted to the HARTs in
+  domain assigned to HART A
+* The SBI HSM calls which try to change/read state of HART B from HART A will
+  only work if both HART A and HART B are assigned same domain
+* A HART running in S-mode or U-mode can only access memory based on the
+  memory regions of the domain assigned to the HART
+
+Domain Device Tree Bindings
+---------------------------
+
+The OpenSBI domains can be described in the **device tree (DT) blob** (or
+flattened device tree) passed to the OpenSBI firmwares by the previous
+booting stage. This allows OpenSBI platform support to parse and populate
+OpenSBI domains from the device tree blob (or flattened device tree).
+
+### Domain Configuration Node
+
+All OpenSBI domain description related DT nodes should be under the domain
+configuration DT node. The **/chosen** DT node is the preferred parent of
+the domain configuration DT node.
+
+The DT properties of a domain configuration DT node are as follows:
+
+* **compatible** (Mandatory) - The compatible string of the domain
+  configuration. This DT property should have value *"opensbi,domain,config"*
+
+### Domain Memory Region Node
+
+The domain memory region DT node describes details of a memory region and
+can be pointed by multiple domain instance DT nodes. The access permissions
+of the memory region are specified separately in domain instance node.
+
+The DT properties of a domain memory region DT node are as follows:
+
+* **compatible** (Mandatory) - The compatible string of the domain memory
+  region. This DT property should have value *"opensbi,domain,memregion"*
+* **base** (Mandatory) - The base address of the domain memory region. This
+  DT property should have a **2 ^ order** aligned 64 bit address (i.e. two
+  DT cells).
+* **order** (Mandatory) - The order of the domain memory region. This DT
+  property should have a 32 bit value (i.e. one DT cell) in the range
+  **3 <= order <= __riscv_xlen**.
+* **mmio** (Optional) - A boolean flag representing whether the domain
+  memory region is a memory-mapped I/O (MMIO) region.
+* **devices** (Optional) - The list of device DT node phandles for devices
+  which fall under this domain memory region.
+
+### Domain Instance Node
+
+The domain instance DT node describes set of possible HARTs, set of memory
+regions, and other details of a domain instance.
+
+The DT properties of a domain instance DT node are as follows:
+
+* **compatible** (Mandatory) - The compatible string of the domain instance.
+  This DT property should have value *"opensbi,domain,instance"*
+* **possible-harts** (Optional) - The list of CPU DT node phandles for the
+  the domain instance. This list represents the possible HARTs of the
+  domain instance.
+* **regions** (Optional) - The list of domain memory region DT node phandle
+  and access permissions for the domain instance. Each list entry is a pair
+  of DT node phandle and access permissions. The access permissions are
+  represented as a 32bit bitmask having bits: **readable** (BIT[0]),
+  **writeable** (BIT[1]), **executable** (BIT[2]), and **m-mode** (BIT[3]).
+* **boot-hart** (Optional) - The DT node phandle of the HART booting the
+  domain instance. If coldboot HART is assigned to the domain instance then
+  this DT property is ignored and the coldboot HART is assumed to be the
+  boot HART of the domain instance.
+* **next-arg1** (Optional) - The 64 bit next booting stage arg1 for the
+  domain instance. If this DT property is not available and coldboot HART
+  is not assigned to the domain instance then **0x0** is used as default
+  value. If this DT property is not available and coldboot HART is assigned
+  to the domain instance then **next booting stage arg1 of coldboot HART**
+  is used as default value.
+* **next-addr** (Optional) - The 64 bit next booting stage address for the
+  domain instance. If this DT property is not available and coldboot HART
+  is not assigned to the domain instance then **0x0** is used as default
+  value. If this DT property is not available and coldboot HART is assigned
+  to the domain instance then **next booting stage address of coldboot HART**
+  is used as default value.
+* **next-mode** (Optional) - The 32 bit next booting stage mode for the
+  domain instance. The possible values of this DT property are: **0x1**
+  (s-mode), and **0x0** (u-mode). If this DT property is not available
+  and coldboot HART is not assigned to the domain instance then **0x1**
+  is used as default value. If this DT property is not available and
+  coldboot HART is assigned to the domain instance then **next booting
+  stage mode of coldboot HART** is used as default value.
+* **system-reset-allowed** (Optional) - A boolean flag representing
+  whether the domain instance is allowed to do system reset.
+* **system-suspend-allowed** (Optional) - A boolean flag representing
+  whether the domain instance is allowed to do system suspend.
+
+### Assigning HART To Domain Instance
+
+By default, all HARTs are assigned to **the ROOT domain**. The OpenSBI
+platform support can provide the HART to domain instance assignment using
+platform specific callback.
+
+The HART to domain instance assignment can be parsed from the device tree
+using optional DT property **opensbi,domain** in each CPU DT node. The
+value of DT property **opensbi,domain** is the DT phandle of the domain
+instance DT node. If **opensbi,domain** DT property is not specified then
+corresponding HART is assigned to **the ROOT domain**.
+
+### Domain Configuration Only Accessible to OpenSBI
+
+The software running inside a domain instance should only be aware of
+devices and hardware resources accessible to itself.
+
+To hide domain configuration from domain instances, the following should
+be done:
+
+* The previous booting stage should preferably provide a separate device
+  tree for each domain instance and mention location of device tree in
+  respective domain instance DT nodes using **next-arg1** DT property.
+* If domain assigned to a HART does not have separate device tree then
+  OpenSBI platform support should remove all domain configuration details
+  from the device tree passed by previous booting stage before passing it
+  to the next booting stage.
+
+### Example
+
+```
+    chosen {
+        opensbi-domains {
+            compatible = "opensbi,domain,config";
+
+            tmem: tmem {
+                compatible = "opensbi,domain,memregion";
+                base = <0x0 0x80100000>;
+                order = <20>;
+            };
+
+            tuart: tuart {
+                compatible = "opensbi,domain,memregion";
+                base = <0x0 0x10011000>;
+                order = <12>;
+                mmio;
+                devices = <&uart1>;
+            };
+
+            allmem: allmem {
+                compatible = "opensbi,domain,memregion";
+                base = <0x0 0x0>;
+                order = <64>;
+            };
+
+            tdomain: trusted-domain {
+                compatible = "opensbi,domain,instance";
+                possible-harts = <&cpu0>;
+                regions = <&tmem 0x7>, <&tuart 0x7>;
+                boot-hart = <&cpu0>;
+                next-arg1 = <0x0 0x0>;
+                next-addr = <0x0 0x80100000>;
+                next-mode = <0x0>;
+                system-reset-allowed;
+                system-suspend-allowed;
+            };
+
+            udomain: untrusted-domain {
+                compatible = "opensbi,domain,instance";
+                possible-harts = <&cpu1 &cpu2 &cpu3 &cpu4>;
+                regions = <&tmem 0x0>, <&tuart 0x0>, <&allmem 0x7>;
+            };
+        };
+    };
+
+    cpus {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        timebase-frequency = <10000000>;
+
+        cpu0: cpu@0 {
+            device_type = "cpu";
+            reg = <0x00>;
+            compatible = "riscv";
+            opensbi-domain = <&tdomain>;
+            ...
+        };
+
+        cpu1: cpu@1 {
+            device_type = "cpu";
+            reg = <0x01>;
+            compatible = "riscv";
+            opensbi-domain = <&udomain>;
+            ...
+        };
+
+        cpu2: cpu@2 {
+            device_type = "cpu";
+            reg = <0x02>;
+            compatible = "riscv";
+            opensbi-domain = <&udomain>;
+            ...
+        };
+
+        cpu3: cpu@3 {
+            device_type = "cpu";
+            reg = <0x03>;
+            compatible = "riscv";
+            opensbi-domain = <&udomain>;
+            ...
+        };
+
+        cpu4: cpu@4 {
+            device_type = "cpu";
+            reg = <0x04>;
+            compatible = "riscv";
+            opensbi-domain = <&udomain>;
+            ...
+        };
+    };
+
+    uart1: serial@10011000 {
+        ...
+    };
+```

docs/doxygen.cfg

@@ -793,7 +793,9 @@ WARN_LOGFILE           =
 INPUT                  = @@SRC_DIR@@/README.md \
                          @@SRC_DIR@@/docs/contributing.md \
                          @@SRC_DIR@@/docs/platform_guide.md \
+                         @@SRC_DIR@@/docs/platform_requirements.md \
                          @@SRC_DIR@@/docs/library_usage.md \
+                         @@SRC_DIR@@/docs/domain_support.md \
                          @@SRC_DIR@@/docs/firmware \
                          @@SRC_DIR@@/docs/platform \
                          @@SRC_DIR@@/include \
@@ -948,7 +950,7 @@ FILTER_SOURCE_PATTERNS =
 # (index.html). This can be useful if you have a project on for instance GitHub
 # and want to reuse the introduction page also for the doxygen output.
 
-USE_MDFILE_AS_MAINPAGE = 
+USE_MDFILE_AS_MAINPAGE = README.md
 
 #---------------------------------------------------------------------------
 # Configuration options related to source browsing
@@ -1444,7 +1446,7 @@ DISABLE_INDEX          = NO
 # The default value is: NO.
 # This tag requires that the tag GENERATE_HTML is set to YES.
 
-GENERATE_TREEVIEW      = NO
+GENERATE_TREEVIEW      = YES
 
 # The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values that
 # doxygen will group on one line in the generated HTML documentation.

docs/firmware/fw.md

@@ -51,11 +51,17 @@ case, a *FW_PAYLOAD* firmware allows embedding a flattened device tree in the
 Firmware Configuration and Compilation
 --------------------------------------
 
-All firmware types mandate the definition of the following compile time
-configuration parameter.
+All firmware types support the following common compile time configuration
+parameters:
 
-* **FW_TEXT_ADDR** - Defines the address at which the previous booting stage
-  loads OpenSBI firmware.
+* **FW_TEXT_ADDR** - Defines the execution address of the OpenSBI firmware.
+  This configuration parameter is mandatory.
+* **FW_FDT_PATH** - Path to an external flattened device tree binary file to
+  be embedded in the *.rodata* section of the final firmware. If this option
+  is not provided then the firmware will expect the FDT to be passed as an
+  argument by the prior booting stage.
+* **FW_FDT_PADDING** - Optional zero bytes padding to the embedded flattened
+  device tree binary file specified by **FW_FDT_PATH** option.
 
 Additionally, each firmware type as a set of type specific configuration
 parameters. Detailed information for each firmware type can be found in the

docs/firmware/fw_dynamic.md

@@ -1,4 +1,4 @@
-OpenSBI Firmware with Dynamic Information *FW_DYNAMIC*
+OpenSBI Firmware with Dynamic Information (FW_DYNAMIC)
 ======================================================
 
 OpenSBI **firmware with dynamic info (FW_DYNAMIC)** is a firmware which gets

docs/firmware/fw_jump.md

@@ -1,4 +1,4 @@
-OpenSBI Firmware with Jump Address *FW_JUMP*
+OpenSBI Firmware with Jump Address (FW_JUMP)
 ============================================
 
 OpenSBI **firmware with Jump Address (FW_JUMP)** is a firmware which only

docs/firmware/fw_payload.md

@@ -1,4 +1,4 @@
-OpenSBI Firmware with Payload *FW_PAYLOAD*
+OpenSBI Firmware with Payload (FW_PAYLOAD)
 ==========================================
 
 OpenSBI **firmware with Payload (FW_PAYLOAD)** is a firmware which directly
@@ -55,23 +55,9 @@ file. The parameters currently defined are as follows:
   automatically generated and used as a payload. This test payload executes
   an infinite `while (1)` loop after printing a message on the platform console.
 
-* **FW_PAYLOAD_FDT_PATH** - Path to an external flattened device tree binary
-  file to be embedded in the *.text* section of the final firmware. If this
-  option is not provided and no internal device tree file is specified by the
-  platform (c.f. *FW_PAYLOAD_FDT*), then the firmware will expect the FDT to
-  be passed as an argument by the prior booting stage.
-
-* **FW_PAYLOAD_FDT** - Path to an internal flattened device tree binary file
-  defined by the platform code. The file name must match the DTB file name
-  specified in the platform *objects.mk* file with the *platform-dtb-y* entry.
-  This option results in *FW_PAYLOAD_FDT_PATH* to be automatically set.
-  Specifying *FW_PAYLOAD_FDT_PATH* on the `make` command line disables
-  *FW_PAYLOAD_FDT* and the command line specified device tree binary file is
-  used for building the final firmware.
-
 * **FW_PAYLOAD_FDT_ADDR** - Address where the FDT passed by the prior booting
-  stage or specified by the *FW_PAYLOAD_FDT_PATH* parameter and embedded in
-  the *.text* section will be placed before executing the next booting stage,
+  stage or specified by the *FW_FDT_PATH* parameter and embedded in the
+  *.rodata* section will be placed before executing the next booting stage,
   that is, the payload firmware. If this option is not provided, then the
   firmware will pass the FDT address passed by the previous booting stage
   to the next booting stage.
@@ -83,7 +69,4 @@ The *[qemu/virt]* platforms illustrate how to configure and use a *FW_PAYLOAD*
 firmware. Detailed information regarding these platforms can be found in the
 platform documentation files.
 
-The *kendryte/k210* platform also enables a build of a *FW_PAYLOAD* using an
-internally defined device tree file (*FW_PAYLOAD_FDT*).
-
 [qemu/virt]: ../platform/qemu_virt.md

docs/platform/andes-ae350.md

@@ -19,12 +19,12 @@ Building Andes AE350 Platform
 -----------------------------
 
 To use Linux v5.2 should be used to build Andes AE350 OpenSBI binaries by using
-the compile time option FW_PAYLOAD_FDT_PATH.
+the compile time option FW_FDT_PATH.
 
 AE350's dts is included in https://github.com/andestech/linux/tree/ast-v3_2_0-release-public
 
 **Linux Kernel Payload**
 
 ```
-make PLATFORM=andes/ae350 FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image FW_PAYLOAD_FDT_PATH=<ae350.dtb path>
+make PLATFORM=andes/ae350 FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image FW_FDT_PATH=<ae350.dtb path>
 ```

docs/platform/generic.md

@@ -0,0 +1,56 @@
+Generic Platform
+================
+
+The **Generic** platform is a flattened device tree (FDT) based platform
+where all platform specific functionality is provided based on FDT passed
+by previous booting stage. The **Generic** platform allows us to use same
+OpenSBI firmware binaries on various emulators, simulators, FPGAs, and
+boards.
+
+By default, the generic FDT platform makes following assumptions:
+
+1. platform FW_TEXT_START is 0x80000000
+2. platform features are default
+3. platform stack size is default
+4. platform has no quirks or work-arounds
+
+The above assumptions (except 1) can be overridden by adding special platform
+callbacks which will be called based on FDT root node compatible string.
+
+Users of the generic FDT platform will have to ensure that:
+
+1. Various FDT based drivers under lib/utils directory are upto date
+   based on their platform requirements
+2. The FDT passed by previous booting stage has DT compatible strings and
+   DT properties in sync with the FDT based drivers under lib/utils directory
+3. The FDT must have "stdout-path" DT property in the "/chosen" DT node when
+   a platform has multiple serial ports or consoles
+4. On multi-HART platform, the FDT must have a DT node for IPI device and
+   lib/utils/ipi directory must have corresponding FDT based IPI driver
+5. The FDT must have a DT node for timer device and lib/utils/timer directory
+   must have corresponding FDT based timer driver
+
+To build the platform-specific library and firmware images, provide the
+*PLATFORM=generic* parameter to the top level `make` command.
+
+For custom FW_TEXT_START, we can build the platform-specific library and
+firmware images by passing *PLATFORM=generic FW_TEXT_START=<custom_text_start>*
+parameter to the top level `make` command.
+
+Platform Options
+----------------
+
+The *Generic* platform does not have any platform-specific options.
+
+RISC-V Platforms Using Generic Platform
+---------------------------------------
+
+* **QEMU RISC-V Virt Machine** (*[qemu_virt.md]*)
+* **Spike** (*[spike.md]*)
+* **Shakti C-class SoC Platform** (*[shakti_cclass.md]*)
+* **T-HEAD C9xx series Processors** (*[thead-c9xx.md]*)
+
+[qemu_virt.md]: qemu_virt.md
+[spike.md]: spike.md
+[shakti_cclass.md]: shakti_cclass.md
+[thead-c9xx.md]: thead-c9xx.md

docs/platform/nuclei_ux600.md

@@ -0,0 +1,22 @@
+
+Nuclei UX600 Platform
+=====================
+
+The **Nuclei UX600** is a 64-bit RISC-V Core which is capable of running Linux.
+
+> Nuclei UX600: single core, pipeline as single-issue and 6~9 variable stages, in-order dispatch and out-of-order write-back, running up to >1.2GHz
+
+To build the platform-specific library and firmware images, provide the
+*PLATFORM=nuclei/ux600* parameter to the top level `make` command.
+
+Platform Options
+----------------
+
+The *Nuclei UX600* platform does not have any platform-specific options.
+
+Building Nuclei UX600 Platform
+------------------------------
+
+```
+make PLATFORM=nuclei/ux600 clean all
+```

docs/platform/platform.md

@@ -3,6 +3,11 @@ OpenSBI Supported Platforms
 
 OpenSBI currently supports the following virtual and hardware platforms:
 
+* **Generic**: Flattened device tree (FDT) based platform where platform
+  specific functionality is provided based on the FDT passed by previous
+  booting stage. More details on this platform can be found in the file
+  *[generic.md]*.
+
 * **QEMU RISC-V Virt Machine**: Platform support for the QEMU *virt* virtual
   RISC-V machine. This virtual machine is intended for RISC-V software
   development and tests. More details on this platform can be found in the
@@ -17,16 +22,22 @@ OpenSBI currently supports the following virtual and hardware platforms:
   boards such as the Kendryte KD233 or the Sipeed MAIX Dock.
 
 * **Ariane FPGA SoC**: Platform support for the Ariane FPGA SoC used on
-  Genesys 2 board.
+  Genesys 2 board. More details on this platform can be found in the file
+  *[fpga-ariane.md]*.
 
-* **Andes AE350 SoC**: Platform support for the Andes's SoC (AE350).
+* **Andes AE350 SoC**: Platform support for the Andes's SoC (AE350). More
+  details on this platform can be found in the file *[andes-ae350.md]*.
 
-* **T-HEAD C910**: Platform support for the T-HEAD C910 Processor.
+* **Spike**: Platform support for the Spike emulator. More
+  details on this platform can be found in the file *[spike.md]*.
 
-* **Spike**: Platform support for the Spike emulator.
+* **OpenPiton FPGA SoC**: Platform support OpenPiton research platform based
+  on ariane core. More details on this platform can be found in the file
+  *[fpga-openpiton.md]*.
 
-* **OpenPiton FPGA SoC**: Platform support OpenPiton research platform based on
-ariane core.
+* **Shakti C-class SoC Platform**: Platform support for Shakti C-class
+  processor based SOCs. More details on this platform can be found in the
+  file *[shakti_cclass.md]*.
 
 The code for these supported platforms can be used as example to implement
 support for other platforms. The *platform/template* directory also provides
@@ -34,10 +45,12 @@ template files for implementing support for a new platform. The *object.mk*,
 *config.mk* and *platform.c* template files provides enough comments to
 facilitate the implementation.
 
+[generic.md]: generic.md
 [qemu_virt.md]: qemu_virt.md
 [sifive_fu540.md]: sifive_fu540.md
 [fpga-ariane.md]: fpga-ariane.md
-[andes_ae350.md]: andes-ae350.md
+[andes-ae350.md]: andes-ae350.md
 [thead-c910.md]: thead-c910.md
 [spike.md]: spike.md
-[fpga_openpiton.md]: fpga_openpiton.md
+[fpga-openpiton.md]: fpga-openpiton.md
+[shakti_cclass.md]: shakti_cclass.md

docs/platform/qemu_virt.md

@@ -7,7 +7,7 @@ software development and testing. It is also referred to as
 storage, and other types of IO.
 
 To build the platform-specific library and firmware images, provide the
-*PLATFORM=qemu/virt* parameter to the top level `make` command.
+*PLATFORM=generic* parameter to the top level `make` command.
 
 Platform Options
 ----------------
@@ -22,13 +22,13 @@ Execution on QEMU RISC-V 64-bit
 
 Build:
 ```
-make PLATFORM=qemu/virt
+make PLATFORM=generic
 ```
 
 Run:
 ```
 qemu-system-riscv64 -M virt -m 256M -nographic \
-	-kernel build/platform/qemu/virt/firmware/fw_payload.elf
+	-bios build/platform/generic/firmware/fw_payload.bin
 ```
 
 **U-Boot Payload**
@@ -38,19 +38,19 @@ the `qemu-riscv64_smode_defconfig` configuration.
 
 Build:
 ```
-make PLATFORM=qemu/virt FW_PAYLOAD_PATH=<uboot_build_directory>/u-boot.bin
+make PLATFORM=generic FW_PAYLOAD_PATH=<uboot_build_directory>/u-boot.bin
 ```
 
 Run:
 ```
 qemu-system-riscv64 -M virt -m 256M -nographic \
-	-kernel build/platform/qemu/virt/firmware/fw_payload.elf
+	-bios build/platform/generic/firmware/fw_payload.elf
 ```
 or
 ```
 qemu-system-riscv64 -M virt -m 256M -nographic \
-	-kernel build/platform/qemu/virt/firmware/fw_jump.elf \
-	-device loader,file=<uboot_build_directory>/u-boot.bin,addr=0x80200000
+	-bios build/platform/generic/firmware/fw_jump.bin \
+	-kernel <uboot_build_directory>/u-boot.bin
 ```
 
 **Linux Kernel Payload**
@@ -60,13 +60,13 @@ Note: We assume that the Linux kernel is compiled using
 
 Build:
 ```
-make PLATFORM=qemu/virt FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image
+make PLATFORM=generic FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image
 ```
 
 Run:
 ```
 qemu-system-riscv64 -M virt -m 256M -nographic \
-	-kernel build/platform/qemu/virt/firmware/fw_payload.elf \
+	-bios build/platform/generic/firmware/fw_payload.elf \
 	-drive file=<path_to_linux_rootfs>,format=raw,id=hd0 \
 	-device virtio-blk-device,drive=hd0 \
 	-append "root=/dev/vda rw console=ttyS0"
@@ -74,8 +74,8 @@ qemu-system-riscv64 -M virt -m 256M -nographic \
 or
 ```
 qemu-system-riscv64 -M virt -m 256M -nographic \
-	-kernel build/platform/qemu/virt/firmware/fw_jump.elf \
-	-device loader,file=<linux_build_directory>/arch/riscv/boot/Image,addr=0x80200000 \
+	-bios build/platform/generic/firmware/fw_jump.bin \
+	-kernel <linux_build_directory>/arch/riscv/boot/Image \
 	-drive file=<path_to_linux_rootfs>,format=raw,id=hd0 \
 	-device virtio-blk-device,drive=hd0 \
 	-append "root=/dev/vda rw console=ttyS0"
@@ -89,13 +89,13 @@ Execution on QEMU RISC-V 32-bit
 
 Build:
 ```
-make PLATFORM=qemu/virt
+make PLATFORM=generic PLATFORM_RISCV_XLEN=32
 ```
 
 Run:
 ```
 qemu-system-riscv32 -M virt -m 256M -nographic \
-	-kernel build/platform/qemu/virt/firmware/fw_payload.elf
+	-bios build/platform/generic/firmware/fw_payload.bin
 ```
 
 **U-Boot Payload**
@@ -105,37 +105,35 @@ the `qemu-riscv32_smode_defconfig` configuration.
 
 Build:
 ```
-make PLATFORM=qemu/virt FW_PAYLOAD_PATH=<uboot_build_directory>/u-boot.bin
+make PLATFORM=generic PLATFORM_RISCV_XLEN=32 FW_PAYLOAD_PATH=<uboot_build_directory>/u-boot.bin
 ```
 
 Run:
 ```
 qemu-system-riscv32 -M virt -m 256M -nographic \
-	-kernel build/platform/qemu/virt/firmware/fw_payload.elf
+	-bios build/platform/generic/firmware/fw_payload.elf
 ```
 or
 ```
 qemu-system-riscv32 -M virt -m 256M -nographic \
-	-kernel build/platform/qemu/virt/firmware/fw_jump.elf \
-	-device loader,file=<uboot_build_directory>/u-boot.bin,addr=0x80400000
+	-bios build/platform/generic/firmware/fw_jump.bin \
+	-kernel <uboot_build_directory>/u-boot.bin
 ```
 
 **Linux Kernel Payload**
 
 Note: We assume that the Linux kernel is compiled using
-*arch/riscv/configs/rv32_defconfig* (kernel 5.1 and newer)
-respectively using *arch/riscv/configs/defconfig* plus setting
-CONFIG_ARCH_RV32I=y (kernel 5.0 and older).
+*arch/riscv/configs/rv32_defconfig*.
 
 Build:
 ```
-make PLATFORM=qemu/virt FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image
+make PLATFORM=generic PLATFORM_RISCV_XLEN=32 FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image
 ```
 
 Run:
 ```
 qemu-system-riscv32 -M virt -m 256M -nographic \
-	-kernel build/platform/qemu/virt/firmware/fw_payload.elf \
+	-bios build/platform/generic/firmware/fw_payload.elf \
 	-drive file=<path_to_linux_rootfs>,format=raw,id=hd0 \
 	-device virtio-blk-device,drive=hd0 \
 	-append "root=/dev/vda rw console=ttyS0"
@@ -143,8 +141,8 @@ qemu-system-riscv32 -M virt -m 256M -nographic \
 or
 ```
 qemu-system-riscv32 -M virt -m 256M -nographic \
-	-kernel build/platform/qemu/virt/firmware/fw_jump.elf \
-	-device loader,file=<linux_build_directory>/arch/riscv/boot/Image,addr=0x80400000 \
+	-bios build/platform/generic/firmware/fw_jump.bin \
+	-kernel <linux_build_directory>/arch/riscv/boot/Image \
 	-drive file=<path_to_linux_rootfs>,format=raw,id=hd0 \
 	-device virtio-blk-device,drive=hd0 \
 	-append "root=/dev/vda rw console=ttyS0"

docs/platform/shakti_cclass.md

@@ -0,0 +1,33 @@
+Shakti C-class SoC Platform
+===========================
+C-Class is a member of the SHAKTI family of processors from
+Indian Institute of Technology - Madras (IIT-M).
+
+It is an extremely configurable and commercial-grade 5-stage
+in-order core supporting the standard RV64GCSUN ISA extensions.
+
+For more details, refer:
+* https://gitlab.com/shaktiproject/cores/c-class/blob/master/README.md
+* https://c-class.readthedocs.io/en/latest
+* https://shakti.org.in
+
+Platform Options
+----------------
+
+The *Shakti C-class SoC* platform does not have any platform-specific
+options.
+
+Building Shakti C-class Platform
+--------------------------------
+
+**Linux Kernel Payload**
+
+```
+make PLATFORM=generic FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image FW_FDT_PATH=<shakti.dtb path>
+```
+
+**Test Payload**
+
+```
+make PLATFORM=generic FW_FDT_PATH=<shakti.dtb path>
+```

docs/platform/sifive_fu540.md

@@ -27,50 +27,28 @@ U-Boot v2020.01 (or higher) should be used.
 The HiFive Unleashed device tree(DT) is merged in Linux v5.2 release. This
 DT (device tree) is not backward compatible with the DT passed from FSBL.
 
-To use Linux v5.2 (or higher, the pre-built DTB (DT binary) from Linux v5.2
+To use Linux v5.2 (or higher), the pre-built DTB (DT binary) from Linux v5.2
 (or higher) should be used to build SiFive FU540 OpenSBI binaries by using
-the compile time option *FW_PAYLOAD_FDT_PATH*.
+the compile time option *FW_FDT_PATH*.
 
 ```
 make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image
 or
 (For Linux v5.2 or higher)
-make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image FW_PAYLOAD_FDT_PATH=<hifive-unleashed-a00.dtb path from Linux kernel>
+make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image FW_FDT_PATH=<hifive-unleashed-a00.dtb path from Linux kernel>
 ```
 
 **U-Boot Payload**
 
 The command-line example here assumes that U-Boot was compiled using the
-sifive_fu540_defconfig configuration and with U-Boot v2020.01 (or higher).
-
-The detailed U-Boot booting guide is avaialble at [U-Boot].
+sifive_fu540_defconfig configuration and with U-Boot v2020.01, and up to
+v2021.04. sifive_unleashed_defconfig shall be used with v2021.07 or above.
 
 ```
 make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH=<u-boot_build_dir>/u-boot-dtb.bin
 ```
-
-**U-Boot & Linux Kernel as a single payload**
-
-A single monolithic image containing both U-Boot & Linux can also be used if
-network boot setup is not available.
-
-1. Create a temporary image with u-boot-dtb.bin as the first payload. The
-command-line example here assumes that U-Boot was compiled using
-sifive_fu540_defconfig configuration.
-```
-dd if=~/workspace/u-boot-riscv/u-boot-dtb.bin of=/tmp/temp.bin bs=1M
-```
-2. Append the Linux Kernel image.
-```
-dd if=<linux_build_directory>/arch/riscv/boot/Image of=/tmp/temp.bin bs=1M seek=4
-```
-3. Compile OpenSBI with temp.bin (generated in step 2) as payload.
-```
-make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH=/tmp/temp.bin
-or
-(For U-Boot which follows Linux v5.2 (or higher) DT bindings)
-make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH=/tmp/temp.bin
-```
+For U-Boot v2020.07-rc4 or later releases, SPL support was added in U-Boot.
+Please refer to the detailed U-Boot booting guide available at [U-Boot].
 
 Flashing the OpenSBI firmware binary to storage media:
 ------------------------------------------------------
@@ -169,22 +147,47 @@ booti ${kernel_addr_r} - ${fdt_addr_r}
 QEMU Specific Instructions
 --------------------------
 If you want to test OpenSBI with QEMU 'sifive_u' machine, please follow the
-same instructions above, with the exception of not passing FW_PAYLOAD_FDT_PATH.
+same instructions above, with the exception of not passing FW_FDT_PATH.
 
 This is because QEMU generates a device tree blob on the fly based on the
 command line parameters and it's compatible with the one used in the upstream
 Linux kernel.
 
-When U-Boot v2020.01 (or higher) is used as the payload, as the SiFive FU540
+When U-Boot v2021.07 (or higher) is used as the payload, as the SiFive FU540
 DTB for the real hardware is embedded in U-Boot binary itself, due to the same
-reason above, we need to switch the U-Boot sifive_fu540_defconfig configuration
-from CONFIG_OF_SEPARATE to CONFIG_OF_PRIOR_STAGE so that U-Boot uses the DTB
-generated by QEMU, and u-boot.bin should be used as the payload image, like:
+reason above, we need to switch the U-Boot sifive_unleashed_defconfig
+configuration from **CONFIG_OF_SEPARATE** to **CONFIG_OF_PRIOR_STAGE** so that
+U-Boot uses the DTB generated by QEMU, and u-boot.bin should be used as the
+payload image, like:
 
 ```
 make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH=<u-boot_build_dir>/u-boot.bin
 ```
 
+U-Boot v2020.07 release added SPL support to SiFive HiFive Unleashed board,
+hence a build error will be seen after you switch to **CONFIG_OF_PRIOR_STAGE**.
+
+```
+./tools/mkimage: Can't open arch/riscv/dts/hifive-unleashed-a00.dtb: No such file or directory
+./tools/mkimage: failed to build FIT
+Makefile:1402: recipe for target 'u-boot.img' failed
+make: *** [u-boot.img] Error 1
+```
+
+The above errors can be safely ignored as we don't run U-Boot SPL under QEMU.
+
+Run:
+```
+qemu-system-riscv64 -M sifive_u -m 256M -nographic \
+	-bios build/platform/sifive/fu540/firmware/fw_payload.bin
+```
+or
+```
+qemu-system-riscv64 -M sifive_u -m 256M -nographic \
+	-bios build/platform/sifive/fu540/firmware/fw_jump.bin \
+	-kernel <uboot_build_dir>/u-boot.bin
+```
+
 While the real hardware operates at the 64-bit mode, it's possible for QEMU to
 test the 32-bit OpenSBI firmware. This can be helpful for testing 32-bit SiFive
 specific drivers.

docs/platform/spike.md

@@ -9,7 +9,7 @@ on **Spike** simulator and QEMU Spike machine.
 For more details, refer [Spike on GitHub](https://github.com/riscv/riscv-isa-sim)
 
 To build the platform-specific library and firmware images, provide the
-*PLATFORM=spike* parameter to the top level `make` command.
+*PLATFORM=generic* parameter to the top level `make` command.
 
 Platform Options
 ----------------
@@ -23,12 +23,12 @@ Execution on Spike Simulator
 
 Build:
 ```
-make PLATFORM=spike
+make PLATFORM=generic
 ```
 
 Run:
 ```
-spike build/platform/spike/firmware/fw_payload.elf
+spike build/platform/generic/firmware/fw_payload.elf
 ```
 
 **Linux Kernel Payload**
@@ -38,12 +38,12 @@ Note: We assume that the Linux kernel is compiled using
 
 Build:
 ```
-make PLATFORM=spike FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image
+make PLATFORM=generic FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image
 ```
 
 Run:
 ```
-spike --initrd <path_to_cpio_ramdisk> build/platform/spike/firmware/fw_payload.elf
+spike --initrd <path_to_cpio_ramdisk> build/platform/generic/firmware/fw_payload.elf
 ```
 
 Execution on QEMU RISC-V 64-bit
@@ -53,13 +53,13 @@ Execution on QEMU RISC-V 64-bit
 
 Build:
 ```
-make PLATFORM=spike
+make PLATFORM=generic
 ```
 
 Run:
 ```
 qemu-system-riscv64 -M spike -m 256M -nographic \
-	-kernel build/platform/spike/firmware/fw_payload.elf
+	-bios build/platform/generic/firmware/fw_payload.elf
 ```
 
 **Linux Kernel Payload**
@@ -69,20 +69,20 @@ Note: We assume that the Linux kernel is compiled using
 
 Build:
 ```
-make PLATFORM=spike FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image
+make PLATFORM=generic FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image
 ```
 
 Run:
 ```
 qemu-system-riscv64 -M spike -m 256M -nographic \
-	-kernel build/platform/spike/firmware/fw_payload.elf \
+	-bios build/platform/generic/firmware/fw_payload.elf \
 	-initrd <path_to_cpio_ramdisk> \
 	-append "root=/dev/ram rw console=hvc0 earlycon=sbi"
 ```
 or
 ```
 qemu-system-riscv64 -M spike -m 256M -nographic \
-	-bios build/platform/spike/firmware/fw_jump.elf \
+	-bios build/platform/generic/firmware/fw_jump.elf \
 	-kernel <linux_build_directory>/arch/riscv/boot/Image \
 	-initrd <path_to_cpio_ramdisk> \
 	-append "root=/dev/ram rw console=hvc0 earlycon=sbi"

docs/platform/thead-c910.md

@@ -1,34 +0,0 @@
-T-HEAD C910 Processor
-=====================
-C910 is a 12-stage, 3 issues, 8 executions, out-of-order 64-bit RISC-V CPU which
-supports 16 cores, runs with 2.5GHz, and is capable of running Linux.
-
-To build platform specific library and firmwares, provide the
-*PLATFORM=thead/c910* parameter to the top level make command.
-
-Platform Options
-----------------
-
-The *T-HEAD C910* platform does not have any platform-specific options.
-
-Building T-HEAD C910 Platform
------------------------------
-
-```
-make PLATFORM=thead/c910
-```
-
-Booting T-HEAD C910 Platform
-----------------------------
-
-**No Payload**
-
-As there's no payload, you may download vmlinux or u-boot to FW_JUMP_ADDR which
-specified in config.mk or compile commands with GDB. And the execution flow will
-turn to vmlinux or u-boot when opensbi ends.
-
-**Linux Kernel Payload**
-
-You can also choose to use Linux kernel as payload by enabling FW_PAYLOAD=y
-along with specifying FW_PAYLOAD_OFFSET. The kernel image will be embedded in
-the OPENSBI firmware binary, T-head will directly boot into Linux after OpenSBI.

docs/platform/thead-c9xx.md

@@ -0,0 +1,204 @@
+T-HEAD C9xx Series Processors
+=============================
+
+The **C9xx** series processors are high-performance RISC-V architecture
+multi-core processors with AI vector acceleration engine.
+
+For more details, refer [T-HEAD.CN](https://www.t-head.cn/)
+
+To build the platform-specific library and firmware images, provide the
+*PLATFORM=generic* parameter to the top level `make` command.
+
+Platform Options
+----------------
+
+The *T-HEAD C9xx* does not have any platform-specific compile options
+because it use generic platform.
+
+```
+CROSS_COMPILE=riscv64-linux-gnu- PLATFORM=generic FW_PIC=y /usr/bin/make
+```
+
+The *T-HEAD C9xx* DTB provided to OpenSBI generic firmwares will usually have
+"riscv,clint0", "riscv,plic0", "thead,reset-sample" compatible strings.
+
+DTS Example1: (Single core, eg: Allwinner D1 - c906)
+----------------------------------------------------
+
+```
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <3000000>;
+		cpu@0 {
+			device_type = "cpu";
+			reg = <0>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv64imafdcv";
+			mmu-type = "riscv,sv39";
+			cpu0_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+	};
+
+	soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "simple-bus";
+		ranges;
+
+		reset: reset-sample {
+			compatible = "thead,reset-sample";
+			plic-delegate = <0x0 0x101ffffc>;
+		};
+
+		clint0: clint@14000000 {
+			compatible = "riscv,clint0";
+			interrupts-extended = <
+				&cpu0_intc  3 &cpu0_intc  7
+				>;
+			reg = <0x0 0x14000000 0x0 0x04000000>;
+			clint,has-no-64bit-mmio;
+		};
+
+		intc: interrupt-controller@10000000 {
+			#interrupt-cells = <1>;
+			compatible = "riscv,plic0";
+			interrupt-controller;
+			interrupts-extended = <
+				&cpu0_intc  0xffffffff &cpu0_intc  9
+				>;
+			reg = <0x0 0x10000000 0x0 0x04000000>;
+			reg-names = "control";
+			riscv,max-priority = <7>;
+			riscv,ndev = <200>;
+		};
+	}
+```
+
+DTS Example2: (Multi cores with soc reset-regs)
+-----------------------------------------------
+
+```
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <3000000>;
+		cpu@0 {
+			device_type = "cpu";
+			reg = <0>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv64imafdc";
+			mmu-type = "riscv,sv39";
+			cpu0_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+		cpu@1 {
+			device_type = "cpu";
+			reg = <1>;
+			status = "fail";
+			compatible = "riscv";
+			riscv,isa = "rv64imafdc";
+			mmu-type = "riscv,sv39";
+			cpu1_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+		cpu@2 {
+			device_type = "cpu";
+			reg = <2>;
+			status = "fail";
+			compatible = "riscv";
+			riscv,isa = "rv64imafdc";
+			mmu-type = "riscv,sv39";
+			cpu2_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+		cpu@3 {
+			device_type = "cpu";
+			reg = <3>;
+			status = "fail";
+			compatible = "riscv";
+			riscv,isa = "rv64imafdc";
+			mmu-type = "riscv,sv39";
+			cpu3_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+	};
+
+	soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "simple-bus";
+		ranges;
+
+		reset: reset-sample {
+			compatible = "thead,reset-sample";
+			plic-delegate = <0xff 0xd81ffffc>;
+			entry-reg = <0xff 0xff019050>;
+			entry-cnt = <4>;
+			control-reg = <0xff 0xff015004>;
+			control-val = <0x1c>;
+			csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;
+		};
+
+		clint0: clint@ffdc000000 {
+			compatible = "riscv,clint0";
+			interrupts-extended = <
+				&cpu0_intc  3 &cpu0_intc  7
+				&cpu1_intc  3 &cpu1_intc  7
+				&cpu2_intc  3 &cpu2_intc  7
+				&cpu3_intc  3 &cpu3_intc  7
+				&cpu4_intc  3 &cpu4_intc  7
+				>;
+			reg = <0xff 0xdc000000 0x0 0x04000000>;
+			clint,has-no-64bit-mmio;
+		};
+
+		intc: interrupt-controller@ffd8000000 {
+			#interrupt-cells = <1>;
+			compatible = "riscv,plic0";
+			interrupt-controller;
+			interrupts-extended = <
+				&cpu0_intc  0xffffffff &cpu0_intc  9
+				&cpu1_intc  0xffffffff &cpu1_intc  9
+				&cpu2_intc  0xffffffff &cpu2_intc  9
+				&cpu3_intc  0xffffffff &cpu3_intc  9
+				>;
+			reg = <0xff 0xd8000000 0x0 0x04000000>;
+			reg-names = "control";
+			riscv,max-priority = <7>;
+			riscv,ndev = <80>;
+		};
+	}
+```
+
+DTS Example2: (Multi cores with old reset csrs)
+-----------------------------------------------
+```
+	reset: reset-sample {
+		compatible = "thead,reset-sample";
+		plic-delegate = <0xff 0xd81ffffc>;
+		using-csr-reset;
+		csr-copy = <0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc
+			    0x3b0 0x3b1 0x3b2 0x3b3
+			    0x3b4 0x3b5 0x3b6 0x3b7
+			    0x3a0>;
+	};
+```

docs/platform_requirements.md

@@ -0,0 +1,44 @@
+OpenSBI Platform Requirements
+=============================
+
+The RISC-V platform requirements for OpenSBI can change over time
+with advances in RISC-V specifications and ecosystem.
+
+To handle this, we have two types of RISC-V platform requirements:
+
+1. **Base platform requirements** which apply to all OpenSBI releases
+2. **Release specific platform requirements** which apply to a OpenSBI
+   release and later releases
+
+Currently, we don't have any **Release specific platform requirements**
+but such platform requirements will be added in future.
+
+Base Platform Requirements
+--------------------------
+
+The base RISC-V platform requirements for OpenSBI are as follows:
+
+1. At least rv32ima or rv64ima required on all HARTs
+2. At least one HART should have S-mode support because:
+
+     * SBI calls are meant for RISC-V S-mode (Supervisor mode)
+     * OpenSBI implements SBI calls for S-mode software
+
+3. The MTVEC CSR on all HARTs must support direct mode
+4. The PMP CSRs are optional. If PMP CSRs are not implemented then
+   OpenSBI cannot protect M-mode firmware and secured memory regions
+5. The TIME CSR is optional. If TIME CSR is not implemented in
+   hardware then a 64-bit MMIO counter is required to track time
+   and emulate TIME CSR
+6. Hardware support for injecting M-mode software interrupts on
+   a multi-HART platform
+
+The RISC-V extensions not covered by rv32ima or rv64ima are optional
+for OpenSBI. Although, OpenSBI will detect and handle some of these
+optional RISC-V extensions at runtime.
+
+The optional RISC-V extensions handled by OpenSBI at runtime are:
+
+* D-extension: Double precision floating point
+* F-extension: Single precision floating point
+* H-extension: Hypervisor

firmware/external_deps.mk

@@ -7,5 +7,8 @@
 #   Anup Patel <anup.patel@wdc.com>
 #
 
+$(platform_build_dir)/firmware/fw_dynamic.o: $(FW_FDT_PATH)
+$(platform_build_dir)/firmware/fw_jump.o: $(FW_FDT_PATH)
+$(platform_build_dir)/firmware/fw_payload.o: $(FW_FDT_PATH)
+
 $(platform_build_dir)/firmware/fw_payload.o: $(FW_PAYLOAD_PATH_FINAL)
-$(platform_build_dir)/firmware/fw_payload.o: $(FW_PAYLOAD_FDT_PATH)

firmware/fw_base.S

@@ -9,6 +9,7 @@
 
 #include <sbi/riscv_asm.h>
 #include <sbi/riscv_encoding.h>
+#include <sbi/riscv_elf.h>
 #include <sbi/sbi_platform.h>
 #include <sbi/sbi_scratch.h>
 #include <sbi/sbi_trap.h>
@@ -57,39 +58,91 @@ _start:
 	bne	a0, a6, _wait_relocate_copy_done
 _try_lottery:
 	/* Jump to relocation wait loop if we don't get relocation lottery */
-	la	a6, _relocate_lottery
+	lla	a6, _relocate_lottery
 	li	a7, 1
 	amoadd.w a6, a7, (a6)
 	bnez	a6, _wait_relocate_copy_done
 
 	/* Save load address */
-	la	t0, _load_start
-	la	t1, _start
+	lla	t0, _load_start
+	lla	t1, _start
 	REG_S	t1, 0(t0)
 
+#ifdef FW_PIC
+	/* relocate the global table content */
+	lla	t0, _link_start
+	REG_L	t0, 0(t0)
+	/* t1 shall has the address of _start */
+	sub	t2, t1, t0
+	lla	t3, _runtime_offset
+	REG_S	t2, (t3)
+	lla	t0, __rel_dyn_start
+	lla	t1, __rel_dyn_end
+	beq	t0, t1, _relocate_done
+	j	5f
+2:
+	REG_L	t5, -(REGBYTES*2)(t0)	/* t5 <-- relocation info:type */
+	li	t3, R_RISCV_RELATIVE	/* reloc type R_RISCV_RELATIVE */
+	bne	t5, t3, 3f
+	REG_L	t3, -(REGBYTES*3)(t0)
+	REG_L	t5, -(REGBYTES)(t0)	/* t5 <-- addend */
+	add	t5, t5, t2
+	add	t3, t3, t2
+	REG_S	t5, 0(t3)		/* store runtime address to the GOT entry */
+	j	5f
+
+3:
+	lla	t4, __dyn_sym_start
+
+4:
+	REG_L	t5, -(REGBYTES*2)(t0)	/* t5 <-- relocation info:type */
+	srli	t6, t5, SYM_INDEX	/* t6 <--- sym table index */
+	andi	t5, t5, 0xFF		/* t5 <--- relocation type */
+	li	t3, RELOC_TYPE
+	bne	t5, t3, 5f
+
+	/* address R_RISCV_64 or R_RISCV_32 cases*/
+	REG_L	t3, -(REGBYTES*3)(t0)
+	li	t5, SYM_SIZE
+	mul	t6, t6, t5
+	add	s5, t4, t6
+	REG_L	t6, -(REGBYTES)(t0)	/* t0 <-- addend */
+	REG_L	t5, REGBYTES(s5)
+	add	t5, t5, t6
+	add	t5, t5, t2		/* t5 <-- location to fix up in RAM */
+	add	t3, t3, t2		/* t3 <-- location to fix up in RAM */
+	REG_S	t5, 0(t3)		/* store runtime address to the variable */
+
+5:
+	addi	t0, t0, (REGBYTES*3)
+	ble	t0, t1, 2b
+	j	_relocate_done
+_wait_relocate_copy_done:
+	j	_wait_for_boot_hart
+#else
 	/* Relocate if load address != link address */
 _relocate:
-	la	t0, _link_start
+	lla	t0, _link_start
 	REG_L	t0, 0(t0)
-	la	t1, _link_end
+	lla	t1, _link_end
 	REG_L	t1, 0(t1)
-	la	t2, _load_start
+	lla	t2, _load_start
 	REG_L	t2, 0(t2)
 	sub	t3, t1, t0
 	add	t3, t3, t2
 	beq	t0, t2, _relocate_done
-	la	t4, _relocate_done
+	lla	t4, _relocate_done
 	sub	t4, t4, t2
 	add	t4, t4, t0
 	blt	t2, t0, _relocate_copy_to_upper
 _relocate_copy_to_lower:
 	ble	t1, t2, _relocate_copy_to_lower_loop
-	la	t3, _relocate_lottery
+	lla	t3, _relocate_lottery
 	BRANGE	t2, t1, t3, _start_hang
-	la	t3, _boot_status
+	lla	t3, _boot_status
 	BRANGE	t2, t1, t3, _start_hang
-	la	t3, _relocate
-	la	t5, _relocate_done
+	lla	t3, _relocate
+	lla	t5, _relocate_done
 	BRANGE	t2, t1, t3, _start_hang
 	BRANGE	t2, t1, t5, _start_hang
 	BRANGE  t3, t5, t2, _start_hang
@@ -102,12 +155,12 @@ _relocate_copy_to_lower_loop:
 	jr	t4
 _relocate_copy_to_upper:
 	ble	t3, t0, _relocate_copy_to_upper_loop
-	la	t2, _relocate_lottery
+	lla	t2, _relocate_lottery
 	BRANGE	t0, t3, t2, _start_hang
-	la	t2, _boot_status
+	lla	t2, _boot_status
 	BRANGE	t0, t3, t2, _start_hang
-	la	t2, _relocate
-	la	t5, _relocate_done
+	lla	t2, _relocate
+	lla	t5, _relocate_done
 	BRANGE	t0, t3, t2, _start_hang
 	BRANGE	t0, t3, t5, _start_hang
 	BRANGE	t2, t5, t0, _start_hang
@@ -119,12 +172,12 @@ _relocate_copy_to_upper_loop:
 	blt	t0, t1, _relocate_copy_to_upper_loop
 	jr	t4
 _wait_relocate_copy_done:
-	la	t0, _start
-	la	t1, _link_start
+	lla	t0, _start
+	lla	t1, _link_start
 	REG_L	t1, 0(t1)
 	beq	t0, t1, _wait_for_boot_hart
-	la	t2, _boot_status
-	la	t3, _wait_for_boot_hart
+	lla	t2, _boot_status
+	lla	t3, _wait_for_boot_hart
 	sub	t3, t3, t0
 	add	t3, t3, t1
 1:
@@ -137,19 +190,22 @@ _wait_relocate_copy_done:
 	nop
 	bgt     t4, t5, 1b
 	jr	t3
+#endif
 _relocate_done:
 
 	/*
 	 * Mark relocate copy done
 	 * Use _boot_status copy relative to the load address
 	 */
-	la	t0, _boot_status
-	la	t1, _link_start
+	lla	t0, _boot_status
+#ifndef FW_PIC
+	lla	t1, _link_start
 	REG_L	t1, 0(t1)
-	la	t2, _load_start
+	lla	t2, _load_start
 	REG_L	t2, 0(t2)
 	sub	t0, t0, t1
 	add	t0, t0, t2
+#endif
 	li	t1, BOOT_STATUS_RELOCATE_DONE
 	REG_S	t1, 0(t0)
 	fence	rw, rw
@@ -160,16 +216,49 @@ _relocate_done:
 	li	ra, 0
 	call	_reset_regs
 
+	/* Zero-out BSS */
+	lla	s4, _bss_start
+	lla	s5, _bss_end
+_bss_zero:
+	REG_S	zero, (s4)
+	add	s4, s4, __SIZEOF_POINTER__
+	blt	s4, s5, _bss_zero
+
+	/* Setup temporary trap handler */
+	lla	s4, _start_hang
+	csrw	CSR_MTVEC, s4
+
+	/* Setup temporary stack */
+	lla	s4, _fw_end
+	li	s5, (SBI_SCRATCH_SIZE * 2)
+	add	sp, s4, s5
+
 	/* Allow main firmware to save info */
 	MOV_5R	s0, a0, s1, a1, s2, a2, s3, a3, s4, a4
 	call	fw_save_info
 	MOV_5R	a0, s0, a1, s1, a2, s2, a3, s3, a4, s4
 
+#ifdef FW_FDT_PATH
+	/* Override previous arg1 */
+	lla	a1, fw_fdt_bin
+#endif
+
+	/*
+	 * Initialize platform
+	 * Note: The a0 to a4 registers passed to the
+	 * firmware are parameters to this function.
+	 */
+	MOV_5R	s0, a0, s1, a1, s2, a2, s3, a3, s4, a4
+	call	fw_platform_init
+	add	t0, a0, zero
+	MOV_5R	a0, s0, a1, s1, a2, s2, a3, s3, a4, s4
+	add	a1, t0, zero
+
 	/* Preload HART details
 	 * s7 -> HART Count
 	 * s8 -> HART Stack Size
 	 */
-	la	a4, platform
+	lla	a4, platform
 #if __riscv_xlen == 64
 	lwu	s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4)
 	lwu	s8, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(a4)
@@ -179,7 +268,7 @@ _relocate_done:
 #endif
 
 	/* Setup scratch space for all the HARTs*/
-	la	tp, _fw_end
+	lla	tp, _fw_end
 	mul	a5, s7, s8
 	add	tp, tp, a5
 	/* Keep a copy of tp */
@@ -197,8 +286,8 @@ _scratch_init:
 
 	/* Initialize scratch space */
 	/* Store fw_start and fw_size in scratch space */
-	la	a4, _fw_start
-	la	a5, _fw_end
+	lla	a4, _fw_start
+	lla	a5, _fw_end
 	mul	t0, s7, s8
 	add	a5, a5, t0
 	sub	a5, a5, a4
@@ -220,48 +309,32 @@ _scratch_init:
 	REG_S	a0, SBI_SCRATCH_NEXT_MODE_OFFSET(tp)
 	MOV_3R	a0, s0, a1, s1, a2, s2
 	/* Store warm_boot address in scratch space */
-	la	a4, _start_warm
+	lla	a4, _start_warm
 	REG_S	a4, SBI_SCRATCH_WARMBOOT_ADDR_OFFSET(tp)
 	/* Store platform address in scratch space */
-	la	a4, platform
+	lla	a4, platform
 	REG_S	a4, SBI_SCRATCH_PLATFORM_ADDR_OFFSET(tp)
 	/* Store hartid-to-scratch function address in scratch space */
-	la	a4, _hartid_to_scratch
+	lla	a4, _hartid_to_scratch
 	REG_S	a4, SBI_SCRATCH_HARTID_TO_SCRATCH_OFFSET(tp)
+	/* Store trap-exit function address in scratch space */
+	lla	a4, _trap_exit
+	REG_S	a4, SBI_SCRATCH_TRAP_EXIT_OFFSET(tp)
 	/* Clear tmp0 in scratch space */
 	REG_S	zero, SBI_SCRATCH_TMP0_OFFSET(tp)
 	/* Store firmware options in scratch space */
 	MOV_3R	s0, a0, s1, a1, s2, a2
 #ifdef FW_OPTIONS
-	li	a4, FW_OPTIONS
+	li	a0, FW_OPTIONS
 #else
-	add	a4, zero, zero
-#endif
 	call	fw_options
-	or	a4, a4, a0
-	REG_S	a4, SBI_SCRATCH_OPTIONS_OFFSET(tp)
+#endif
+	REG_S	a0, SBI_SCRATCH_OPTIONS_OFFSET(tp)
 	MOV_3R	a0, s0, a1, s1, a2, s2
 	/* Move to next scratch space */
 	add	t1, t1, t2
 	blt	t1, s7, _scratch_init
 
-	/* Zero-out BSS */
-	la	a4, _bss_start
-	la	a5, _bss_end
-_bss_zero:
-	REG_S	zero, (a4)
-	add	a4, a4, __SIZEOF_POINTER__
-	blt	a4, a5, _bss_zero
-
-	/* Override pervious arg1 */
-	MOV_3R	s0, a0, s1, a1, s2, a2
-	call	fw_prev_arg1
-	add	t1, a0, zero
-	MOV_3R	a0, s0, a1, s1, a2, s2
-	beqz	t1, _prev_arg1_override_done
-	add	a1, t1, zero
-_prev_arg1_override_done:
-
 	/*
 	 * Relocate Flatened Device Tree (FDT)
 	 * source FDT address = previous arg1
@@ -326,15 +399,15 @@ _fdt_reloc_done:
 
 	/* mark boot hart done */
 	li	t0, BOOT_STATUS_BOOT_HART_DONE
-	la	t1, _boot_status
+	lla	t1, _boot_status
 	REG_S	t0, 0(t1)
 	fence	rw, rw
 	j	_start_warm
 
-	/* waitting for boot hart done (_boot_status == 2) */
+	/* waiting for boot hart to be done (_boot_status == 2) */
 _wait_for_boot_hart:
 	li	t0, BOOT_STATUS_BOOT_HART_DONE
-	la	t1, _boot_status
+	lla	t1, _boot_status
 	REG_L	t1, 0(t1)
 	/* Reduce the bus traffic so that boot hart may proceed faster */
 	nop
@@ -352,7 +425,7 @@ _start_warm:
 	csrw	CSR_MIP, zero
 
 	/* Find HART count and HART stack size */
-	la	a4, platform
+	lla	a4, platform
 #if __riscv_xlen == 64
 	lwu	s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4)
 	lwu	s8, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(a4)
@@ -383,7 +456,7 @@ _start_warm:
 3:	bge	s6, s7, _start_hang
 
 	/* Find the scratch space based on HART index */
-	la	tp, _fw_end
+	lla	tp, _fw_end
 	mul	a5, s7, s8
 	add	tp, tp, a5
 	mul	a5, s8, s6
@@ -398,11 +471,28 @@ _start_warm:
 	add	sp, tp, zero
 
 	/* Setup trap handler */
-	la	a4, _trap_handler
+	lla	a4, _trap_handler
+#if __riscv_xlen == 32
+	csrr	a5, CSR_MISA
+	srli	a5, a5, ('H' - 'A')
+	andi	a5, a5, 0x1
+	beq	a5, zero, _skip_trap_handler_rv32_hyp
+	lla	a4, _trap_handler_rv32_hyp
+_skip_trap_handler_rv32_hyp:
+#endif
 	csrw	CSR_MTVEC, a4
-	/* Make sure that mtvec is updated */
-1:	csrr	a5, CSR_MTVEC
-	bne	a4, a5, 1b
+
+#if __riscv_xlen == 32
+	/* Override trap exit for H-extension */
+	csrr	a5, CSR_MISA
+	srli	a5, a5, ('H' - 'A')
+	andi	a5, a5, 0x1
+	beq	a5, zero, _skip_trap_exit_rv32_hyp
+	lla	a4, _trap_exit_rv32_hyp
+	csrr	a5, CSR_MSCRATCH
+	REG_S	a4, SBI_SCRATCH_TRAP_EXIT_OFFSET(a5)
+_skip_trap_exit_rv32_hyp:
+#endif
 
 	/* Initialize SBI runtime */
 	csrr	a0, CSR_MSCRATCH
@@ -412,6 +502,10 @@ _start_warm:
 	j	_start_hang
 
 	.align 3
+#ifdef FW_PIC
+_runtime_offset:
+	RISCV_PTR	0
+#endif
 _relocate_lottery:
 	RISCV_PTR	0
 _boot_status:
@@ -419,7 +513,7 @@ _boot_status:
 _load_start:
 	RISCV_PTR	_fw_start
 _link_start:
-	RISCV_PTR	_fw_start
+	RISCV_PTR	FW_TEXT_START
 _link_end:
 	RISCV_PTR	_fw_reloc_end
 
@@ -434,7 +528,7 @@ _hartid_to_scratch:
 	 * t1 -> HART Stack End
 	 * t2 -> Temporary
 	 */
-	la	t2, platform
+	lla	t2, platform
 #if __riscv_xlen == 64
 	lwu	t0, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(t2)
 	lwu	t2, SBI_PLATFORM_HART_COUNT_OFFSET(t2)
@@ -444,7 +538,7 @@ _hartid_to_scratch:
 #endif
 	sub	t2, t2, a1
 	mul	t2, t2, t0
-	la	t1, _fw_end
+	lla	t1, _fw_end
 	add	t1, t1, t2
 	li	t2, SBI_SCRATCH_SIZE
 	sub	a0, t1, t2
@@ -459,43 +553,43 @@ _start_hang:
 
 	.section .entry, "ax", %progbits
 	.align 3
-	.globl _trap_handler
-_trap_handler:
+	.globl fw_platform_init
+	.weak fw_platform_init
+fw_platform_init:
+	add	a0, a1, zero
+	ret
+
+.macro	TRAP_SAVE_AND_SETUP_SP_T0
 	/* Swap TP and MSCRATCH */
 	csrrw	tp, CSR_MSCRATCH, tp
 
 	/* Save T0 in scratch space */
 	REG_S	t0, SBI_SCRATCH_TMP0_OFFSET(tp)
 
-	/* Check which mode we came from */
+	/*
+	 * Set T0 to appropriate exception stack
+	 *
+	 * Came_From_M_Mode = ((MSTATUS.MPP < PRV_M) ? 1 : 0) - 1;
+	 * Exception_Stack = TP ^ (Came_From_M_Mode & (SP ^ TP))
+	 *
+	 * Came_From_M_Mode = 0    ==>    Exception_Stack = TP
+	 * Came_From_M_Mode = -1   ==>    Exception_Stack = SP
+	 */
 	csrr	t0, CSR_MSTATUS
 	srl	t0, t0, MSTATUS_MPP_SHIFT
 	and	t0, t0, PRV_M
-	xori	t0, t0, PRV_M
-	beq	t0, zero, _trap_handler_m_mode
+	slti	t0, t0, PRV_M
+	add	t0, t0, -1
+	xor	sp, sp, tp
+	and	t0, t0, sp
+	xor	sp, sp, tp
+	xor	t0, tp, t0
 
-	/* We came from S-mode or U-mode */
-_trap_handler_s_mode:
-	/* Set T0 to original SP */
-	add	t0, sp, zero
+	/* Save original SP on exception stack */
+	REG_S	sp, (SBI_TRAP_REGS_OFFSET(sp) - SBI_TRAP_REGS_SIZE)(t0)
 
-	/* Setup exception stack */
-	add	sp, tp, -(SBI_TRAP_REGS_SIZE)
-
-	/* Jump to code common for all modes */
-	j	_trap_handler_all_mode
-
-	/* We came from M-mode */
-_trap_handler_m_mode:
-	/* Set T0 to original SP */
-	add	t0, sp, zero
-
-	/* Re-use current SP as exception stack */
-	add	sp, sp, -(SBI_TRAP_REGS_SIZE)
-
-_trap_handler_all_mode:
-	/* Save original SP (from T0) on stack */
-	REG_S	t0, SBI_TRAP_REGS_OFFSET(sp)(sp)
+	/* Set SP to exception stack and make room for trap registers */
+	add	sp, t0, -(SBI_TRAP_REGS_SIZE)
 
 	/* Restore T0 from scratch space */
 	REG_L	t0, SBI_SCRATCH_TMP0_OFFSET(tp)
@@ -505,23 +599,23 @@ _trap_handler_all_mode:
 
 	/* Swap TP and MSCRATCH */
 	csrrw	tp, CSR_MSCRATCH, tp
+.endm
 
+.macro	TRAP_SAVE_MEPC_MSTATUS have_mstatush
 	/* Save MEPC and MSTATUS CSRs */
 	csrr	t0, CSR_MEPC
 	REG_S	t0, SBI_TRAP_REGS_OFFSET(mepc)(sp)
 	csrr	t0, CSR_MSTATUS
 	REG_S	t0, SBI_TRAP_REGS_OFFSET(mstatus)(sp)
-	REG_S	zero, SBI_TRAP_REGS_OFFSET(mstatusH)(sp)
-#if __riscv_xlen == 32
-	csrr	t0, CSR_MISA
-	srli	t0, t0, ('H' - 'A')
-	andi	t0, t0, 0x1
-	beq	t0, zero, _skip_mstatush_save
+	.if \have_mstatush
 	csrr	t0, CSR_MSTATUSH
 	REG_S	t0, SBI_TRAP_REGS_OFFSET(mstatusH)(sp)
-_skip_mstatush_save:
-#endif
+	.else
+	REG_S	zero, SBI_TRAP_REGS_OFFSET(mstatusH)(sp)
+	.endif
+.endm
 
+.macro	TRAP_SAVE_GENERAL_REGS_EXCEPT_SP_T0
 	/* Save all general regisers except SP and T0 */
 	REG_S	zero, SBI_TRAP_REGS_OFFSET(zero)(sp)
 	REG_S	ra, SBI_TRAP_REGS_OFFSET(ra)(sp)
@@ -553,65 +647,113 @@ _skip_mstatush_save:
 	REG_S	t4, SBI_TRAP_REGS_OFFSET(t4)(sp)
 	REG_S	t5, SBI_TRAP_REGS_OFFSET(t5)(sp)
 	REG_S	t6, SBI_TRAP_REGS_OFFSET(t6)(sp)
+.endm
 
+.macro	TRAP_CALL_C_ROUTINE
 	/* Call C routine */
 	add	a0, sp, zero
 	call	sbi_trap_handler
+.endm
 
-	/* Restore all general regisers except SP and T0 */
-	REG_L	ra, SBI_TRAP_REGS_OFFSET(ra)(sp)
-	REG_L	gp, SBI_TRAP_REGS_OFFSET(gp)(sp)
-	REG_L	tp, SBI_TRAP_REGS_OFFSET(tp)(sp)
-	REG_L	t1, SBI_TRAP_REGS_OFFSET(t1)(sp)
-	REG_L	t2, SBI_TRAP_REGS_OFFSET(t2)(sp)
-	REG_L	s0, SBI_TRAP_REGS_OFFSET(s0)(sp)
-	REG_L	s1, SBI_TRAP_REGS_OFFSET(s1)(sp)
-	REG_L	a0, SBI_TRAP_REGS_OFFSET(a0)(sp)
-	REG_L	a1, SBI_TRAP_REGS_OFFSET(a1)(sp)
-	REG_L	a2, SBI_TRAP_REGS_OFFSET(a2)(sp)
-	REG_L	a3, SBI_TRAP_REGS_OFFSET(a3)(sp)
-	REG_L	a4, SBI_TRAP_REGS_OFFSET(a4)(sp)
-	REG_L	a5, SBI_TRAP_REGS_OFFSET(a5)(sp)
-	REG_L	a6, SBI_TRAP_REGS_OFFSET(a6)(sp)
-	REG_L	a7, SBI_TRAP_REGS_OFFSET(a7)(sp)
-	REG_L	s2, SBI_TRAP_REGS_OFFSET(s2)(sp)
-	REG_L	s3, SBI_TRAP_REGS_OFFSET(s3)(sp)
-	REG_L	s4, SBI_TRAP_REGS_OFFSET(s4)(sp)
-	REG_L	s5, SBI_TRAP_REGS_OFFSET(s5)(sp)
-	REG_L	s6, SBI_TRAP_REGS_OFFSET(s6)(sp)
-	REG_L	s7, SBI_TRAP_REGS_OFFSET(s7)(sp)
-	REG_L	s8, SBI_TRAP_REGS_OFFSET(s8)(sp)
-	REG_L	s9, SBI_TRAP_REGS_OFFSET(s9)(sp)
-	REG_L	s10, SBI_TRAP_REGS_OFFSET(s10)(sp)
-	REG_L	s11, SBI_TRAP_REGS_OFFSET(s11)(sp)
-	REG_L	t3, SBI_TRAP_REGS_OFFSET(t3)(sp)
-	REG_L	t4, SBI_TRAP_REGS_OFFSET(t4)(sp)
-	REG_L	t5, SBI_TRAP_REGS_OFFSET(t5)(sp)
-	REG_L	t6, SBI_TRAP_REGS_OFFSET(t6)(sp)
+.macro	TRAP_RESTORE_GENERAL_REGS_EXCEPT_A0_T0
+	/* Restore all general regisers except A0 and T0 */
+	REG_L	ra, SBI_TRAP_REGS_OFFSET(ra)(a0)
+	REG_L	sp, SBI_TRAP_REGS_OFFSET(sp)(a0)
+	REG_L	gp, SBI_TRAP_REGS_OFFSET(gp)(a0)
+	REG_L	tp, SBI_TRAP_REGS_OFFSET(tp)(a0)
+	REG_L	t1, SBI_TRAP_REGS_OFFSET(t1)(a0)
+	REG_L	t2, SBI_TRAP_REGS_OFFSET(t2)(a0)
+	REG_L	s0, SBI_TRAP_REGS_OFFSET(s0)(a0)
+	REG_L	s1, SBI_TRAP_REGS_OFFSET(s1)(a0)
+	REG_L	a1, SBI_TRAP_REGS_OFFSET(a1)(a0)
+	REG_L	a2, SBI_TRAP_REGS_OFFSET(a2)(a0)
+	REG_L	a3, SBI_TRAP_REGS_OFFSET(a3)(a0)
+	REG_L	a4, SBI_TRAP_REGS_OFFSET(a4)(a0)
+	REG_L	a5, SBI_TRAP_REGS_OFFSET(a5)(a0)
+	REG_L	a6, SBI_TRAP_REGS_OFFSET(a6)(a0)
+	REG_L	a7, SBI_TRAP_REGS_OFFSET(a7)(a0)
+	REG_L	s2, SBI_TRAP_REGS_OFFSET(s2)(a0)
+	REG_L	s3, SBI_TRAP_REGS_OFFSET(s3)(a0)
+	REG_L	s4, SBI_TRAP_REGS_OFFSET(s4)(a0)
+	REG_L	s5, SBI_TRAP_REGS_OFFSET(s5)(a0)
+	REG_L	s6, SBI_TRAP_REGS_OFFSET(s6)(a0)
+	REG_L	s7, SBI_TRAP_REGS_OFFSET(s7)(a0)
+	REG_L	s8, SBI_TRAP_REGS_OFFSET(s8)(a0)
+	REG_L	s9, SBI_TRAP_REGS_OFFSET(s9)(a0)
+	REG_L	s10, SBI_TRAP_REGS_OFFSET(s10)(a0)
+	REG_L	s11, SBI_TRAP_REGS_OFFSET(s11)(a0)
+	REG_L	t3, SBI_TRAP_REGS_OFFSET(t3)(a0)
+	REG_L	t4, SBI_TRAP_REGS_OFFSET(t4)(a0)
+	REG_L	t5, SBI_TRAP_REGS_OFFSET(t5)(a0)
+	REG_L	t6, SBI_TRAP_REGS_OFFSET(t6)(a0)
+.endm
 
+.macro	TRAP_RESTORE_MEPC_MSTATUS have_mstatush
 	/* Restore MEPC and MSTATUS CSRs */
-	REG_L	t0, SBI_TRAP_REGS_OFFSET(mepc)(sp)
+	REG_L	t0, SBI_TRAP_REGS_OFFSET(mepc)(a0)
 	csrw	CSR_MEPC, t0
-	REG_L	t0, SBI_TRAP_REGS_OFFSET(mstatus)(sp)
+	REG_L	t0, SBI_TRAP_REGS_OFFSET(mstatus)(a0)
 	csrw	CSR_MSTATUS, t0
-#if __riscv_xlen == 32
-	csrr	t0, CSR_MISA
-	srli	t0, t0, ('H' - 'A')
-	andi	t0, t0, 0x1
-	beq	t0, zero, _skip_mstatush_restore
-	REG_L	t0, SBI_TRAP_REGS_OFFSET(mstatusH)(sp)
+	.if \have_mstatush
+	REG_L	t0, SBI_TRAP_REGS_OFFSET(mstatusH)(a0)
 	csrw	CSR_MSTATUSH, t0
-_skip_mstatush_restore:
-#endif
+	.endif
+.endm
 
+.macro TRAP_RESTORE_A0_T0
 	/* Restore T0 */
-	REG_L	t0, SBI_TRAP_REGS_OFFSET(t0)(sp)
+	REG_L	t0, SBI_TRAP_REGS_OFFSET(t0)(a0)
 
-	/* Restore SP */
-	REG_L	sp, SBI_TRAP_REGS_OFFSET(sp)(sp)
+	/* Restore A0 */
+	REG_L	a0, SBI_TRAP_REGS_OFFSET(a0)(a0)
+.endm
+
+	.section .entry, "ax", %progbits
+	.align 3
+	.globl _trap_handler
+	.globl _trap_exit
+_trap_handler:
+	TRAP_SAVE_AND_SETUP_SP_T0
+
+	TRAP_SAVE_MEPC_MSTATUS 0
+
+	TRAP_SAVE_GENERAL_REGS_EXCEPT_SP_T0
+
+	TRAP_CALL_C_ROUTINE
+
+_trap_exit:
+	TRAP_RESTORE_GENERAL_REGS_EXCEPT_A0_T0
+
+	TRAP_RESTORE_MEPC_MSTATUS 0
+
+	TRAP_RESTORE_A0_T0
 
 	mret
 
+#if __riscv_xlen == 32
+	.section .entry, "ax", %progbits
+	.align 3
+	.globl _trap_handler_rv32_hyp
+	.globl _trap_exit_rv32_hyp
+_trap_handler_rv32_hyp:
+	TRAP_SAVE_AND_SETUP_SP_T0
+
+	TRAP_SAVE_MEPC_MSTATUS 1
+
+	TRAP_SAVE_GENERAL_REGS_EXCEPT_SP_T0
+
+	TRAP_CALL_C_ROUTINE
+
+_trap_exit_rv32_hyp:
+	TRAP_RESTORE_GENERAL_REGS_EXCEPT_A0_T0
+
+	TRAP_RESTORE_MEPC_MSTATUS 1
+
+	TRAP_RESTORE_A0_T0
+
+	mret
+#endif
+
 	.section .entry, "ax", %progbits
 	.align 3
 	.globl _reset_regs
@@ -650,3 +792,14 @@ _reset_regs:
 	csrw CSR_MSCRATCH, 0
 
 	ret
+
+#ifdef FW_FDT_PATH
+	.section .rodata
+	.align 4
+	.globl fw_fdt_bin
+fw_fdt_bin:
+	.incbin FW_FDT_PATH
+#ifdef FW_FDT_PADDING
+	.fill FW_FDT_PADDING, 1, 0
+#endif
+#endif

firmware/fw_base.ldS

@@ -61,6 +61,19 @@
 		PROVIDE(_data_end = .);
 	}
 
+	.dynsym : {
+		PROVIDE(__dyn_sym_start = .);
+		*(.dynsym)
+		PROVIDE(__dyn_sym_end = .);
+	}
+
+	.rela.dyn : {
+		PROVIDE(__rel_dyn_start = .);
+		*(.rela*)
+		. = ALIGN(8);
+		PROVIDE(__rel_dyn_end = .);
+	}
+
 	. = ALIGN(0x1000); /* Ensure next section is page aligned */
 
 	.bss :

firmware/fw_dynamic.S

@@ -54,7 +54,7 @@ fw_boot_hart:
 	 */
 fw_save_info:
 	/* Save next arg1 in 'a1' */
-	la	a4, _dynamic_next_arg1
+	lla	a4, _dynamic_next_arg1
 	REG_S	a1, (a4)
 
 	/* Sanity checks */
@@ -66,13 +66,13 @@ fw_save_info:
 	bgt	a3, a4, _bad_dynamic_info
 
 	/* Save version == 0x1 fields */
-	la	a4, _dynamic_next_addr
+	lla	a4, _dynamic_next_addr
 	REG_L	a3, FW_DYNAMIC_INFO_NEXT_ADDR_OFFSET(a2)
 	REG_S	a3, (a4)
-	la	a4, _dynamic_next_mode
+	lla	a4, _dynamic_next_mode
 	REG_L	a3, FW_DYNAMIC_INFO_NEXT_MODE_OFFSET(a2)
 	REG_S	a3, (a4)
-	la	a4, _dynamic_options
+	lla	a4, _dynamic_options
 	REG_L	a3, FW_DYNAMIC_INFO_OPTIONS_OFFSET(a2)
 	REG_S	a3, (a4)
 
@@ -80,25 +80,12 @@ fw_save_info:
 	li	a4, 0x2
 	REG_L	a3, FW_DYNAMIC_INFO_VERSION_OFFSET(a2)
 	blt	a3, a4, 2f
-	la	a4, _dynamic_boot_hart
+	lla	a4, _dynamic_boot_hart
 	REG_L	a3, FW_DYNAMIC_INFO_BOOT_HART_OFFSET(a2)
 	REG_S	a3, (a4)
 2:
 	ret
 
-	.section .entry, "ax", %progbits
-	.align 3
-	.global fw_prev_arg1
-	/*
-	 * We can only use a0, a1, and a2 registers here.
-	 * The a0, a1, and a2 registers will be same as passed by
-	 * previous booting stage.
-	 * The previous arg1 should be returned in 'a0'.
-	 */
-fw_prev_arg1:
-	add	a0, zero, zero
-	ret
-
 	.section .entry, "ax", %progbits
 	.align 3
 	.global fw_next_arg1
@@ -109,7 +96,7 @@ fw_prev_arg1:
 	 * The next arg1 should be returned in 'a0'.
 	 */
 fw_next_arg1:
-	la	a0, _dynamic_next_arg1
+	lla	a0, _dynamic_next_arg1
 	REG_L	a0, (a0)
 	ret
 
@@ -121,7 +108,7 @@ fw_next_arg1:
 	 * The next address should be returned in 'a0'.
 	 */
 fw_next_addr:
-	la	a0, _dynamic_next_addr
+	lla	a0, _dynamic_next_addr
 	REG_L	a0, (a0)
 	ret
 
@@ -133,7 +120,7 @@ fw_next_addr:
 	 * The next address should be returned in 'a0'
 	 */
 fw_next_mode:
-	la	a0, _dynamic_next_mode
+	lla	a0, _dynamic_next_mode
 	REG_L	a0, (a0)
 	ret
 
@@ -146,7 +133,7 @@ fw_next_mode:
 	 * The next address should be returned in 'a0'.
 	 */
 fw_options:
-	la	a0, _dynamic_options
+	lla	a0, _dynamic_options
 	REG_L	a0, (a0)
 	ret
 

firmware/fw_jump.S

@@ -34,19 +34,6 @@ fw_boot_hart:
 fw_save_info:
 	ret
 
-	.section .entry, "ax", %progbits
-	.align 3
-	.global fw_prev_arg1
-	/*
-	 * We can only use a0, a1, and a2 registers here.
-	 * The a0, a1, and a2 registers will be same as passed by
-	 * previous booting stage.
-	 * The previous arg1 should be returned in 'a0'.
-	 */
-fw_prev_arg1:
-	add	a0, zero, zero
-	ret
-
 	.section .entry, "ax", %progbits
 	.align 3
 	.global fw_next_arg1
@@ -72,7 +59,7 @@ fw_next_arg1:
 	 * The next address should be returned in 'a0'.
 	 */
 fw_next_addr:
-	la	a0, _jump_addr
+	lla	a0, _jump_addr
 	REG_L	a0, (a0)
 	ret
 

firmware/fw_payload.S

@@ -34,23 +34,6 @@ fw_boot_hart:
 fw_save_info:
 	ret
 
-	.section .entry, "ax", %progbits
-	.align 3
-	.global fw_prev_arg1
-	/*
-	 * We can only use a0, a1, and a2 registers here.
-	 * The a0, a1, and a2 registers will be same as passed by
-	 * previous booting stage.
-	 * The previous arg1 should be returned in 'a0'.
-	 */
-fw_prev_arg1:
-#ifdef FW_PAYLOAD_FDT_PATH
-	la	a0, fdt_bin
-#else
-	add	a0, zero, zero
-#endif
-	ret
-
 	.section .entry, "ax", %progbits
 	.align 3
 	.global fw_next_arg1
@@ -76,7 +59,7 @@ fw_next_arg1:
 	 * The next address should be returned in 'a0'.
 	 */
 fw_next_addr:
-	la	a0, payload_bin
+	lla	a0, payload_bin
 	ret
 
 	.section .entry, "ax", %progbits
@@ -102,14 +85,6 @@ fw_options:
 	add	a0, zero, zero
 	ret
 
-#ifdef FW_PAYLOAD_FDT_PATH
-	.section .text, "ax", %progbits
-	.align 4
-	.globl fdt_bin
-fdt_bin:
-	.incbin	FW_PAYLOAD_FDT_PATH
-#endif
-
 	.section .payload, "ax", %progbits
 	.align 4
 	.globl payload_bin

firmware/objects.mk

@@ -13,10 +13,28 @@ firmware-cflags-y +=
 firmware-asflags-y +=
 firmware-ldflags-y +=
 
+ifndef FW_PIC
+FW_PIC := y
+endif
+
+ifeq ($(FW_PIC),y)
+firmware-genflags-y +=	-DFW_PIC
+firmware-asflags-y  +=	-fpic
+firmware-cflags-y   +=	-fPIE -pie
+firmware-ldflags-y  +=  -Wl,--no-dynamic-linker
+endif
+
 ifdef FW_TEXT_START
 firmware-genflags-y += -DFW_TEXT_START=$(FW_TEXT_START)
 endif
 
+ifdef FW_FDT_PATH
+firmware-genflags-y += -DFW_FDT_PATH=\"$(FW_FDT_PATH)\"
+ifdef FW_FDT_PADDING
+firmware-genflags-y += -DFW_FDT_PADDING=$(FW_FDT_PADDING)
+endif
+endif
+
 firmware-bins-$(FW_DYNAMIC) += fw_dynamic.bin
 
 firmware-bins-$(FW_JUMP) += fw_jump.bin
@@ -41,14 +59,6 @@ ifdef FW_PAYLOAD_ALIGN
 firmware-genflags-$(FW_PAYLOAD) += -DFW_PAYLOAD_ALIGN=$(FW_PAYLOAD_ALIGN)
 endif
 
-ifndef FW_PAYLOAD_FDT_PATH
-ifdef FW_PAYLOAD_FDT
-FW_PAYLOAD_FDT_PATH=$(platform_build_dir)/$(FW_PAYLOAD_FDT)
-endif
-endif
-ifdef FW_PAYLOAD_FDT_PATH
-firmware-genflags-$(FW_PAYLOAD) += -DFW_PAYLOAD_FDT_PATH=\"$(FW_PAYLOAD_FDT_PATH)\"
-endif
 ifdef FW_PAYLOAD_FDT_ADDR
 firmware-genflags-$(FW_PAYLOAD) += -DFW_PAYLOAD_FDT_ADDR=$(FW_PAYLOAD_FDT_ADDR)
 endif

firmware/payloads/test_head.S

@@ -28,20 +28,20 @@
 	.globl _start
 _start:
 	/* Pick one hart to run the main boot sequence */
-	la	a3, _hart_lottery
+	lla	a3, _hart_lottery
 	li	a2, 1
 	amoadd.w a3, a2, (a3)
 	bnez	a3, _start_hang
 
 	/* Save a0 and a1 */
-	la	a3, _boot_a0
+	lla	a3, _boot_a0
 	REG_S	a0, 0(a3)
-	la	a3, _boot_a1
+	lla	a3, _boot_a1
 	REG_S	a1, 0(a3)
 
 	/* Zero-out BSS */
-	la	a4, _bss_start
-	la	a5, _bss_end
+	lla	a4, _bss_start
+	lla	a5, _bss_end
 _bss_zero:
 	REG_S	zero, (a4)
 	add	a4, a4, __SIZEOF_POINTER__
@@ -53,18 +53,18 @@ _start_warm:
 	csrw	CSR_SIP, zero
 
 	/* Setup exception vectors */
-	la	a3, _start_hang
+	lla	a3, _start_hang
 	csrw	CSR_STVEC, a3
 
 	/* Setup stack */
-	la	a3, _payload_end
+	lla	a3, _payload_end
 	li	a4, 0x2000
 	add	sp, a3, a4
 
 	/* Jump to C main */
-	la	a3, _boot_a0
+	lla	a3, _boot_a0
 	REG_L	a0, 0(a3)
-	la	a3, _boot_a1
+	lla	a3, _boot_a1
 	REG_L	a1, 0(a3)
 	call	test_main
 

include/sbi/fw_dynamic.h

@@ -40,7 +40,7 @@
 
 /* clang-format on */
 
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
 
 #include <sbi/sbi_types.h>
 

include/sbi/riscv_asm.h

@@ -14,7 +14,7 @@
 
 /* clang-format off */
 
-#ifdef __ASSEMBLY__
+#ifdef __ASSEMBLER__
 #define __ASM_STR(x)	x
 #else
 #define __ASM_STR(x)	#x
@@ -38,7 +38,7 @@
 #define LGREG		__REG_SEL(3, 2)
 
 #if __SIZEOF_POINTER__ == 8
-#ifdef __ASSEMBLY__
+#ifdef __ASSEMBLER__
 #define RISCV_PTR		.dword
 #define RISCV_SZPTR		8
 #define RISCV_LGPTR		3
@@ -48,7 +48,7 @@
 #define RISCV_LGPTR		"3"
 #endif
 #elif __SIZEOF_POINTER__ == 4
-#ifdef __ASSEMBLY__
+#ifdef __ASSEMBLER__
 #define RISCV_PTR		.word
 #define RISCV_SZPTR		4
 #define RISCV_LGPTR		2
@@ -79,7 +79,7 @@
 
 /* clang-format on */
 
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
 
 #define csr_swap(csr, val)                                              \
 	({                                                              \
@@ -157,6 +157,11 @@ void csr_write_num(int csr_num, unsigned long val);
 		__asm__ __volatile__("wfi" ::: "memory"); \
 	} while (0)
 
+#define ebreak()                                             \
+	do {                                              \
+		__asm__ __volatile__("ebreak" ::: "memory"); \
+	} while (0)
+
 /* Get current HART id */
 #define current_hartid()	((unsigned int)csr_read(CSR_MHARTID))
 
@@ -173,26 +178,15 @@ int misa_extension_imp(char ext);
 /* Get MXL field of misa, return -1 on error */
 int misa_xlen(void);
 
-static inline void misa_string(char *out, unsigned int out_sz)
-{
-	unsigned long i;
-
-	for (i = 0; i < 26; i++) {
-		if (misa_extension_imp('A' + i)) {
-			*out = 'A' + i;
-			out++;
-		}
-	}
-	*out = '\0';
-	out++;
-}
+/* Get RISC-V ISA string representation */
+void misa_string(int xlen, char *out, unsigned int out_sz);
 
 int pmp_set(unsigned int n, unsigned long prot, unsigned long addr,
 	    unsigned long log2len);
 
 int pmp_get(unsigned int n, unsigned long *prot_out, unsigned long *addr_out,
-	    unsigned long *size);
+	    unsigned long *log2len);
 
-#endif /* !__ASSEMBLY__ */
+#endif /* !__ASSEMBLER__ */
 
 #endif

include/sbi/riscv_barrier.h

@@ -18,6 +18,9 @@
 #define RISCV_FENCE(p, s) \
 	__asm__ __volatile__ ("fence " #p "," #s : : : "memory")
 
+#define RISCV_FENCE_I \
+	__asm__ __volatile__ ("fence.i" : : : "memory")
+
 /* Read & Write Memory barrier */
 #define mb()			RISCV_FENCE(iorw,iorw)
 

include/sbi/riscv_elf.h

@@ -0,0 +1,14 @@
+#ifndef __RISCV_ELF_H__
+#define __RISCV_ELF_H__
+
+#include <sbi/riscv_asm.h>
+
+#define R_RISCV_32		1
+#define R_RISCV_64		2
+#define R_RISCV_RELATIVE	3
+
+#define RELOC_TYPE		__REG_SEL(R_RISCV_64, R_RISCV_32)
+#define SYM_INDEX		__REG_SEL(0x20,	0x8)
+#define SYM_SIZE		__REG_SEL(0x18,0x10)
+
+#endif

include/sbi/riscv_encoding.h

@@ -61,12 +61,20 @@
 #define SSTATUS64_UXL			MSTATUS_UXL
 #define SSTATUS64_SD			MSTATUS64_SD
 
+#if __riscv_xlen == 64
+#define HSTATUS_VSXL			_UL(0x300000000)
+#define HSTATUS_VSXL_SHIFT		32
+#endif
 #define HSTATUS_VTSR			_UL(0x00400000)
+#define HSTATUS_VTW			_UL(0x00200000)
 #define HSTATUS_VTVM			_UL(0x00100000)
-#define HSTATUS_SP2V			_UL(0x00000200)
-#define HSTATUS_SP2P			_UL(0x00000100)
+#define HSTATUS_VGEIN			_UL(0x0003f000)
+#define HSTATUS_VGEIN_SHIFT		12
+#define HSTATUS_HU			_UL(0x00000200)
+#define HSTATUS_SPVP			_UL(0x00000100)
 #define HSTATUS_SPV			_UL(0x00000080)
-#define HSTATUS_SPRV			_UL(0x00000001)
+#define HSTATUS_GVA			_UL(0x00000040)
+#define HSTATUS_VSBE			_UL(0x00000020)
 
 #define IRQ_S_SOFT			1
 #define IRQ_VS_SOFT			2
@@ -111,6 +119,21 @@
 #define SATP_MODE_SV57			_UL(10)
 #define SATP_MODE_SV64			_UL(11)
 
+#define HGATP_MODE_OFF			_UL(0)
+#define HGATP_MODE_SV32X4		_UL(1)
+#define HGATP_MODE_SV39X4		_UL(8)
+#define HGATP_MODE_SV48X4		_UL(9)
+
+#define HGATP32_MODE_SHIFT		31
+#define HGATP32_VMID_SHIFT		22
+#define HGATP32_VMID_MASK		_UL(0x1FC00000)
+#define HGATP32_PPN			_UL(0x003FFFFF)
+
+#define HGATP64_MODE_SHIFT		60
+#define HGATP64_VMID_SHIFT		44
+#define HGATP64_VMID_MASK		_ULL(0x03FFF00000000000)
+#define HGATP64_PPN			_ULL(0x00000FFFFFFFFFFF)
+
 #define PMP_R				_UL(0x01)
 #define PMP_W				_UL(0x02)
 #define PMP_X				_UL(0x04)
@@ -121,50 +144,54 @@
 #define PMP_L				_UL(0x80)
 
 #define PMP_SHIFT			2
-#define PMP_COUNT			16
-
-/* page table entry (PTE) fields */
-#define PTE_V				_UL(0x001) /* Valid */
-#define PTE_R				_UL(0x002) /* Read */
-#define PTE_W				_UL(0x004) /* Write */
-#define PTE_X				_UL(0x008) /* Execute */
-#define PTE_U				_UL(0x010) /* User */
-#define PTE_G				_UL(0x020) /* Global */
-#define PTE_A				_UL(0x040) /* Accessed */
-#define PTE_D				_UL(0x080) /* Dirty */
-#define PTE_SOFT			_UL(0x300) /* Reserved for Software */
-
-#define PTE_PPN_SHIFT			10
-
-#define PTE_TABLE(PTE)			\
-	(((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)
+#define PMP_COUNT			64
+#if __riscv_xlen == 64
+#define PMP_ADDR_MASK			((_ULL(0x1) << 54) - 1)
+#else
+#define PMP_ADDR_MASK			_UL(0xFFFFFFFF)
+#endif
 
 #if __riscv_xlen == 64
 #define MSTATUS_SD			MSTATUS64_SD
 #define SSTATUS_SD			SSTATUS64_SD
-#define RISCV_PGLEVEL_BITS		9
 #define SATP_MODE			SATP64_MODE
+
+#define HGATP_PPN			HGATP64_PPN
+#define HGATP_VMID_SHIFT		HGATP64_VMID_SHIFT
+#define HGATP_VMID_MASK			HGATP64_VMID_MASK
+#define HGATP_MODE_SHIFT		HGATP64_MODE_SHIFT
 #else
 #define MSTATUS_SD			MSTATUS32_SD
 #define SSTATUS_SD			SSTATUS32_SD
-#define RISCV_PGLEVEL_BITS		10
 #define SATP_MODE			SATP32_MODE
-#endif
-#define RISCV_PGSHIFT			12
-#define RISCV_PGSIZE			(1 << RISCV_PGSHIFT)
 
-#define CSR_USTATUS			0x0
-#define CSR_FFLAGS			0x1
-#define CSR_FRM				0x2
-#define CSR_FCSR			0x3
+#define HGATP_PPN			HGATP32_PPN
+#define HGATP_VMID_SHIFT		HGATP32_VMID_SHIFT
+#define HGATP_VMID_MASK			HGATP32_VMID_MASK
+#define HGATP_MODE_SHIFT		HGATP32_MODE_SHIFT
+#endif
+
+/* ===== User-level CSRs ===== */
+
+/* User Trap Setup (N-extension) */
+#define CSR_USTATUS			0x000
+#define CSR_UIE				0x004
+#define CSR_UTVEC			0x005
+
+/* User Trap Handling (N-extension) */
+#define CSR_USCRATCH			0x040
+#define CSR_UEPC			0x041
+#define CSR_UCAUSE			0x042
+#define CSR_UTVAL			0x043
+#define CSR_UIP				0x044
+
+/* User Floating-point CSRs */
+#define CSR_FFLAGS			0x001
+#define CSR_FRM				0x002
+#define CSR_FCSR			0x003
+
+/* User Counters/Timers */
 #define CSR_CYCLE			0xc00
-#define CSR_UIE				0x4
-#define CSR_UTVEC			0x5
-#define CSR_USCRATCH			0x40
-#define CSR_UEPC			0x41
-#define CSR_UCAUSE			0x42
-#define CSR_UTVAL			0x43
-#define CSR_UIP				0x44
 #define CSR_TIME			0xc01
 #define CSR_INSTRET			0xc02
 #define CSR_HPMCOUNTER3			0xc03
@@ -196,148 +223,6 @@
 #define CSR_HPMCOUNTER29		0xc1d
 #define CSR_HPMCOUNTER30		0xc1e
 #define CSR_HPMCOUNTER31		0xc1f
-#define CSR_SSTATUS			0x100
-#define CSR_SIE				0x104
-#define CSR_STVEC			0x105
-#define CSR_SCOUNTEREN			0x106
-#define CSR_SSCRATCH			0x140
-#define CSR_SEPC			0x141
-#define CSR_SCAUSE			0x142
-#define CSR_STVAL			0x143
-#define CSR_SIP				0x144
-#define CSR_SATP			0x180
-
-#define CSR_HSTATUS			0x600
-#define CSR_HEDELEG			0x602
-#define CSR_HIDELEG			0x603
-#define CSR_HIE				0x604
-#define CSR_HTIMEDELTA			0x605
-#define CSR_HTIMEDELTAH			0x615
-#define CSR_HCOUNTERNEN			0x606
-#define CSR_HGEIE			0x607
-#define CSR_HTVAL			0x643
-#define CSR_HIP				0x644
-#define CSR_HTINST			0x64a
-#define CSR_HGATP			0x680
-#define CSR_HGEIP			0xe07
-
-#define CSR_VSSTATUS			0x200
-#define CSR_VSIE			0x204
-#define CSR_VSTVEC			0x205
-#define CSR_VSSCRATCH			0x240
-#define CSR_VSEPC			0x241
-#define CSR_VSCAUSE			0x242
-#define CSR_VSTVAL			0x243
-#define CSR_VSIP			0x244
-#define CSR_VSATP			0x280
-
-#define CSR_MSTATUS			0x300
-#define CSR_MISA			0x301
-#define CSR_MEDELEG			0x302
-#define CSR_MIDELEG			0x303
-#define CSR_MIE				0x304
-#define CSR_MTVEC			0x305
-#define CSR_MCOUNTEREN			0x306
-#define CSR_MSTATUSH			0x310
-#define CSR_MSCRATCH			0x340
-#define CSR_MEPC			0x341
-#define CSR_MCAUSE			0x342
-#define CSR_MTVAL			0x343
-#define CSR_MIP				0x344
-#define CSR_MTINST			0x34a
-#define CSR_MTVAL2			0x34b
-#define CSR_PMPCFG0			0x3a0
-#define CSR_PMPCFG1			0x3a1
-#define CSR_PMPCFG2			0x3a2
-#define CSR_PMPCFG3			0x3a3
-#define CSR_PMPADDR0			0x3b0
-#define CSR_PMPADDR1			0x3b1
-#define CSR_PMPADDR2			0x3b2
-#define CSR_PMPADDR3			0x3b3
-#define CSR_PMPADDR4			0x3b4
-#define CSR_PMPADDR5			0x3b5
-#define CSR_PMPADDR6			0x3b6
-#define CSR_PMPADDR7			0x3b7
-#define CSR_PMPADDR8			0x3b8
-#define CSR_PMPADDR9			0x3b9
-#define CSR_PMPADDR10			0x3ba
-#define CSR_PMPADDR11			0x3bb
-#define CSR_PMPADDR12			0x3bc
-#define CSR_PMPADDR13			0x3bd
-#define CSR_PMPADDR14			0x3be
-#define CSR_PMPADDR15			0x3bf
-#define CSR_TSELECT			0x7a0
-#define CSR_TDATA1			0x7a1
-#define CSR_TDATA2			0x7a2
-#define CSR_TDATA3			0x7a3
-#define CSR_DCSR			0x7b0
-#define CSR_DPC				0x7b1
-#define CSR_DSCRATCH			0x7b2
-
-#define CSR_MCYCLE			0xb00
-#define CSR_MINSTRET			0xb02
-#define CSR_MHPMCOUNTER3		0xb03
-#define CSR_MHPMCOUNTER4		0xb04
-#define CSR_MHPMCOUNTER5		0xb05
-#define CSR_MHPMCOUNTER6		0xb06
-#define CSR_MHPMCOUNTER7		0xb07
-#define CSR_MHPMCOUNTER8		0xb08
-#define CSR_MHPMCOUNTER9		0xb09
-#define CSR_MHPMCOUNTER10		0xb0a
-#define CSR_MHPMCOUNTER11		0xb0b
-#define CSR_MHPMCOUNTER12		0xb0c
-#define CSR_MHPMCOUNTER13		0xb0d
-#define CSR_MHPMCOUNTER14		0xb0e
-#define CSR_MHPMCOUNTER15		0xb0f
-#define CSR_MHPMCOUNTER16		0xb10
-#define CSR_MHPMCOUNTER17		0xb11
-#define CSR_MHPMCOUNTER18		0xb12
-#define CSR_MHPMCOUNTER19		0xb13
-#define CSR_MHPMCOUNTER20		0xb14
-#define CSR_MHPMCOUNTER21		0xb15
-#define CSR_MHPMCOUNTER22		0xb16
-#define CSR_MHPMCOUNTER23		0xb17
-#define CSR_MHPMCOUNTER24		0xb18
-#define CSR_MHPMCOUNTER25		0xb19
-#define CSR_MHPMCOUNTER26		0xb1a
-#define CSR_MHPMCOUNTER27		0xb1b
-#define CSR_MHPMCOUNTER28		0xb1c
-#define CSR_MHPMCOUNTER29		0xb1d
-#define CSR_MHPMCOUNTER30		0xb1e
-#define CSR_MHPMCOUNTER31		0xb1f
-#define CSR_MHPMEVENT3			0x323
-#define CSR_MHPMEVENT4			0x324
-#define CSR_MHPMEVENT5			0x325
-#define CSR_MHPMEVENT6			0x326
-#define CSR_MHPMEVENT7			0x327
-#define CSR_MHPMEVENT8			0x328
-#define CSR_MHPMEVENT9			0x329
-#define CSR_MHPMEVENT10			0x32a
-#define CSR_MHPMEVENT11			0x32b
-#define CSR_MHPMEVENT12			0x32c
-#define CSR_MHPMEVENT13			0x32d
-#define CSR_MHPMEVENT14			0x32e
-#define CSR_MHPMEVENT15			0x32f
-#define CSR_MHPMEVENT16			0x330
-#define CSR_MHPMEVENT17			0x331
-#define CSR_MHPMEVENT18			0x332
-#define CSR_MHPMEVENT19			0x333
-#define CSR_MHPMEVENT20			0x334
-#define CSR_MHPMEVENT21			0x335
-#define CSR_MHPMEVENT22			0x336
-#define CSR_MHPMEVENT23			0x337
-#define CSR_MHPMEVENT24			0x338
-#define CSR_MHPMEVENT25			0x339
-#define CSR_MHPMEVENT26			0x33a
-#define CSR_MHPMEVENT27			0x33b
-#define CSR_MHPMEVENT28			0x33c
-#define CSR_MHPMEVENT29			0x33d
-#define CSR_MHPMEVENT30			0x33e
-#define CSR_MHPMEVENT31			0x33f
-#define CSR_MVENDORID			0xf11
-#define CSR_MARCHID			0xf12
-#define CSR_MIMPID			0xf13
-#define CSR_MHARTID			0xf14
 #define CSR_CYCLEH			0xc80
 #define CSR_TIMEH			0xc81
 #define CSR_INSTRETH			0xc82
@@ -370,6 +255,203 @@
 #define CSR_HPMCOUNTER29H		0xc9d
 #define CSR_HPMCOUNTER30H		0xc9e
 #define CSR_HPMCOUNTER31H		0xc9f
+
+/* ===== Supervisor-level CSRs ===== */
+
+/* Supervisor Trap Setup */
+#define CSR_SSTATUS			0x100
+#define CSR_SEDELEG			0x102
+#define CSR_SIDELEG			0x103
+#define CSR_SIE				0x104
+#define CSR_STVEC			0x105
+#define CSR_SCOUNTEREN			0x106
+
+/* Supervisor Trap Handling */
+#define CSR_SSCRATCH			0x140
+#define CSR_SEPC			0x141
+#define CSR_SCAUSE			0x142
+#define CSR_STVAL			0x143
+#define CSR_SIP				0x144
+
+/* Supervisor Protection and Translation */
+#define CSR_SATP			0x180
+
+/* ===== Hypervisor-level CSRs ===== */
+
+/* Hypervisor Trap Setup (H-extension) */
+#define CSR_HSTATUS			0x600
+#define CSR_HEDELEG			0x602
+#define CSR_HIDELEG			0x603
+#define CSR_HIE				0x604
+#define CSR_HCOUNTEREN			0x606
+#define CSR_HGEIE			0x607
+
+/* Hypervisor Trap Handling (H-extension) */
+#define CSR_HTVAL			0x643
+#define CSR_HIP				0x644
+#define CSR_HVIP			0x645
+#define CSR_HTINST			0x64a
+#define CSR_HGEIP			0xe12
+
+/* Hypervisor Protection and Translation (H-extension) */
+#define CSR_HGATP			0x680
+
+/* Hypervisor Counter/Timer Virtualization Registers (H-extension) */
+#define CSR_HTIMEDELTA			0x605
+#define CSR_HTIMEDELTAH			0x615
+
+/* Virtual Supervisor Registers (H-extension) */
+#define CSR_VSSTATUS			0x200
+#define CSR_VSIE			0x204
+#define CSR_VSTVEC			0x205
+#define CSR_VSSCRATCH			0x240
+#define CSR_VSEPC			0x241
+#define CSR_VSCAUSE			0x242
+#define CSR_VSTVAL			0x243
+#define CSR_VSIP			0x244
+#define CSR_VSATP			0x280
+
+/* ===== Machine-level CSRs ===== */
+
+/* Machine Information Registers */
+#define CSR_MVENDORID			0xf11
+#define CSR_MARCHID			0xf12
+#define CSR_MIMPID			0xf13
+#define CSR_MHARTID			0xf14
+
+/* Machine Trap Setup */
+#define CSR_MSTATUS			0x300
+#define CSR_MISA			0x301
+#define CSR_MEDELEG			0x302
+#define CSR_MIDELEG			0x303
+#define CSR_MIE				0x304
+#define CSR_MTVEC			0x305
+#define CSR_MCOUNTEREN			0x306
+#define CSR_MSTATUSH			0x310
+
+/* Machine Trap Handling */
+#define CSR_MSCRATCH			0x340
+#define CSR_MEPC			0x341
+#define CSR_MCAUSE			0x342
+#define CSR_MTVAL			0x343
+#define CSR_MIP				0x344
+#define CSR_MTINST			0x34a
+#define CSR_MTVAL2			0x34b
+
+/* Machine Memory Protection */
+#define CSR_PMPCFG0			0x3a0
+#define CSR_PMPCFG1			0x3a1
+#define CSR_PMPCFG2			0x3a2
+#define CSR_PMPCFG3			0x3a3
+#define CSR_PMPCFG4			0x3a4
+#define CSR_PMPCFG5			0x3a5
+#define CSR_PMPCFG6			0x3a6
+#define CSR_PMPCFG7			0x3a7
+#define CSR_PMPCFG8			0x3a8
+#define CSR_PMPCFG9			0x3a9
+#define CSR_PMPCFG10			0x3aa
+#define CSR_PMPCFG11			0x3ab
+#define CSR_PMPCFG12			0x3ac
+#define CSR_PMPCFG13			0x3ad
+#define CSR_PMPCFG14			0x3ae
+#define CSR_PMPCFG15			0x3af
+#define CSR_PMPADDR0			0x3b0
+#define CSR_PMPADDR1			0x3b1
+#define CSR_PMPADDR2			0x3b2
+#define CSR_PMPADDR3			0x3b3
+#define CSR_PMPADDR4			0x3b4
+#define CSR_PMPADDR5			0x3b5
+#define CSR_PMPADDR6			0x3b6
+#define CSR_PMPADDR7			0x3b7
+#define CSR_PMPADDR8			0x3b8
+#define CSR_PMPADDR9			0x3b9
+#define CSR_PMPADDR10			0x3ba
+#define CSR_PMPADDR11			0x3bb
+#define CSR_PMPADDR12			0x3bc
+#define CSR_PMPADDR13			0x3bd
+#define CSR_PMPADDR14			0x3be
+#define CSR_PMPADDR15			0x3bf
+#define CSR_PMPADDR16			0x3c0
+#define CSR_PMPADDR17			0x3c1
+#define CSR_PMPADDR18			0x3c2
+#define CSR_PMPADDR19			0x3c3
+#define CSR_PMPADDR20			0x3c4
+#define CSR_PMPADDR21			0x3c5
+#define CSR_PMPADDR22			0x3c6
+#define CSR_PMPADDR23			0x3c7
+#define CSR_PMPADDR24			0x3c8
+#define CSR_PMPADDR25			0x3c9
+#define CSR_PMPADDR26			0x3ca
+#define CSR_PMPADDR27			0x3cb
+#define CSR_PMPADDR28			0x3cc
+#define CSR_PMPADDR29			0x3cd
+#define CSR_PMPADDR30			0x3ce
+#define CSR_PMPADDR31			0x3cf
+#define CSR_PMPADDR32			0x3d0
+#define CSR_PMPADDR33			0x3d1
+#define CSR_PMPADDR34			0x3d2
+#define CSR_PMPADDR35			0x3d3
+#define CSR_PMPADDR36			0x3d4
+#define CSR_PMPADDR37			0x3d5
+#define CSR_PMPADDR38			0x3d6
+#define CSR_PMPADDR39			0x3d7
+#define CSR_PMPADDR40			0x3d8
+#define CSR_PMPADDR41			0x3d9
+#define CSR_PMPADDR42			0x3da
+#define CSR_PMPADDR43			0x3db
+#define CSR_PMPADDR44			0x3dc
+#define CSR_PMPADDR45			0x3dd
+#define CSR_PMPADDR46			0x3de
+#define CSR_PMPADDR47			0x3df
+#define CSR_PMPADDR48			0x3e0
+#define CSR_PMPADDR49			0x3e1
+#define CSR_PMPADDR50			0x3e2
+#define CSR_PMPADDR51			0x3e3
+#define CSR_PMPADDR52			0x3e4
+#define CSR_PMPADDR53			0x3e5
+#define CSR_PMPADDR54			0x3e6
+#define CSR_PMPADDR55			0x3e7
+#define CSR_PMPADDR56			0x3e8
+#define CSR_PMPADDR57			0x3e9
+#define CSR_PMPADDR58			0x3ea
+#define CSR_PMPADDR59			0x3eb
+#define CSR_PMPADDR60			0x3ec
+#define CSR_PMPADDR61			0x3ed
+#define CSR_PMPADDR62			0x3ee
+#define CSR_PMPADDR63			0x3ef
+
+/* Machine Counters/Timers */
+#define CSR_MCYCLE			0xb00
+#define CSR_MINSTRET			0xb02
+#define CSR_MHPMCOUNTER3		0xb03
+#define CSR_MHPMCOUNTER4		0xb04
+#define CSR_MHPMCOUNTER5		0xb05
+#define CSR_MHPMCOUNTER6		0xb06
+#define CSR_MHPMCOUNTER7		0xb07
+#define CSR_MHPMCOUNTER8		0xb08
+#define CSR_MHPMCOUNTER9		0xb09
+#define CSR_MHPMCOUNTER10		0xb0a
+#define CSR_MHPMCOUNTER11		0xb0b
+#define CSR_MHPMCOUNTER12		0xb0c
+#define CSR_MHPMCOUNTER13		0xb0d
+#define CSR_MHPMCOUNTER14		0xb0e
+#define CSR_MHPMCOUNTER15		0xb0f
+#define CSR_MHPMCOUNTER16		0xb10
+#define CSR_MHPMCOUNTER17		0xb11
+#define CSR_MHPMCOUNTER18		0xb12
+#define CSR_MHPMCOUNTER19		0xb13
+#define CSR_MHPMCOUNTER20		0xb14
+#define CSR_MHPMCOUNTER21		0xb15
+#define CSR_MHPMCOUNTER22		0xb16
+#define CSR_MHPMCOUNTER23		0xb17
+#define CSR_MHPMCOUNTER24		0xb18
+#define CSR_MHPMCOUNTER25		0xb19
+#define CSR_MHPMCOUNTER26		0xb1a
+#define CSR_MHPMCOUNTER27		0xb1b
+#define CSR_MHPMCOUNTER28		0xb1c
+#define CSR_MHPMCOUNTER29		0xb1d
+#define CSR_MHPMCOUNTER30		0xb1e
+#define CSR_MHPMCOUNTER31		0xb1f
 #define CSR_MCYCLEH			0xb80
 #define CSR_MINSTRETH			0xb82
 #define CSR_MHPMCOUNTER3H		0xb83
@@ -402,6 +484,52 @@
 #define CSR_MHPMCOUNTER30H		0xb9e
 #define CSR_MHPMCOUNTER31H		0xb9f
 
+/* Machine Counter Setup */
+#define CSR_MCOUNTINHIBIT		0x320
+#define CSR_MHPMEVENT3			0x323
+#define CSR_MHPMEVENT4			0x324
+#define CSR_MHPMEVENT5			0x325
+#define CSR_MHPMEVENT6			0x326
+#define CSR_MHPMEVENT7			0x327
+#define CSR_MHPMEVENT8			0x328
+#define CSR_MHPMEVENT9			0x329
+#define CSR_MHPMEVENT10			0x32a
+#define CSR_MHPMEVENT11			0x32b
+#define CSR_MHPMEVENT12			0x32c
+#define CSR_MHPMEVENT13			0x32d
+#define CSR_MHPMEVENT14			0x32e
+#define CSR_MHPMEVENT15			0x32f
+#define CSR_MHPMEVENT16			0x330
+#define CSR_MHPMEVENT17			0x331
+#define CSR_MHPMEVENT18			0x332
+#define CSR_MHPMEVENT19			0x333
+#define CSR_MHPMEVENT20			0x334
+#define CSR_MHPMEVENT21			0x335
+#define CSR_MHPMEVENT22			0x336
+#define CSR_MHPMEVENT23			0x337
+#define CSR_MHPMEVENT24			0x338
+#define CSR_MHPMEVENT25			0x339
+#define CSR_MHPMEVENT26			0x33a
+#define CSR_MHPMEVENT27			0x33b
+#define CSR_MHPMEVENT28			0x33c
+#define CSR_MHPMEVENT29			0x33d
+#define CSR_MHPMEVENT30			0x33e
+#define CSR_MHPMEVENT31			0x33f
+
+/* Debug/Trace Registers */
+#define CSR_TSELECT			0x7a0
+#define CSR_TDATA1			0x7a1
+#define CSR_TDATA2			0x7a2
+#define CSR_TDATA3			0x7a3
+
+/* Debug Mode Registers */
+#define CSR_DCSR			0x7b0
+#define CSR_DPC				0x7b1
+#define CSR_DSCRATCH0			0x7b2
+#define CSR_DSCRATCH1			0x7b3
+
+/* ===== Trap/Exception Causes ===== */
+
 #define CAUSE_MISALIGNED_FETCH		0x0
 #define CAUSE_FETCH_ACCESS		0x1
 #define CAUSE_ILLEGAL_INSTRUCTION	0x2
@@ -411,16 +539,19 @@
 #define CAUSE_MISALIGNED_STORE		0x6
 #define CAUSE_STORE_ACCESS		0x7
 #define CAUSE_USER_ECALL		0x8
-#define CAUSE_HYPERVISOR_ECALL		0x9
-#define CAUSE_SUPERVISOR_ECALL		0xa
+#define CAUSE_SUPERVISOR_ECALL		0x9
+#define CAUSE_VIRTUAL_SUPERVISOR_ECALL	0xa
 #define CAUSE_MACHINE_ECALL		0xb
 #define CAUSE_FETCH_PAGE_FAULT		0xc
 #define CAUSE_LOAD_PAGE_FAULT		0xd
 #define CAUSE_STORE_PAGE_FAULT		0xf
 #define CAUSE_FETCH_GUEST_PAGE_FAULT	0x14
 #define CAUSE_LOAD_GUEST_PAGE_FAULT	0x15
+#define CAUSE_VIRTUAL_INST_FAULT	0x16
 #define CAUSE_STORE_GUEST_PAGE_FAULT	0x17
 
+/* ===== Instruction Encodings ===== */
+
 #define INSN_MATCH_LB			0x3
 #define INSN_MASK_LB			0x707f
 #define INSN_MATCH_LH			0x1003

include/sbi/riscv_locks.h

@@ -2,26 +2,37 @@
  * SPDX-License-Identifier: BSD-2-Clause
  *
  * Copyright (c) 2019 Western Digital Corporation or its affiliates.
- *
- * Authors:
- *   Anup Patel <anup.patel@wdc.com>
+ * Copyright (c) 2021 Christoph Müllner <cmuellner@linux.com>
  */
 
 #ifndef __RISCV_LOCKS_H__
 #define __RISCV_LOCKS_H__
 
+#include <sbi/sbi_types.h>
+
+#define TICKET_SHIFT	16
+
 typedef struct {
-	volatile long lock;
-} spinlock_t;
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+       u16 next;
+       u16 owner;
+#else
+       u16 owner;
+       u16 next;
+#endif
+} __aligned(4) spinlock_t;
 
-#define __RISCV_SPIN_UNLOCKED 0
+#define __SPIN_LOCK_UNLOCKED	\
+	(spinlock_t) { 0, 0 }
 
-#define SPIN_LOCK_INIT(_lptr) (_lptr)->lock = __RISCV_SPIN_UNLOCKED
+#define SPIN_LOCK_INIT(x)	\
+	x = __SPIN_LOCK_UNLOCKED
 
-#define SPIN_LOCK_INITIALIZER                  \
-	{                                      \
-		.lock = __RISCV_SPIN_UNLOCKED, \
-	}
+#define SPIN_LOCK_INITIALIZER	\
+	__SPIN_LOCK_UNLOCKED
+
+#define DEFINE_SPIN_LOCK(x)	\
+	spinlock_t SPIN_LOCK_INIT(x)
 
 int spin_lock_check(spinlock_t *lock);
 

include/sbi/sbi_bitops.h

@@ -66,10 +66,8 @@ static inline int ffs(int x)
 		x >>= 2;
 		r += 2;
 	}
-	if (!(x & 1)) {
-		x >>= 1;
+	if (!(x & 1))
 		r += 1;
-	}
 	return r;
 }
 
@@ -148,10 +146,8 @@ static inline int fls(int x)
 		x <<= 2;
 		r -= 2;
 	}
-	if (!(x & 0x80000000u)) {
-		x <<= 1;
+	if (!(x & 0x80000000u))
 		r -= 1;
-	}
 	return r;
 }
 

include/sbi/sbi_console.h

@@ -12,6 +12,17 @@
 
 #include <sbi/sbi_types.h>
 
+struct sbi_console_device {
+	/** Name of the console device */
+	char name[32];
+
+	/** Write a character to the console output */
+	void (*console_putc)(char ch);
+
+	/** Read a character from the console input */
+	int (*console_getc)(void);
+};
+
 #define __printf(a, b) __attribute__((format(printf, a, b)))
 
 bool sbi_isprintable(char ch);
@@ -32,6 +43,10 @@ int __printf(1, 2) sbi_printf(const char *format, ...);
 
 int __printf(1, 2) sbi_dprintf(const char *format, ...);
 
+const struct sbi_console_device *sbi_console_get_device(void);
+
+void sbi_console_set_device(const struct sbi_console_device *dev);
+
 struct sbi_scratch;
 
 int sbi_console_init(struct sbi_scratch *scratch);

include/sbi/sbi_const.h

@@ -22,7 +22,7 @@
 
 /* clang-format off */
 
-#ifdef __ASSEMBLY__
+#ifdef __ASSEMBLER__
 #define _AC(X,Y)	X
 #define _AT(T,X)	X
 #else

include/sbi/sbi_csr_detect.h

@@ -0,0 +1,53 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Atish Patra <atish.patra@wdc.com>
+ */
+
+#ifndef __SBI_CSR_DETECT__H
+#define __SBI_CSR_DETECT__H
+
+#include <sbi/riscv_encoding.h>
+#include <sbi/sbi_hart.h>
+#include <sbi/sbi_trap.h>
+
+#define csr_read_allowed(csr_num, trap)					\
+	({								\
+	register ulong tinfo asm("a3") = (ulong)trap;			\
+	register ulong ttmp asm("a4");					\
+	register ulong mtvec = sbi_hart_expected_trap_addr();		\
+	register ulong ret = 0;						\
+	((struct sbi_trap_info *)(trap))->cause = 0;			\
+	asm volatile(							\
+		"add %[ttmp], %[tinfo], zero\n"				\
+		"csrrw %[mtvec], " STR(CSR_MTVEC) ", %[mtvec]\n"	\
+		"csrr %[ret], %[csr]\n"					\
+		"csrw " STR(CSR_MTVEC) ", %[mtvec]"			\
+	    : [mtvec] "+&r"(mtvec), [tinfo] "+&r"(tinfo),		\
+	      [ttmp] "+&r"(ttmp), [ret] "=&r" (ret)			\
+	    : [csr] "i" (csr_num)					\
+	    : "memory");						\
+	ret;								\
+	})								\
+
+#define csr_write_allowed(csr_num, trap, value)				\
+	({								\
+	register ulong tinfo asm("a3") = (ulong)trap;			\
+	register ulong ttmp asm("a4");					\
+	register ulong mtvec = sbi_hart_expected_trap_addr();		\
+	((struct sbi_trap_info *)(trap))->cause = 0;			\
+	asm volatile(							\
+		"add %[ttmp], %[tinfo], zero\n"				\
+		"csrrw %[mtvec], " STR(CSR_MTVEC) ", %[mtvec]\n"	\
+		"csrw %[csr], %[val]\n"					\
+		"csrw " STR(CSR_MTVEC) ", %[mtvec]"			\
+	    : [mtvec] "+&r"(mtvec),					\
+	      [tinfo] "+&r"(tinfo), [ttmp] "+&r"(ttmp)			\
+	    : [csr] "i" (csr_num), [val] "r" (value)			\
+	    : "memory");						\
+	})								\
+
+#endif

include/sbi/sbi_domain.h

@@ -0,0 +1,189 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel <anup.patel@wdc.com>
+ */
+
+#ifndef __SBI_DOMAIN_H__
+#define __SBI_DOMAIN_H__
+
+#include <sbi/sbi_types.h>
+#include <sbi/sbi_hartmask.h>
+
+struct sbi_scratch;
+
+/** Domain access types */
+enum sbi_domain_access {
+	SBI_DOMAIN_READ = (1UL << 0),
+	SBI_DOMAIN_WRITE = (1UL << 1),
+	SBI_DOMAIN_EXECUTE = (1UL << 2),
+	SBI_DOMAIN_MMIO = (1UL << 3)
+};
+
+/** Representation of OpenSBI domain memory region */
+struct sbi_domain_memregion {
+	/**
+	 * Size of memory region as power of 2
+	 * It has to be minimum 3 and maximum __riscv_xlen
+	 */
+	unsigned long order;
+	/**
+	 * Base address of memory region
+	 * It must be 2^order aligned address
+	 */
+	unsigned long base;
+	/** Flags representing memory region attributes */
+#define SBI_DOMAIN_MEMREGION_READABLE		(1UL << 0)
+#define SBI_DOMAIN_MEMREGION_WRITEABLE		(1UL << 1)
+#define SBI_DOMAIN_MEMREGION_EXECUTABLE		(1UL << 2)
+#define SBI_DOMAIN_MEMREGION_MMODE		(1UL << 3)
+#define SBI_DOMAIN_MEMREGION_ACCESS_MASK	(0xfUL)
+
+#define SBI_DOMAIN_MEMREGION_MMIO		(1UL << 31)
+	unsigned long flags;
+};
+
+/** Maximum number of domains */
+#define SBI_DOMAIN_MAX_INDEX			32
+
+/** Representation of OpenSBI domain */
+struct sbi_domain {
+	/**
+	 * Logical index of this domain
+	 * Note: This set by sbi_domain_finalize() in the coldboot path
+	 */
+	u32 index;
+	/**
+	 * HARTs assigned to this domain
+	 * Note: This set by sbi_domain_init() and sbi_domain_finalize()
+	 * in the coldboot path
+	 */
+	struct sbi_hartmask assigned_harts;
+	/** Name of this domain */
+	char name[64];
+	/** Possible HARTs in this domain */
+	const struct sbi_hartmask *possible_harts;
+	/** Array of memory regions terminated by a region with order zero */
+	struct sbi_domain_memregion *regions;
+	/** HART id of the HART booting this domain */
+	u32 boot_hartid;
+	/** Arg1 (or 'a1' register) of next booting stage for this domain */
+	unsigned long next_arg1;
+	/** Address of next booting stage for this domain */
+	unsigned long next_addr;
+	/** Privilege mode of next booting stage for this domain */
+	unsigned long next_mode;
+	/** Is domain allowed to reset the system */
+	bool system_reset_allowed;
+	/** Is domain allowed to suspend the system */
+	bool system_suspend_allowed;
+};
+
+/** The root domain instance */
+extern struct sbi_domain root;
+
+/** HART id to domain table */
+extern struct sbi_domain *hartid_to_domain_table[];
+
+/** Get pointer to sbi_domain from HART id */
+#define sbi_hartid_to_domain(__hartid) \
+	hartid_to_domain_table[__hartid]
+
+/** Get pointer to sbi_domain for current HART */
+#define sbi_domain_thishart_ptr() \
+	sbi_hartid_to_domain(current_hartid())
+
+/** Index to domain table */
+extern struct sbi_domain *domidx_to_domain_table[];
+
+/** Get pointer to sbi_domain from index */
+#define sbi_index_to_domain(__index) \
+	domidx_to_domain_table[__index]
+
+/** Iterate over each domain */
+#define sbi_domain_for_each(__i, __d) \
+	for ((__i) = 0; ((__d) = sbi_index_to_domain(__i)); (__i)++)
+
+/** Iterate over each memory region of a domain */
+#define sbi_domain_for_each_memregion(__d, __r) \
+	for ((__r) = (__d)->regions; (__r)->order; (__r)++)
+
+/**
+ * Check whether given HART is assigned to specified domain
+ * @param dom pointer to domain
+ * @param hartid the HART ID
+ * @return TRUE if HART is assigned to domain otherwise FALSE
+ */
+bool sbi_domain_is_assigned_hart(const struct sbi_domain *dom, u32 hartid);
+
+/**
+ * Get ulong assigned HART mask for given domain and HART base ID
+ * @param dom pointer to domain
+ * @param hbase the HART base ID
+ * @return ulong possible HART mask
+ * Note: the return ulong mask will be set to zero on failure.
+ */
+ulong sbi_domain_get_assigned_hartmask(const struct sbi_domain *dom,
+				       ulong hbase);
+
+/**
+ * Initialize a domain memory region based on it's physical
+ * address and size.
+ *
+ * @param addr start physical address of memory region
+ * @param size physical size of memory region
+ * @param flags memory region flags
+ * @param reg pointer to memory region being initialized
+ */
+void sbi_domain_memregion_init(unsigned long addr,
+				unsigned long size,
+				unsigned long flags,
+				struct sbi_domain_memregion *reg);
+
+/**
+ * Check whether we can access specified address for given mode and
+ * memory region flags under a domain
+ * @param dom pointer to domain
+ * @param addr the address to be checked
+ * @param mode the privilege mode of access
+ * @param access_flags bitmask of domain access types (enum sbi_domain_access)
+ * @return TRUE if access allowed otherwise FALSE
+ */
+bool sbi_domain_check_addr(const struct sbi_domain *dom,
+			   unsigned long addr, unsigned long mode,
+			   unsigned long access_flags);
+
+/** Dump domain details on the console */
+void sbi_domain_dump(const struct sbi_domain *dom, const char *suffix);
+
+/** Dump all domain details on the console */
+void sbi_domain_dump_all(const char *suffix);
+
+/**
+ * Register a new domain
+ * @param dom pointer to domain
+ * @param assign_mask pointer to HART mask of HARTs assigned to the domain
+ *
+ * @return 0 on success and negative error code on failure
+ */
+int sbi_domain_register(struct sbi_domain *dom,
+			const struct sbi_hartmask *assign_mask);
+
+/**
+ * Add a memory region to the root domain
+ * @param reg pointer to the memory region to be added
+ *
+ * @return 0 on success and negative error code on failure
+ */
+int sbi_domain_root_add_memregion(const struct sbi_domain_memregion *reg);
+
+/** Finalize domain tables and startup non-root domains */
+int sbi_domain_finalize(struct sbi_scratch *scratch, u32 cold_hartid);
+
+/** Initialize domains */
+int sbi_domain_init(struct sbi_scratch *scratch, u32 cold_hartid);
+
+#endif

include/sbi/sbi_ecall.h

@@ -14,7 +14,7 @@
 #include <sbi/sbi_list.h>
 
 #define SBI_ECALL_VERSION_MAJOR		0
-#define SBI_ECALL_VERSION_MINOR		2
+#define SBI_ECALL_VERSION_MINOR		3
 #define SBI_OPENSBI_IMPID		1
 
 struct sbi_trap_regs;
@@ -26,7 +26,8 @@ struct sbi_ecall_extension {
 	unsigned long extid_end;
 	int (* probe)(unsigned long extid, unsigned long *out_val);
 	int (* handle)(unsigned long extid, unsigned long funcid,
-		       unsigned long *args, unsigned long *out_val,
+		       const struct sbi_trap_regs *regs,
+		       unsigned long *out_val,
 		       struct sbi_trap_info *out_trap);
 };
 
@@ -37,6 +38,8 @@ extern struct sbi_ecall_extension ecall_rfence;
 extern struct sbi_ecall_extension ecall_ipi;
 extern struct sbi_ecall_extension ecall_vendor;
 extern struct sbi_ecall_extension ecall_hsm;
+extern struct sbi_ecall_extension ecall_srst;
+extern struct sbi_ecall_extension ecall_susp;
 
 u16 sbi_ecall_version_major(void);
 

include/sbi/sbi_ecall_interface.h

@@ -13,7 +13,7 @@
 /* clang-format off */
 
 /* SBI Extension IDs */
-#define	SBI_EXT_0_1_SET_TIMER			0x0
+#define SBI_EXT_0_1_SET_TIMER			0x0
 #define SBI_EXT_0_1_CONSOLE_PUTCHAR		0x1
 #define SBI_EXT_0_1_CONSOLE_GETCHAR		0x2
 #define SBI_EXT_0_1_CLEAR_IPI			0x3
@@ -27,6 +27,8 @@
 #define SBI_EXT_IPI				0x735049
 #define SBI_EXT_RFENCE				0x52464E43
 #define SBI_EXT_HSM				0x48534D
+#define SBI_EXT_SRST				0x53525354
+#define SBI_EXT_SUSP				0x53555350
 
 /* SBI function IDs for BASE extension*/
 #define SBI_EXT_BASE_GET_SPEC_VERSION		0x0
@@ -36,6 +38,9 @@
 #define SBI_EXT_BASE_GET_MVENDORID		0x4
 #define SBI_EXT_BASE_GET_MARCHID		0x5
 #define SBI_EXT_BASE_GET_MIMPID			0x6
+#define SBI_EXT_BASE_RESET_C906L		0x7
+#define SBI_EXT_BASE_RST_C906L			0x8
+#define SBI_EXT_BASE_UNRST_C906L		0x9
 
 /* SBI function IDs for TIME extension*/
 #define SBI_EXT_TIME_SET_TIMER			0x0
@@ -47,26 +52,75 @@
 #define SBI_EXT_RFENCE_REMOTE_FENCE_I		0x0
 #define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA	0x1
 #define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID	0x2
-#define SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA	0x3
-#define SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID	0x4
-#define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA	0x5
-#define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID	0x6
+#define SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID	0x3
+#define SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA	0x4
+#define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID	0x5
+#define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA	0x6
 
 /* SBI function IDs for HSM extension */
 #define SBI_EXT_HSM_HART_START			0x0
 #define SBI_EXT_HSM_HART_STOP			0x1
 #define SBI_EXT_HSM_HART_GET_STATUS		0x2
+#define SBI_EXT_HSM_HART_SUSPEND		0x3
 
-#define SBI_HSM_HART_STATUS_STARTED		0x0
-#define SBI_HSM_HART_STATUS_STOPPED		0x1
-#define SBI_HSM_HART_STATUS_START_PENDING	0x2
-#define SBI_HSM_HART_STATUS_STOP_PENDING	0x3
+#define SBI_HSM_STATE_STARTED			0x0
+#define SBI_HSM_STATE_STOPPED			0x1
+#define SBI_HSM_STATE_START_PENDING		0x2
+#define SBI_HSM_STATE_STOP_PENDING		0x3
+#define SBI_HSM_STATE_SUSPENDED			0x4
+#define SBI_HSM_STATE_SUSPEND_PENDING		0x5
+#define SBI_HSM_STATE_RESUME_PENDING		0x6
+
+#define SBI_HSM_SUSP_BASE_MASK			0x7fffffff
+#define SBI_HSM_SUSP_NON_RET_BIT		0x80000000
+#define SBI_HSM_SUSP_PLAT_BASE			0x10000000
+
+#define SBI_HSM_SUSPEND_RET_DEFAULT		0x00000000
+#define SBI_HSM_SUSPEND_RET_PLATFORM		SBI_HSM_SUSP_PLAT_BASE
+#define SBI_HSM_SUSPEND_RET_LAST		SBI_HSM_SUSP_BASE_MASK
+#define SBI_HSM_SUSPEND_NON_RET_DEFAULT		SBI_HSM_SUSP_NON_RET_BIT
+#define SBI_HSM_SUSPEND_NON_RET_PLATFORM	(SBI_HSM_SUSP_NON_RET_BIT | \
+						 SBI_HSM_SUSP_PLAT_BASE)
+#define SBI_HSM_SUSPEND_NON_RET_LAST		(SBI_HSM_SUSP_NON_RET_BIT | \
+						 SBI_HSM_SUSP_BASE_MASK)
+
+/* SBI function IDs for SRST extension */
+#define SBI_EXT_SRST_RESET			0x0
+
+#define SBI_SRST_RESET_TYPE_SHUTDOWN		0x0
+#define SBI_SRST_RESET_TYPE_COLD_REBOOT	0x1
+#define SBI_SRST_RESET_TYPE_WARM_REBOOT	0x2
+#define SBI_SRST_RESET_TYPE_LAST	SBI_SRST_RESET_TYPE_WARM_REBOOT
+
+#define SBI_SRST_RESET_REASON_NONE	0x0
+#define SBI_SRST_RESET_REASON_SYSFAIL	0x1
 
 #define SBI_SPEC_VERSION_MAJOR_OFFSET		24
 #define SBI_SPEC_VERSION_MAJOR_MASK		0x7f
 #define SBI_SPEC_VERSION_MINOR_MASK		0xffffff
 #define SBI_EXT_VENDOR_START			0x09000000
 #define SBI_EXT_VENDOR_END			0x09FFFFFF
+#define SBI_EXT_FIRMWARE_START			0x0A000000
+#define SBI_EXT_FIRMWARE_END			0x0AFFFFFF
+
+/* SBI return error codes */
+#define SBI_SUCCESS				0
+#define SBI_ERR_FAILED				-1
+#define SBI_ERR_NOT_SUPPORTED			-2
+#define SBI_ERR_INVALID_PARAM			-3
+#define SBI_ERR_DENIED				-4
+#define SBI_ERR_INVALID_ADDRESS			-5
+#define SBI_ERR_ALREADY_AVAILABLE		-6
+
+/* SBI function IDs for SUSP extension */
+#define SBI_EXT_SUSP_SUSPEND                   0x0
+
+#define SBI_SUSP_SLEEP_TYPE_SUSPEND            0x0
+#define SBI_SUSP_SLEEP_TYPE_LAST               SBI_SUSP_SLEEP_TYPE_SUSPEND
+#define SBI_SUSP_PLATFORM_SLEEP_START          0x80000000
+
+#define SBI_LAST_ERR				SBI_ERR_ALREADY_AVAILABLE
+
 /* clang-format on */
 
 #endif

include/sbi/sbi_error.h

@@ -10,25 +10,28 @@
 #ifndef __SBI_ERROR_H__
 #define __SBI_ERROR_H__
 
+#include <sbi/sbi_ecall_interface.h>
+
 /* clang-format off */
 
 #define SBI_OK			0
-#define SBI_EFAIL		-1
-#define SBI_ENOTSUPP		-2
-#define SBI_EINVAL		-3
-#define SBI_DENIED		-4
-#define SBI_INVALID_ADDR	-5
-#define SBI_ENODEV		-6
-#define SBI_ENOSYS		-7
-#define SBI_ETIMEDOUT		-8
-#define SBI_EIO			-9
-#define SBI_EILL		-10
-#define SBI_ENOSPC		-11
-#define SBI_ENOMEM		-12
-#define SBI_ETRAP		-13
-#define SBI_EUNKNOWN		-14
-#define SBI_ENOENT		-15
-#define SBI_EALREADY_STARTED	-16
+#define SBI_EFAIL		SBI_ERR_FAILED
+#define SBI_ENOTSUPP		SBI_ERR_NOT_SUPPORTED
+#define SBI_EINVAL		SBI_ERR_INVALID_PARAM
+#define SBI_EDENIED		SBI_ERR_DENIED
+#define SBI_EINVALID_ADDR	SBI_ERR_INVALID_ADDRESS
+#define SBI_EALREADY		SBI_ERR_ALREADY_AVAILABLE
+
+#define SBI_ENODEV		-1000
+#define SBI_ENOSYS		-1001
+#define SBI_ETIMEDOUT		-1002
+#define SBI_EIO			-1003
+#define SBI_EILL		-1004
+#define SBI_ENOSPC		-1005
+#define SBI_ENOMEM		-1006
+#define SBI_ETRAP		-1007
+#define SBI_EUNKNOWN		-1008
+#define SBI_ENOENT		-1009
 
 /* clang-format on */
 

include/sbi/sbi_hart.h

@@ -12,20 +12,40 @@
 
 #include <sbi/sbi_types.h>
 
+/** Possible feature flags of a hart */
+enum sbi_hart_features {
+	/** Hart has S-mode counter enable */
+	SBI_HART_HAS_SCOUNTEREN = (1 << 0),
+	/** Hart has M-mode counter enable */
+	SBI_HART_HAS_MCOUNTEREN = (1 << 1),
+	/** HART has timer csr implementation in hardware */
+	SBI_HART_HAS_TIME = (1 << 2),
+
+	/** Last index of Hart features*/
+	SBI_HART_HAS_LAST_FEATURE = SBI_HART_HAS_TIME,
+};
+
 struct sbi_scratch;
 
-int sbi_hart_init(struct sbi_scratch *scratch, u32 hartid, bool cold_boot);
+int sbi_hart_reinit(struct sbi_scratch *scratch);
+int sbi_hart_init(struct sbi_scratch *scratch, bool cold_boot);
 
-extern void (*sbi_hart_unpriv_trap)(void);
-static inline ulong sbi_hart_unpriv_trap_addr(void)
+extern void (*sbi_hart_expected_trap)(void);
+static inline ulong sbi_hart_expected_trap_addr(void)
 {
-	return (ulong)sbi_hart_unpriv_trap;
+	return (ulong)sbi_hart_expected_trap;
 }
 
-void sbi_hart_delegation_dump(struct sbi_scratch *scratch);
-void sbi_hart_pmp_dump(struct sbi_scratch *scratch);
-int  sbi_hart_pmp_check_addr(struct sbi_scratch *scratch, unsigned long daddr,
-			     unsigned long attr);
+unsigned int sbi_hart_mhpm_count(struct sbi_scratch *scratch);
+void sbi_hart_delegation_dump(struct sbi_scratch *scratch,
+			      const char *prefix, const char *suffix);
+unsigned int sbi_hart_pmp_count(struct sbi_scratch *scratch);
+unsigned long sbi_hart_pmp_granularity(struct sbi_scratch *scratch);
+unsigned int sbi_hart_pmp_addrbits(struct sbi_scratch *scratch);
+int sbi_hart_pmp_configure(struct sbi_scratch *scratch);
+bool sbi_hart_has_feature(struct sbi_scratch *scratch, unsigned long feature);
+void sbi_hart_get_features_str(struct sbi_scratch *scratch,
+			       char *features_str, int nfstr);
 
 void __attribute__((noreturn)) sbi_hart_hang(void);
 

include/sbi/sbi_hartmask.h

@@ -67,7 +67,7 @@ static inline void sbi_hartmask_clear_hart(u32 h, struct sbi_hartmask *m)
  * @param h HART id to test
  * @param m the hartmask pointer
  */
-static inline int sbi_hartmask_test_hart(u32 h, struct sbi_hartmask *m)
+static inline int sbi_hartmask_test_hart(u32 h, const struct sbi_hartmask *m)
 {
 	if (h < SBI_HARTMASK_MAX_BITS)
 		return __test_bit(h, m->bits);

include/sbi/sbi_hfence.h

@@ -10,8 +10,9 @@
 
 #ifndef __SBI_FENCE_H__
 #define __SBI_FENCE_H__
+
 /** Invalidate Stage2 TLBs for given VMID and guest physical address */
-void __sbi_hfence_gvma_vmid_gpa(unsigned long vmid, unsigned long gpa);
+void __sbi_hfence_gvma_vmid_gpa(unsigned long gpa, unsigned long vmid);
 
 /** Invalidate Stage2 TLBs for given VMID */
 void __sbi_hfence_gvma_vmid(unsigned long vmid);
@@ -23,7 +24,7 @@ void __sbi_hfence_gvma_gpa(unsigned long gpa);
 void __sbi_hfence_gvma_all(void);
 
 /** Invalidate unified TLB entries for given asid and guest virtual address */
-void __sbi_hfence_vvma_asid_va(unsigned long asid, unsigned long va);
+void __sbi_hfence_vvma_asid_va(unsigned long va, unsigned long asid);
 
 /** Invalidate unified TLB entries for given ASID for a guest*/
 void __sbi_hfence_vvma_asid(unsigned long asid);
@@ -33,4 +34,5 @@ void __sbi_hfence_vvma_va(unsigned long va);
 
 /** Invalidate all possible Stage2 TLBs */
 void __sbi_hfence_vvma_all(void);
+
 #endif

include/sbi/sbi_hsm.h

@@ -12,25 +12,58 @@
 
 #include <sbi/sbi_types.h>
 
-/** Hart state values **/
-#define SBI_HART_STOPPED	0
-#define SBI_HART_STOPPING	1
-#define SBI_HART_STARTING	2
-#define SBI_HART_STARTED	3
-#define SBI_HART_UNKNOWN	4
+/** Hart state managment device */
+struct sbi_hsm_device {
+	/** Name of the hart state managment device */
+	char name[32];
 
+	/** Start (or power-up) the given hart */
+	int (*hart_start)(u32 hartid, ulong saddr);
+
+	/**
+	 * Stop (or power-down) the current hart from running. This call
+	 * doesn't expect to return if success.
+	 */
+	int (*hart_stop)(void);
+
+	/**
+	 * Put the current hart in platform specific suspend (or low-power)
+	 * state.
+	 *
+	 * For successful retentive suspend, the call will return 0 when
+	 * the hart resumes normal execution.
+	 *
+	 * For successful non-retentive suspend, the hart will resume from
+	 * specified resume address
+	 */
+	int (*hart_suspend)(u32 suspend_type, ulong raddr);
+};
+
+struct sbi_domain;
 struct sbi_scratch;
 
+const struct sbi_hsm_device *sbi_hsm_get_device(void);
+
+void sbi_hsm_set_device(const struct sbi_hsm_device *dev);
+
 int sbi_hsm_init(struct sbi_scratch *scratch, u32 hartid, bool cold_boot);
 void __noreturn sbi_hsm_exit(struct sbi_scratch *scratch);
 
-int sbi_hsm_hart_start(struct sbi_scratch *scratch, u32 hartid,
-		       ulong saddr, ulong priv);
+int sbi_hsm_hart_start(struct sbi_scratch *scratch,
+		       const struct sbi_domain *dom,
+		       u32 hartid, ulong saddr, ulong smode, ulong priv);
 int sbi_hsm_hart_stop(struct sbi_scratch *scratch, bool exitnow);
-int sbi_hsm_hart_get_state(u32 hartid);
-int sbi_hsm_hart_state_to_status(int state);
-bool sbi_hsm_hart_started(u32 hartid);
-int sbi_hsm_hart_started_mask(ulong hbase, ulong *out_hmask);
+void sbi_hsm_hart_resume_start(struct sbi_scratch *scratch);
+void sbi_hsm_hart_resume_finish(struct sbi_scratch *scratch);
+int sbi_hsm_hart_suspend(struct sbi_scratch *scratch, u32 suspend_type,
+			 ulong raddr, ulong rmode, ulong priv);
+int sbi_hsm_hart_change_state(struct sbi_scratch *scratch, long oldstate,
+				long newstate);
+int __sbi_hsm_hart_get_state(u32 hartid);
+int sbi_hsm_hart_get_state(const struct sbi_domain *dom, u32 hartid);
+int sbi_hsm_hart_interruptible_mask(const struct sbi_domain *dom,
+				    ulong hbase, ulong *out_hmask);
+void __sbi_hsm_suspend_non_ret_save(struct sbi_scratch *scratch);
 void sbi_hsm_prepare_next_jump(struct sbi_scratch *scratch, u32 hartid);
 
 #endif

include/sbi/sbi_ipi.h

@@ -18,6 +18,18 @@
 
 /* clang-format on */
 
+/** IPI hardware device */
+struct sbi_ipi_device {
+	/** Name of the IPI device */
+	char name[32];
+
+	/** Send IPI to a target HART */
+	void (*ipi_send)(u32 target_hart);
+
+	/** Clear IPI for a target HART */
+	void (*ipi_clear)(u32 target_hart);
+};
+
 struct sbi_scratch;
 
 /** IPI event operations or callbacks */
@@ -63,6 +75,12 @@ int sbi_ipi_send_halt(ulong hmask, ulong hbase);
 
 void sbi_ipi_process(void);
 
+void sbi_ipi_raw_send(u32 target_hart);
+
+const struct sbi_ipi_device *sbi_ipi_get_device(void);
+
+void sbi_ipi_set_device(const struct sbi_ipi_device *dev);
+
 int sbi_ipi_init(struct sbi_scratch *scratch, bool cold_boot);
 
 void sbi_ipi_exit(struct sbi_scratch *scratch);

include/sbi/sbi_math.h

@@ -0,0 +1,15 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Atish Patra <atish.patra@wdc.com>
+ */
+
+#ifndef __SBI_MATH_H__
+#define __SBI_MATH_H__
+
+unsigned long log2roundup(unsigned long x);
+
+#endif

include/sbi/sbi_platform.h

@@ -38,37 +38,29 @@
 
 #define SBI_PLATFORM_TLB_RANGE_FLUSH_LIMIT_DEFAULT		(1UL << 12)
 
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
 
-#include <sbi/sbi_ecall.h>
+#include <sbi/sbi_ecall_interface.h>
 #include <sbi/sbi_error.h>
 #include <sbi/sbi_scratch.h>
-#include <sbi/sbi_trap.h>
 #include <sbi/sbi_version.h>
 
+struct sbi_domain_memregion;
+struct sbi_trap_info;
+struct sbi_trap_regs;
+
 /** Possible feature flags of a platform */
 enum sbi_platform_features {
-	/** Platform has timer value */
-	SBI_PLATFORM_HAS_TIMER_VALUE = (1 << 0),
-	/** Platform has HART hotplug support */
-	SBI_PLATFORM_HAS_HART_HOTPLUG = (1 << 1),
-	/** Platform has PMP support */
-	SBI_PLATFORM_HAS_PMP = (1 << 2),
-	/** Platform has S-mode counter enable */
-	SBI_PLATFORM_HAS_SCOUNTEREN = (1 << 3),
-	/** Platform has M-mode counter enable */
-	SBI_PLATFORM_HAS_MCOUNTEREN = (1 << 4),
 	/** Platform has fault delegation support */
-	SBI_PLATFORM_HAS_MFAULTS_DELEGATION = (1 << 5),
-	/** Platform has custom secondary hart booting support */
-	SBI_PLATFORM_HAS_HART_SECONDARY_BOOT = (1 << 6),
+	SBI_PLATFORM_HAS_MFAULTS_DELEGATION = (1 << 1),
+
+	/** Last index of Platform features*/
+	SBI_PLATFORM_HAS_LAST_FEATURE = SBI_PLATFORM_HAS_MFAULTS_DELEGATION,
 };
 
 /** Default feature set for a platform */
 #define SBI_PLATFORM_DEFAULT_FEATURES                                \
-	(SBI_PLATFORM_HAS_TIMER_VALUE | SBI_PLATFORM_HAS_PMP |       \
-	 SBI_PLATFORM_HAS_SCOUNTEREN | SBI_PLATFORM_HAS_MCOUNTEREN | \
-	 SBI_PLATFORM_HAS_MFAULTS_DELEGATION)
+	(SBI_PLATFORM_HAS_MFAULTS_DELEGATION)
 
 /** Platform functions */
 struct sbi_platform_operations {
@@ -94,19 +86,9 @@ struct sbi_platform_operations {
 	 */
 	int (*misa_get_xlen)(void);
 
-	/** Get number of PMP regions for given HART */
-	u32 (*pmp_region_count)(u32 hartid);
-	/**
-	 * Get PMP regions details (namely: protection, base address,
-	 * and size) for given HART
-	 */
-	int (*pmp_region_info)(u32 hartid, u32 index, ulong *prot, ulong *addr,
-			       ulong *log2size);
+	/** Initialize (or populate) domains for the platform */
+	int (*domains_init)(void);
 
-	/** Write a character to the platform console output */
-	void (*console_putc)(char ch);
-	/** Read a character from the platform console input */
-	int (*console_getc)(void);
 	/** Initialize the platform console */
 	int (*console_init)(void);
 
@@ -115,10 +97,6 @@ struct sbi_platform_operations {
 	/** Exit the platform interrupt controller for current HART */
 	void (*irqchip_exit)(void);
 
-	/** Send IPI to a target HART */
-	void (*ipi_send)(u32 target_hart);
-	/** Clear IPI for a target HART */
-	void (*ipi_clear)(u32 target_hart);
 	/** Initialize IPI for current HART */
 	int (*ipi_init)(bool cold_boot);
 	/** Exit IPI for current HART */
@@ -127,38 +105,19 @@ struct sbi_platform_operations {
 	/** Get tlb flush limit value **/
 	u64 (*get_tlbr_flush_limit)(void);
 
-	/** Get platform timer value */
-	u64 (*timer_value)(void);
-	/** Start platform timer event for current HART */
-	void (*timer_event_start)(u64 next_event);
-	/** Stop platform timer event for current HART */
-	void (*timer_event_stop)(void);
 	/** Initialize platform timer for current HART */
 	int (*timer_init)(bool cold_boot);
 	/** Exit platform timer for current HART */
 	void (*timer_exit)(void);
 
-	/** Bringup the given hart */
-	int (*hart_start)(u32 hartid, ulong saddr);
-	/**
-	 * Stop the current hart from running. This call doesn't expect to
-	 * return if success.
-	 */
-	int (*hart_stop)(void);
-
-	/** Reboot the platform */
-	int (*system_reboot)(u32 type);
-	/** Shutdown or poweroff the platform */
-	int (*system_shutdown)(u32 type);
-
 	/** platform specific SBI extension implementation probe function */
 	int (*vendor_ext_check)(long extid);
 	/** platform specific SBI extension implementation provider */
 	int (*vendor_ext_provider)(long extid, long funcid,
-				   unsigned long *args,
+				   const struct sbi_trap_regs *regs,
 				   unsigned long *out_value,
 				   struct sbi_trap_info *out_trap);
-} __packed;
+};
 
 /** Platform default per-HART stack size for exception/interrupt handling */
 #define SBI_PLATFORM_DEFAULT_HART_STACK_SIZE	8192
@@ -205,7 +164,7 @@ struct sbi_platform {
 	 * 2. HART id < SBI_HARTMASK_MAX_BITS
 	 */
 	const u32 *hart_index2id;
-} __packed;
+};
 
 /** Get pointer to sbi_platform for sbi_scratch pointer */
 #define sbi_platform_ptr(__s) \
@@ -217,26 +176,31 @@ struct sbi_platform {
 #define sbi_platform_ops(__p) \
 	((const struct sbi_platform_operations *)(__p)->platform_ops_addr)
 
-/** Check whether the platform supports timer value */
-#define sbi_platform_has_timer_value(__p) \
-	((__p)->features & SBI_PLATFORM_HAS_TIMER_VALUE)
-/** Check whether the platform supports HART hotplug */
-#define sbi_platform_has_hart_hotplug(__p) \
-	((__p)->features & SBI_PLATFORM_HAS_HART_HOTPLUG)
-/** Check whether the platform has PMP support */
-#define sbi_platform_has_pmp(__p) ((__p)->features & SBI_PLATFORM_HAS_PMP)
-/** Check whether the platform supports scounteren CSR */
-#define sbi_platform_has_scounteren(__p) \
-	((__p)->features & SBI_PLATFORM_HAS_SCOUNTEREN)
-/** Check whether the platform supports mcounteren CSR */
-#define sbi_platform_has_mcounteren(__p) \
-	((__p)->features & SBI_PLATFORM_HAS_MCOUNTEREN)
 /** Check whether the platform supports fault delegation */
 #define sbi_platform_has_mfaults_delegation(__p) \
 	((__p)->features & SBI_PLATFORM_HAS_MFAULTS_DELEGATION)
-/** Check whether the platform supports custom secondary hart booting support */
-#define sbi_platform_has_hart_secondary_boot(__p) \
-	((__p)->features & SBI_PLATFORM_HAS_HART_SECONDARY_BOOT)
+
+/**
+ * Get HART index for the given HART
+ *
+ * @param plat pointer to struct sbi_platform
+ * @param hartid HART ID
+ *
+ * @return 0 <= value < hart_count for valid HART otherwise -1U
+ */
+u32 sbi_platform_hart_index(const struct sbi_platform *plat, u32 hartid);
+
+/**
+ * Get the platform features in string format
+ *
+ * @param plat pointer to struct sbi_platform
+ * @param features_str pointer to a char array where the features string will be
+ *		       updated
+ * @param nfstr length of the features_str. The feature string will be truncated
+ *		if nfstr is not long enough.
+ */
+void sbi_platform_get_features_str(const struct sbi_platform *plat,
+				   char *features_str, int nfstr);
 
 /**
  * Get name of the platform
@@ -252,6 +216,21 @@ static inline const char *sbi_platform_name(const struct sbi_platform *plat)
 	return "Unknown";
 }
 
+/**
+ * Get the platform features
+ *
+ * @param plat pointer to struct sbi_platform
+ *
+ * @return the features value currently set for the given platform
+ */
+static inline unsigned long sbi_platform_get_features(
+						const struct sbi_platform *plat)
+{
+	if (plat)
+		return plat->features;
+	return 0;
+}
+
 /**
  * Get platform specific tlb range flush maximum value. Any request with size
  * higher than this is upgraded to a full flush.
@@ -296,32 +275,6 @@ static inline u32 sbi_platform_hart_stack_size(const struct sbi_platform *plat)
 	return 0;
 }
 
-/**
- * Get HART index for the given HART
- *
- * @param plat pointer to struct sbi_platform
- * @param hartid HART ID
- *
- * @return 0 <= value < hart_count for valid HART otherwise -1U
- */
-static inline u32 sbi_platform_hart_index(const struct sbi_platform *plat,
-					  u32 hartid)
-{
-	u32 i;
-
-	if (!plat)
-		return -1U;
-	if (plat->hart_index2id) {
-		for (i = 0; i < plat->hart_count; i++) {
-			if (plat->hart_index2id[i] == hartid)
-				return i;
-		}
-		return -1U;
-	}
-
-	return hartid;
-}
-
 /**
  * Check whether given HART is invalid
  *
@@ -340,39 +293,6 @@ static inline bool sbi_platform_hart_invalid(const struct sbi_platform *plat,
 	return FALSE;
 }
 
-/**
- * Bringup a given hart from previous stage. Platform should implement this
- * operation if they support a custom mechanism to start a hart. Otherwise,
- * a generic WFI based approach will be used to start/stop a hart in OpenSBI.
- *
- * @param plat pointer to struct sbi_platform
- * @param hartid HART id
- * @param saddr M-mode start physical address for the HART
- *
- * @return 0 if sucessful and negative error code on failure
- */
-static inline int sbi_platform_hart_start(const struct sbi_platform *plat,
-					  u32 hartid, ulong saddr)
-{
-	if (plat && sbi_platform_ops(plat)->hart_start)
-		return sbi_platform_ops(plat)->hart_start(hartid, saddr);
-	return SBI_ENOTSUPP;
-}
-
-/**
- * Stop the current hart in OpenSBI.
- *
- * @param plat pointer to struct sbi_platform
- *
- * @return Negative error code on failure. It doesn't return on success.
- */
-static inline int sbi_platform_hart_stop(const struct sbi_platform *plat)
-{
-	if (plat && sbi_platform_ops(plat)->hart_stop)
-		return sbi_platform_ops(plat)->hart_stop();
-	return SBI_ENOTSUPP;
-}
-
 /**
  * Early initialization for current HART
  *
@@ -458,72 +378,19 @@ static inline int sbi_platform_misa_xlen(const struct sbi_platform *plat)
 }
 
 /**
- * Get the number of PMP regions of a HART
+ * Initialize (or populate) domains for the platform
  *
  * @param plat pointer to struct sbi_platform
- * @param hartid HART ID
- *
- * @return number of PMP regions
- */
-static inline u32 sbi_platform_pmp_region_count(const struct sbi_platform *plat,
-						u32 hartid)
-{
-	if (plat && sbi_platform_ops(plat)->pmp_region_count)
-		return sbi_platform_ops(plat)->pmp_region_count(hartid);
-	return 0;
-}
-
-/**
- * Get PMP regions details (namely: protection, base address,
- * and size) of a HART
- *
- * @param plat pointer to struct sbi_platform
- * @param hartid HART ID
- * @param index index of PMP region for which we want details
- * @param prot output pointer for PMP region protection
- * @param addr output pointer for PMP region base address
- * @param log2size output pointer for log-of-2 PMP region size
  *
  * @return 0 on success and negative error code on failure
  */
-static inline int sbi_platform_pmp_region_info(const struct sbi_platform *plat,
-						u32 hartid, u32 index,
-						ulong *prot, ulong *addr,
-						ulong *log2size)
+static inline int sbi_platform_domains_init(const struct sbi_platform *plat)
 {
-	if (plat && sbi_platform_ops(plat)->pmp_region_info)
-		return sbi_platform_ops(plat)->pmp_region_info(hartid, index, prot, addr,
-                                                                              log2size);
+	if (plat && sbi_platform_ops(plat)->domains_init)
+		return sbi_platform_ops(plat)->domains_init();
 	return 0;
 }
 
-/**
- * Write a character to the platform console output
- *
- * @param plat pointer to struct sbi_platform
- * @param ch character to write
- */
-static inline void sbi_platform_console_putc(const struct sbi_platform *plat,
-						char ch)
-{
-	if (plat && sbi_platform_ops(plat)->console_putc)
-		sbi_platform_ops(plat)->console_putc(ch);
-}
-
-/**
- * Read a character from the platform console input
- *
- * @param plat pointer to struct sbi_platform
- *
- * @return character read from console input
- */
-static inline int sbi_platform_console_getc(const struct sbi_platform *plat)
-{
-	if (plat && sbi_platform_ops(plat)->console_getc)
-		return sbi_platform_ops(plat)->console_getc();
-	return -1;
-}
-
 /**
  * Initialize the platform console
  *
@@ -565,32 +432,6 @@ static inline void sbi_platform_irqchip_exit(const struct sbi_platform *plat)
 		sbi_platform_ops(plat)->irqchip_exit();
 }
 
-/**
- * Send IPI to a target HART
- *
- * @param plat pointer to struct sbi_platform
- * @param target_hart HART ID of IPI target
- */
-static inline void sbi_platform_ipi_send(const struct sbi_platform *plat,
-					 u32 target_hart)
-{
-	if (plat && sbi_platform_ops(plat)->ipi_send)
-		sbi_platform_ops(plat)->ipi_send(target_hart);
-}
-
-/**
- * Clear IPI for a target HART
- *
- * @param plat pointer to struct sbi_platform
- * @param target_hart HART ID of IPI target
- */
-static inline void sbi_platform_ipi_clear(const struct sbi_platform *plat,
-					  u32 target_hart)
-{
-	if (plat && sbi_platform_ops(plat)->ipi_clear)
-		sbi_platform_ops(plat)->ipi_clear(target_hart);
-}
-
 /**
  * Initialize the platform IPI support for current HART
  *
@@ -618,45 +459,6 @@ static inline void sbi_platform_ipi_exit(const struct sbi_platform *plat)
 		sbi_platform_ops(plat)->ipi_exit();
 }
 
-/**
- * Get platform timer value
- *
- * @param plat pointer to struct sbi_platform
- *
- * @return 64-bit timer value
- */
-static inline u64 sbi_platform_timer_value(const struct sbi_platform *plat)
-{
-	if (plat && sbi_platform_ops(plat)->timer_value)
-		return sbi_platform_ops(plat)->timer_value();
-	return 0;
-}
-
-/**
- * Start platform timer event for current HART
- *
- * @param plat pointer to struct struct sbi_platform
- * @param next_event timer value when timer event will happen
- */
-static inline void
-sbi_platform_timer_event_start(const struct sbi_platform *plat, u64 next_event)
-{
-	if (plat && sbi_platform_ops(plat)->timer_event_start)
-		sbi_platform_ops(plat)->timer_event_start(next_event);
-}
-
-/**
- * Stop platform timer event for current HART
- *
- * @param plat pointer to struct sbi_platform
- */
-static inline void
-sbi_platform_timer_event_stop(const struct sbi_platform *plat)
-{
-	if (plat && sbi_platform_ops(plat)->timer_event_stop)
-		sbi_platform_ops(plat)->timer_event_stop();
-}
-
 /**
  * Initialize the platform timer for current HART
  *
@@ -684,38 +486,6 @@ static inline void sbi_platform_timer_exit(const struct sbi_platform *plat)
 		sbi_platform_ops(plat)->timer_exit();
 }
 
-/**
- * Reboot the platform
- *
- * @param plat pointer to struct sbi_platform
- * @param type type of reboot
- *
- * @return 0 on success and negative error code on failure
- */
-static inline int sbi_platform_system_reboot(const struct sbi_platform *plat,
-					     u32 type)
-{
-	if (plat && sbi_platform_ops(plat)->system_reboot)
-		return sbi_platform_ops(plat)->system_reboot(type);
-	return 0;
-}
-
-/**
- * Shutdown or poweroff the platform
- *
- * @param plat pointer to struct sbi_platform
- * @param type type of shutdown or poweroff
- *
- * @return 0 on success and negative error code on failure
- */
-static inline int sbi_platform_system_shutdown(const struct sbi_platform *plat,
-					       u32 type)
-{
-	if (plat && sbi_platform_ops(plat)->system_shutdown)
-		return sbi_platform_ops(plat)->system_shutdown(type);
-	return 0;
-}
-
 /**
  * Check if a vendor extension is implemented or not.
  *
@@ -739,7 +509,7 @@ static inline int sbi_platform_vendor_ext_check(const struct sbi_platform *plat,
  * @param plat pointer to struct sbi_platform
  * @param extid	vendor SBI extension id
  * @param funcid SBI function id within the extension id
- * @param args pointer to arguments passed by the caller
+ * @param regs pointer to trap registers passed by the caller
  * @param out_value output value that can be filled by the callee
  * @param out_trap trap info that can be filled by the callee
  *
@@ -748,13 +518,13 @@ static inline int sbi_platform_vendor_ext_check(const struct sbi_platform *plat,
 static inline int sbi_platform_vendor_ext_provider(
 					const struct sbi_platform *plat,
 					long extid, long funcid,
-					unsigned long *args,
+					const struct sbi_trap_regs *regs,
 					unsigned long *out_value,
 					struct sbi_trap_info *out_trap)
 {
 	if (plat && sbi_platform_ops(plat)->vendor_ext_provider) {
 		return sbi_platform_ops(plat)->vendor_ext_provider(extid,
-								funcid, args,
+								funcid, regs,
 								out_value,
 								out_trap);
 	}

include/sbi/sbi_scratch.h

@@ -30,18 +30,20 @@
 #define SBI_SCRATCH_PLATFORM_ADDR_OFFSET	(6 * __SIZEOF_POINTER__)
 /** Offset of hartid_to_scratch member in sbi_scratch */
 #define SBI_SCRATCH_HARTID_TO_SCRATCH_OFFSET	(7 * __SIZEOF_POINTER__)
+/** Offset of trap_exit member in sbi_scratch */
+#define SBI_SCRATCH_TRAP_EXIT_OFFSET		(8 * __SIZEOF_POINTER__)
 /** Offset of tmp0 member in sbi_scratch */
-#define SBI_SCRATCH_TMP0_OFFSET			(8 * __SIZEOF_POINTER__)
+#define SBI_SCRATCH_TMP0_OFFSET			(9 * __SIZEOF_POINTER__)
 /** Offset of options member in sbi_scratch */
-#define SBI_SCRATCH_OPTIONS_OFFSET		(9 * __SIZEOF_POINTER__)
+#define SBI_SCRATCH_OPTIONS_OFFSET		(10 * __SIZEOF_POINTER__)
 /** Offset of extra space in sbi_scratch */
-#define SBI_SCRATCH_EXTRA_SPACE_OFFSET		(10 * __SIZEOF_POINTER__)
+#define SBI_SCRATCH_EXTRA_SPACE_OFFSET		(11 * __SIZEOF_POINTER__)
 /** Maximum size of sbi_scratch (4KB) */
 #define SBI_SCRATCH_SIZE			(0x1000)
 
 /* clang-format on */
 
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
 
 #include <sbi/sbi_types.h>
 
@@ -63,11 +65,13 @@ struct sbi_scratch {
 	unsigned long platform_addr;
 	/** Address of HART ID to sbi_scratch conversion function */
 	unsigned long hartid_to_scratch;
+	/** Address of trap exit function */
+	unsigned long trap_exit;
 	/** Temporary storage */
 	unsigned long tmp0;
 	/** Options for OpenSBI library */
 	unsigned long options;
-} __packed;
+};
 
 /** Possible options for OpenSBI library */
 enum sbi_scratch_options {
@@ -85,7 +89,7 @@ enum sbi_scratch_options {
 #define sbi_scratch_thishart_arg1_ptr() \
 	((void *)(sbi_scratch_thishart_ptr()->next_arg1))
 
-/** Initialize scatch table and allocator */
+/** Initialize scratch table and allocator */
 int sbi_scratch_init(struct sbi_scratch *scratch);
 
 /**

include/sbi/sbi_string.h

@@ -12,8 +12,15 @@
 
 #include <sbi/sbi_types.h>
 
+/*
+  Provides sbi_strcmp for the completeness of supporting string functions.
+  it is not recommended to use sbi_strcmp() but use sbi_strncmp instead.
+*/
+
 int sbi_strcmp(const char *a, const char *b);
 
+int sbi_strncmp(const char *a, const char *b, size_t count);
+
 size_t sbi_strlen(const char *str);
 
 size_t sbi_strnlen(const char *str, size_t count);

include/sbi/sbi_system.h

@@ -12,8 +12,50 @@
 
 #include <sbi/sbi_types.h>
 
-void __noreturn sbi_system_reboot(u32 type);
+/** System reset hardware device */
+struct sbi_system_reset_device {
+	/** Name of the system reset device */
+	char name[32];
 
-void __noreturn sbi_system_shutdown(u32 type);
+	/* Check whether reset type and reason supported by the device */
+	int (*system_reset_check)(u32 reset_type, u32 reset_reason);
+
+	/** Reset the system */
+	void (*system_reset)(u32 reset_type, u32 reset_reason);
+};
+
+const struct sbi_system_reset_device *sbi_system_reset_get_device(void);
+
+void sbi_system_reset_set_device(const struct sbi_system_reset_device *dev);
+
+bool sbi_system_reset_supported(u32 reset_type, u32 reset_reason);
+
+void __noreturn sbi_system_reset(u32 reset_type, u32 reset_reason);
+
+/** System suspend device */
+struct sbi_system_suspend_device {
+	/** Name of the system suspend device */
+	char name[32];
+
+	/* Check whether sleep type is supported by the device */
+	int (*system_suspend_check)(u32 sleep_type);
+
+	/**
+	 * Suspend the system
+	 *
+	 * @sleep_type: The sleep type identifier passed to the SBI call.
+	 * @mmode_resume_addr:
+	 *     This is the same as sbi_scratch.warmboot_addr. Some platforms
+	 *     may not be able to return from system_suspend(), so they will
+	 *     jump directly to this address instead. Platforms which can
+	 *     return from system_suspend() may ignore this parameter.
+	 */
+	int (*system_suspend)(u32 sleep_type, unsigned long mmode_resume_addr);
+};
+
+const struct sbi_system_suspend_device *sbi_system_suspend_get_device(void);
+void sbi_system_suspend_set_device(struct sbi_system_suspend_device *dev);
+bool sbi_system_suspend_supported(u32 sleep_type);
+int sbi_system_suspend(u32 sleep_type, ulong resume_addr, ulong opaque);
 
 #endif

include/sbi/sbi_timer.h

@@ -12,6 +12,21 @@
 
 #include <sbi/sbi_types.h>
 
+/** Timer hardware device */
+struct sbi_timer_device {
+	/** Name of the timer operations */
+	char name[32];
+
+	/** Get free-running timer value */
+	u64 (*timer_value)(void);
+
+	/** Start timer event for current HART */
+	void (*timer_event_start)(u64 next_event);
+
+	/** Stop timer event for current HART */
+	void (*timer_event_stop)(void);
+};
+
 struct sbi_scratch;
 
 /** Get timer value for current HART */
@@ -35,6 +50,12 @@ void sbi_timer_event_start(u64 next_event);
 /** Process timer event for current HART */
 void sbi_timer_process(void);
 
+/** Get current timer device */
+const struct sbi_timer_device *sbi_timer_get_device(void);
+
+/** Register timer device */
+void sbi_timer_set_device(const struct sbi_timer_device *dev);
+
 /* Initialize timer */
 int sbi_timer_init(struct sbi_scratch *scratch, bool cold_boot);
 

include/sbi/sbi_tlb.h

@@ -22,33 +22,33 @@
 
 #define SBI_TLB_FIFO_NUM_ENTRIES		8
 
-enum sbi_tlb_info_types {
-	SBI_TLB_FLUSH_VMA,
-	SBI_TLB_FLUSH_VMA_ASID,
-	SBI_TLB_FLUSH_GVMA,
-	SBI_TLB_FLUSH_GVMA_VMID,
-	SBI_TLB_FLUSH_VVMA,
-	SBI_TLB_FLUSH_VVMA_ASID,
-	SBI_ITLB_FLUSH
-};
-
 struct sbi_scratch;
 
 struct sbi_tlb_info {
 	unsigned long start;
 	unsigned long size;
 	unsigned long asid;
-	unsigned long type;
+	unsigned long vmid;
+	void (*local_fn)(struct sbi_tlb_info *tinfo);
 	struct sbi_hartmask smask;
 };
 
-#define SBI_TLB_INFO_INIT(__ptr, __start, __size, __asid, __type, __src_hart) \
+void sbi_tlb_local_hfence_vvma(struct sbi_tlb_info *tinfo);
+void sbi_tlb_local_hfence_gvma(struct sbi_tlb_info *tinfo);
+void sbi_tlb_local_sfence_vma(struct sbi_tlb_info *tinfo);
+void sbi_tlb_local_hfence_vvma_asid(struct sbi_tlb_info *tinfo);
+void sbi_tlb_local_hfence_gvma_vmid(struct sbi_tlb_info *tinfo);
+void sbi_tlb_local_sfence_vma_asid(struct sbi_tlb_info *tinfo);
+void sbi_tlb_local_fence_i(struct sbi_tlb_info *tinfo);
+
+#define SBI_TLB_INFO_INIT(__p, __start, __size, __asid, __vmid, __lfn, __src) \
 do { \
-	(__ptr)->start = (__start); \
-	(__ptr)->size = (__size); \
-	(__ptr)->asid = (__asid); \
-	(__ptr)->type = (__type); \
-	SBI_HARTMASK_INIT_EXCEPT(&(__ptr)->smask, (__src_hart)); \
+	(__p)->start = (__start); \
+	(__p)->size = (__size); \
+	(__p)->asid = (__asid); \
+	(__p)->vmid = (__vmid); \
+	(__p)->local_fn = (__lfn); \
+	SBI_HARTMASK_INIT_EXCEPT(&(__p)->smask, (__src)); \
 } while (0)
 
 #define SBI_TLB_INFO_SIZE		sizeof(struct sbi_tlb_info)

include/sbi/sbi_trap.h

@@ -110,7 +110,7 @@
 /** Size (in bytes) of sbi_trap_info */
 #define SBI_TRAP_INFO_SIZE SBI_TRAP_INFO_OFFSET(last)
 
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
 
 #include <sbi/sbi_types.h>
 
@@ -186,7 +186,7 @@ struct sbi_trap_regs {
 	unsigned long mstatus;
 	/** mstatusH register state (only for 32-bit) */
 	unsigned long mstatusH;
-} __packed;
+};
 
 /** Representation of trap details */
 struct sbi_trap_info {
@@ -205,7 +205,9 @@ struct sbi_trap_info {
 int sbi_trap_redirect(struct sbi_trap_regs *regs,
 		      struct sbi_trap_info *trap);
 
-void sbi_trap_handler(struct sbi_trap_regs *regs);
+struct sbi_trap_regs *sbi_trap_handler(struct sbi_trap_regs *regs);
+
+void __noreturn sbi_trap_exit(const struct sbi_trap_regs *regs);
 
 #endif
 

include/sbi/sbi_types.h

@@ -63,6 +63,7 @@ typedef unsigned long		physical_size_t;
 
 #define __packed		__attribute__((packed))
 #define __noreturn		__attribute__((noreturn))
+#define __aligned(x)		__attribute__((aligned(x)))
 
 #define likely(x) __builtin_expect((x), 1)
 #define unlikely(x) __builtin_expect((x), 0)
@@ -78,6 +79,8 @@ typedef unsigned long		physical_size_t;
 	const typeof(((type *)0)->member) * __mptr = (ptr);	\
 	(type *)((char *)__mptr - offsetof(type, member)); })
 
+#define array_size(x) 	(sizeof(x) / sizeof((x)[0]))
+
 #define MAX(a, b) ((a) > (b) ? (a) : (b))
 #define MIN(a, b) ((a) < (b) ? (a) : (b))
 #define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi)

include/sbi/sbi_version.h

@@ -11,7 +11,7 @@
 #define __SBI_VERSION_H__
 
 #define OPENSBI_VERSION_MAJOR 0
-#define OPENSBI_VERSION_MINOR 7
+#define OPENSBI_VERSION_MINOR 9
 
 /**
  * OpenSBI 32-bit version with:

include/sbi_utils/fdt/fdt_domain.h

@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * fdt_domain.c - Flat Device Tree Domain helper routines
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel <anup.patel@wdc.com>
+ */
+
+#ifndef __FDT_DOMAIN_H__
+#define __FDT_DOMAIN_H__
+
+#include <sbi/sbi_types.h>
+
+struct sbi_domain;
+
+/**
+ * Iterate over each domains in device tree
+ *
+ * @param fdt device tree blob
+ * @param opaque private pointer for each iteration
+ * @param fn callback function for each iteration
+ *
+ * @return 0 on success and negative error code on failure
+ */
+int fdt_iterate_each_domain(void *fdt, void *opaque,
+			    int (*fn)(void *fdt, int domain_offset,
+				      void *opaque));
+
+/**
+ * Iterate over each memregion of a domain in device tree
+ *
+ * @param fdt device tree blob
+ * @param domain_offset domain DT node offset
+ * @param opaque private pointer for each iteration
+ * @param fn callback function for each iteration
+ *
+ * @return 0 on success and negative error code on failure
+ */
+int fdt_iterate_each_memregion(void *fdt, int domain_offset, void *opaque,
+			       int (*fn)(void *fdt, int domain_offset,
+					 int region_offset, u32 region_access,
+					 void *opaque));
+
+/**
+ * Fix up the domain configuration in the device tree
+ *
+ * This routine:
+ * 1. Disables MMIO devices not accessible to the coldboot HART domain
+ * 2. Removes "opensbi-domain" DT property from CPU DT nodes
+ * 3. Removes domain configuration DT node under /chosen DT node
+ *
+ * It is recommended that platform support call this function in
+ * their final_init() platform operation.
+ *
+ * @param fdt device tree blob
+ */
+void fdt_domain_fixup(void *fdt);
+
+/**
+ * Populate domains from device tree
+ *
+ * It is recommended that platform support call this function in
+ * their domains_init() platform operation.
+ *
+ * @param fdt device tree blob
+ *
+ * @return 0 on success and negative error code on failure
+ */
+int fdt_domains_populate(void *fdt);
+
+#endif /* __FDT_DOMAIN_H__ */

include/sbi_utils/fdt/fdt_fixup.h

@@ -30,9 +30,8 @@ void fdt_cpu_fixup(void *fdt);
  * It is recommended that platform codes call this helper in their final_init()
  *
  * @param fdt: device tree blob
- * @param compat: PLIC node compatible string
  */
-void fdt_plic_fixup(void *fdt, const char *compat);
+void fdt_plic_fixup(void *fdt);
 
 /**
  * Fix up the reserved memory node in the device tree
@@ -47,6 +46,20 @@ void fdt_plic_fixup(void *fdt, const char *compat);
  */
 int fdt_reserved_memory_fixup(void *fdt);
 
+/**
+ * Fix up the reserved memory subnodes in the device tree
+ *
+ * This routine adds the no-map property to the reserved memory subnodes so
+ * that the OS does not map those PMP protected memory regions.
+ *
+ * Platform codes must call this helper in their final_init() after fdt_fixups()
+ * if the OS should not map the PMP protected reserved regions.
+ *
+ * @param fdt: device tree blob
+ * @return zero on success and -ve on failure
+ */
+int fdt_reserved_memory_nomap_fixup(void *fdt);
+
 /**
  * General device tree fix-up
  *

include/sbi_utils/fdt/fdt_helper.h

@@ -10,24 +10,59 @@
 #ifndef __FDT_HELPER_H__
 #define __FDT_HELPER_H__
 
+#include <sbi/sbi_types.h>
+
+struct fdt_match {
+	const char *compatible;
+	void *data;
+};
+
 struct platform_uart_data {
 	unsigned long addr;
 	unsigned long freq;
 	unsigned long baud;
+	unsigned long reg_shift;
+	unsigned long reg_io_width;
 };
 
-struct platform_plic_data {
-	unsigned long addr;
-	unsigned long num_src;
-};
+const struct fdt_match *fdt_match_node(void *fdt, int nodeoff,
+				       const struct fdt_match *match_table);
+
+int fdt_find_match(void *fdt, int startoff,
+		   const struct fdt_match *match_table,
+		   const struct fdt_match **out_match);
+
+int fdt_get_node_addr_size(void *fdt, int node, unsigned long *addr,
+			   unsigned long *size);
+
+int fdt_parse_hart_id(void *fdt, int cpu_offset, u32 *hartid);
+
+int fdt_parse_max_hart_id(void *fdt, u32 *max_hartid);
+
+int fdt_parse_shakti_uart_node(void *fdt, int nodeoffset,
+			       struct platform_uart_data *uart);
+
+int fdt_parse_sifive_uart_node(void *fdt, int nodeoffset,
+			       struct platform_uart_data *uart);
+
+int fdt_parse_uart8250_node(void *fdt, int nodeoffset,
+			    struct platform_uart_data *uart);
 
 int fdt_parse_uart8250(void *fdt, struct platform_uart_data *uart,
 		       const char *compatible);
 
-int fdt_parse_plic(void *fdt, struct platform_plic_data *plic,
-		   const char *compatible);
+struct plic_data;
 
-int fdt_parse_clint(void *fdt, unsigned long *clint_addr,
-		    const char *compatible);
+int fdt_parse_plic_node(void *fdt, int nodeoffset, struct plic_data *plic);
+
+int fdt_parse_plic(void *fdt, struct plic_data *plic, const char *compat);
+
+struct clint_data;
+
+int fdt_parse_clint_node(void *fdt, int nodeoffset, bool for_timer,
+			 struct clint_data *clint);
+
+int fdt_parse_compat_addr(void *fdt, unsigned long *addr,
+			  const char *compatible);
 
 #endif /* __FDT_HELPER_H__ */

include/sbi_utils/ipi/fdt_ipi.h

@@ -0,0 +1,26 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel <anup.patel@wdc.com>
+ */
+
+#ifndef __FDT_IPI_H__
+#define __FDT_IPI_H__
+
+#include <sbi/sbi_types.h>
+
+struct fdt_ipi {
+	const struct fdt_match *match_table;
+	int (*cold_init)(void *fdt, int nodeoff, const struct fdt_match *match);
+	int (*warm_init)(void);
+	void (*exit)(void);
+};
+
+void fdt_ipi_exit(void);
+
+int fdt_ipi_init(bool cold_boot);
+
+#endif

include/sbi_utils/irqchip/fdt_irqchip.h

@@ -0,0 +1,26 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel <anup.patel@wdc.com>
+ */
+
+#ifndef __FDT_IRQCHIP_H__
+#define __FDT_IRQCHIP_H__
+
+#include <sbi/sbi_types.h>
+
+struct fdt_irqchip {
+	const struct fdt_match *match_table;
+	int (*cold_init)(void *fdt, int nodeoff, const struct fdt_match *match);
+	int (*warm_init)(void);
+	void (*exit)(void);
+};
+
+void fdt_irqchip_exit(void);
+
+int fdt_irqchip_init(bool cold_boot);
+
+#endif

include/sbi_utils/irqchip/plic.h

@@ -12,12 +12,18 @@
 
 #include <sbi/sbi_types.h>
 
-int plic_warm_irqchip_init(u32 target_hart, int m_cntx_id, int s_cntx_id);
+struct plic_data {
+	unsigned long addr;
+	unsigned long num_src;
+};
 
-int plic_cold_irqchip_init(unsigned long base, u32 num_sources, u32 hart_count);
+int plic_warm_irqchip_init(struct plic_data *plic,
+			   int m_cntx_id, int s_cntx_id);
 
-void plic_set_thresh(u32 cntxid, u32 val);
+int plic_cold_irqchip_init(struct plic_data *plic);
 
-void plic_set_ie(u32 cntxid, u32 word_index, u32 val);
+void plic_set_thresh(struct plic_data *plic, u32 cntxid, u32 val);
+
+void plic_set_ie(struct plic_data *plic, u32 cntxid, u32 word_index, u32 val);
 
 #endif

include/sbi_utils/reset/fdt_reset.h

@@ -0,0 +1,22 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel <anup.patel@wdc.com>
+ */
+
+#ifndef __FDT_RESET_H__
+#define __FDT_RESET_H__
+
+#include <sbi/sbi_types.h>
+
+struct fdt_reset {
+	const struct fdt_match *match_table;
+	int (*init)(void *fdt, int nodeoff, const struct fdt_match *match);
+};
+
+int fdt_reset_init(void);
+
+#endif

include/sbi_utils/serial/fdt_serial.h

@@ -0,0 +1,22 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel <anup.patel@wdc.com>
+ */
+
+#ifndef __FDT_SERIAL_H__
+#define __FDT_SERIAL_H__
+
+#include <sbi/sbi_types.h>
+
+struct fdt_serial {
+	const struct fdt_match *match_table;
+	int (*init)(void *fdt, int nodeoff, const struct fdt_match *match);
+};
+
+int fdt_serial_init(void);
+
+#endif

include/sbi_utils/serial/shakti-uart.h

@@ -0,0 +1,14 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2020 Vijai Kumar K <vijai@behindbytes.com>
+ */
+
+#ifndef __SERIAL_SHAKTI_UART_H__
+#define __SERIAL_SHAKTI_UART_H__
+
+#include <sbi/sbi_types.h>
+
+int shakti_uart_init(unsigned long base, u32 in_freq, u32 baudrate);
+
+#endif

include/sbi_utils/serial/sifive-uart.h

@@ -12,10 +12,6 @@
 
 #include <sbi/sbi_types.h>
 
-void sifive_uart_putc(char ch);
-
-int sifive_uart_getc(void);
-
 int sifive_uart_init(unsigned long base, u32 in_freq, u32 baudrate);
 
 #endif

include/sbi_utils/serial/uart8250.h

@@ -12,10 +12,6 @@
 
 #include <sbi/sbi_types.h>
 
-void uart8250_putc(char ch);
-
-int uart8250_getc(void);
-
 int uart8250_init(unsigned long base, u32 in_freq, u32 baudrate, u32 reg_shift,
 		  u32 reg_width);
 

include/sbi_utils/sys/clint.h

@@ -12,25 +12,30 @@
 
 #include <sbi/sbi_types.h>
 
-void clint_ipi_send(u32 target_hart);
-
-void clint_ipi_sync(u32 target_hart);
-
-void clint_ipi_clear(u32 target_hart);
+struct clint_data {
+	/* Public details */
+	unsigned long addr;
+	u32 first_hartid;
+	u32 hart_count;
+	bool has_64bit_mmio;
+	/* Private details (initialized and used by CLINT library)*/
+	u32 *ipi;
+	struct clint_data *time_delta_reference;
+	unsigned long time_delta_computed;
+	u64 time_delta;
+	u64 *time_val;
+	u64 *time_cmp;
+	u64 (*time_rd)(volatile u64 *addr);
+	void (*time_wr)(u64 value, volatile u64 *addr);
+};
 
 int clint_warm_ipi_init(void);
 
-int clint_cold_ipi_init(unsigned long base, u32 hart_count);
-
-u64 clint_timer_value(void);
-
-void clint_timer_event_stop(void);
-
-void clint_timer_event_start(u64 next_event);
+int clint_cold_ipi_init(struct clint_data *clint);
 
 int clint_warm_timer_init(void);
 
-int clint_cold_timer_init(unsigned long base, u32 hart_count,
-			  bool has_64bit_mmio);
+int clint_cold_timer_init(struct clint_data *clint,
+			  struct clint_data *reference);
 
 #endif

include/sbi_utils/sys/htif.h

@@ -10,10 +10,8 @@
 
 #include <sbi/sbi_types.h>
 
-void htif_putc(char ch);
+int htif_serial_init(void);
 
-int htif_getc(void);
-
-int htif_system_down(u32 type);
+int htif_system_reset_init(void);
 
 #endif

include/sbi_utils/sys/sifive_test.h

@@ -0,0 +1,17 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel <anup.patel@wdc.com>
+ */
+
+#ifndef __SYS_SIFIVE_TEST_H__
+#define __SYS_SIFIVE_TEST_H__
+
+#include <sbi/sbi_types.h>
+
+int sifive_test_init(unsigned long base);
+
+#endif

include/sbi_utils/timer/fdt_timer.h

@@ -0,0 +1,26 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel <anup.patel@wdc.com>
+ */
+
+#ifndef __FDT_TIMER_H__
+#define __FDT_TIMER_H__
+
+#include <sbi/sbi_types.h>
+
+struct fdt_timer {
+	const struct fdt_match *match_table;
+	int (*cold_init)(void *fdt, int nodeoff, const struct fdt_match *match);
+	int (*warm_init)(void);
+	void (*exit)(void);
+};
+
+void fdt_timer_exit(void);
+
+int fdt_timer_init(bool cold_boot);
+
+#endif

lib/sbi/objects.mk

@@ -15,21 +15,25 @@ libsbi-objs-y += riscv_locks.o
 libsbi-objs-y += sbi_bitmap.o
 libsbi-objs-y += sbi_bitops.o
 libsbi-objs-y += sbi_console.o
+libsbi-objs-y += sbi_domain.o
 libsbi-objs-y += sbi_ecall.o
 libsbi-objs-y += sbi_ecall_base.o
 libsbi-objs-y += sbi_ecall_hsm.o
 libsbi-objs-y += sbi_ecall_legacy.o
 libsbi-objs-y += sbi_ecall_replace.o
 libsbi-objs-y += sbi_ecall_vendor.o
+libsbi-objs-y += sbi_ecall_susp.o
 libsbi-objs-y += sbi_emulate_csr.o
 libsbi-objs-y += sbi_fifo.o
 libsbi-objs-y += sbi_hart.o
+libsbi-objs-y += sbi_math.o
 libsbi-objs-y += sbi_hfence.o
 libsbi-objs-y += sbi_hsm.o
 libsbi-objs-y += sbi_illegal_insn.o
 libsbi-objs-y += sbi_init.o
 libsbi-objs-y += sbi_ipi.o
 libsbi-objs-y += sbi_misaligned_ldst.o
+libsbi-objs-y += sbi_platform.o
 libsbi-objs-y += sbi_scratch.o
 libsbi-objs-y += sbi_string.o
 libsbi-objs-y += sbi_system.o
@@ -37,4 +41,4 @@ libsbi-objs-y += sbi_timer.o
 libsbi-objs-y += sbi_tlb.o
 libsbi-objs-y += sbi_trap.o
 libsbi-objs-y += sbi_unpriv.o
-libsbi-objs-y += sbi_unpriv_trap.o
+libsbi-objs-y += sbi_expected_trap.o

lib/sbi/riscv_asm.c

@@ -17,8 +17,13 @@ int misa_extension_imp(char ext)
 {
 	unsigned long misa = csr_read(CSR_MISA);
 
-	if (misa)
-		return misa & (1 << (ext - 'A'));
+	if (misa) {
+		if ('A' <= ext && ext <= 'Z')
+			return misa & (1 << (ext - 'A'));
+		if ('a' <= ext && ext <= 'z')
+			return misa & (1 << (ext - 'a'));
+		return 0;
+	}
 
 	return sbi_platform_misa_extension(sbi_platform_thishart_ptr(), ext);
 }
@@ -44,144 +49,129 @@ int misa_xlen(void)
 	return r ? r : -1;
 }
 
+void misa_string(int xlen, char *out, unsigned int out_sz)
+{
+	unsigned int i, pos = 0;
+	const char valid_isa_order[] = "iemafdqclbjtpvnsuhkorwxyzg";
+
+	if (!out)
+		return;
+
+	if (5 <= (out_sz - pos)) {
+		out[pos++] = 'r';
+		out[pos++] = 'v';
+		switch (xlen) {
+		case 1:
+			out[pos++] = '3';
+			out[pos++] = '2';
+			break;
+		case 2:
+			out[pos++] = '6';
+			out[pos++] = '4';
+			break;
+		case 3:
+			out[pos++] = '1';
+			out[pos++] = '2';
+			out[pos++] = '8';
+			break;
+		default:
+			return;
+		}
+	}
+
+	for (i = 0; i < array_size(valid_isa_order) && (pos < out_sz); i++) {
+		if (misa_extension_imp(valid_isa_order[i]))
+			out[pos++] = valid_isa_order[i];
+	}
+
+	if (pos < out_sz)
+		out[pos++] = '\0';
+}
+
 unsigned long csr_read_num(int csr_num)
 {
+#define switchcase_csr_read(__csr_num, __val)		\
+	case __csr_num:					\
+		__val = csr_read(__csr_num);		\
+		break;
+#define switchcase_csr_read_2(__csr_num, __val)	\
+	switchcase_csr_read(__csr_num + 0, __val)	\
+	switchcase_csr_read(__csr_num + 1, __val)
+#define switchcase_csr_read_4(__csr_num, __val)	\
+	switchcase_csr_read_2(__csr_num + 0, __val)	\
+	switchcase_csr_read_2(__csr_num + 2, __val)
+#define switchcase_csr_read_8(__csr_num, __val)	\
+	switchcase_csr_read_4(__csr_num + 0, __val)	\
+	switchcase_csr_read_4(__csr_num + 4, __val)
+#define switchcase_csr_read_16(__csr_num, __val)	\
+	switchcase_csr_read_8(__csr_num + 0, __val)	\
+	switchcase_csr_read_8(__csr_num + 8, __val)
+#define switchcase_csr_read_32(__csr_num, __val)	\
+	switchcase_csr_read_16(__csr_num + 0, __val)	\
+	switchcase_csr_read_16(__csr_num + 16, __val)
+#define switchcase_csr_read_64(__csr_num, __val)	\
+	switchcase_csr_read_32(__csr_num + 0, __val)	\
+	switchcase_csr_read_32(__csr_num + 32, __val)
+
 	unsigned long ret = 0;
 
 	switch (csr_num) {
-	case CSR_PMPCFG0:
-		ret = csr_read(CSR_PMPCFG0);
-		break;
-	case CSR_PMPCFG1:
-		ret = csr_read(CSR_PMPCFG1);
-		break;
-	case CSR_PMPCFG2:
-		ret = csr_read(CSR_PMPCFG2);
-		break;
-	case CSR_PMPCFG3:
-		ret = csr_read(CSR_PMPCFG3);
-		break;
-	case CSR_PMPADDR0:
-		ret = csr_read(CSR_PMPADDR0);
-		break;
-	case CSR_PMPADDR1:
-		ret = csr_read(CSR_PMPADDR1);
-		break;
-	case CSR_PMPADDR2:
-		ret = csr_read(CSR_PMPADDR2);
-		break;
-	case CSR_PMPADDR3:
-		ret = csr_read(CSR_PMPADDR3);
-		break;
-	case CSR_PMPADDR4:
-		ret = csr_read(CSR_PMPADDR4);
-		break;
-	case CSR_PMPADDR5:
-		ret = csr_read(CSR_PMPADDR5);
-		break;
-	case CSR_PMPADDR6:
-		ret = csr_read(CSR_PMPADDR6);
-		break;
-	case CSR_PMPADDR7:
-		ret = csr_read(CSR_PMPADDR7);
-		break;
-	case CSR_PMPADDR8:
-		ret = csr_read(CSR_PMPADDR8);
-		break;
-	case CSR_PMPADDR9:
-		ret = csr_read(CSR_PMPADDR9);
-		break;
-	case CSR_PMPADDR10:
-		ret = csr_read(CSR_PMPADDR10);
-		break;
-	case CSR_PMPADDR11:
-		ret = csr_read(CSR_PMPADDR11);
-		break;
-	case CSR_PMPADDR12:
-		ret = csr_read(CSR_PMPADDR12);
-		break;
-	case CSR_PMPADDR13:
-		ret = csr_read(CSR_PMPADDR13);
-		break;
-	case CSR_PMPADDR14:
-		ret = csr_read(CSR_PMPADDR14);
-		break;
-	case CSR_PMPADDR15:
-		ret = csr_read(CSR_PMPADDR15);
-		break;
+	switchcase_csr_read_16(CSR_PMPCFG0, ret)
+	switchcase_csr_read_64(CSR_PMPADDR0, ret)
 	default:
 		break;
 	};
 
 	return ret;
+
+#undef switchcase_csr_read_64
+#undef switchcase_csr_read_32
+#undef switchcase_csr_read_16
+#undef switchcase_csr_read_8
+#undef switchcase_csr_read_4
+#undef switchcase_csr_read_2
+#undef switchcase_csr_read
 }
 
 void csr_write_num(int csr_num, unsigned long val)
 {
+#define switchcase_csr_write(__csr_num, __val)		\
+	case __csr_num:					\
+		csr_write(__csr_num, __val);		\
+		break;
+#define switchcase_csr_write_2(__csr_num, __val)	\
+	switchcase_csr_write(__csr_num + 0, __val)	\
+	switchcase_csr_write(__csr_num + 1, __val)
+#define switchcase_csr_write_4(__csr_num, __val)	\
+	switchcase_csr_write_2(__csr_num + 0, __val)	\
+	switchcase_csr_write_2(__csr_num + 2, __val)
+#define switchcase_csr_write_8(__csr_num, __val)	\
+	switchcase_csr_write_4(__csr_num + 0, __val)	\
+	switchcase_csr_write_4(__csr_num + 4, __val)
+#define switchcase_csr_write_16(__csr_num, __val)	\
+	switchcase_csr_write_8(__csr_num + 0, __val)	\
+	switchcase_csr_write_8(__csr_num + 8, __val)
+#define switchcase_csr_write_32(__csr_num, __val)	\
+	switchcase_csr_write_16(__csr_num + 0, __val)	\
+	switchcase_csr_write_16(__csr_num + 16, __val)
+#define switchcase_csr_write_64(__csr_num, __val)	\
+	switchcase_csr_write_32(__csr_num + 0, __val)	\
+	switchcase_csr_write_32(__csr_num + 32, __val)
+
 	switch (csr_num) {
-	case CSR_PMPCFG0:
-		csr_write(CSR_PMPCFG0, val);
-		break;
-	case CSR_PMPCFG1:
-		csr_write(CSR_PMPCFG1, val);
-		break;
-	case CSR_PMPCFG2:
-		csr_write(CSR_PMPCFG2, val);
-		break;
-	case CSR_PMPCFG3:
-		csr_write(CSR_PMPCFG3, val);
-		break;
-	case CSR_PMPADDR0:
-		csr_write(CSR_PMPADDR0, val);
-		break;
-	case CSR_PMPADDR1:
-		csr_write(CSR_PMPADDR1, val);
-		break;
-	case CSR_PMPADDR2:
-		csr_write(CSR_PMPADDR2, val);
-		break;
-	case CSR_PMPADDR3:
-		csr_write(CSR_PMPADDR3, val);
-		break;
-	case CSR_PMPADDR4:
-		csr_write(CSR_PMPADDR4, val);
-		break;
-	case CSR_PMPADDR5:
-		csr_write(CSR_PMPADDR5, val);
-		break;
-	case CSR_PMPADDR6:
-		csr_write(CSR_PMPADDR6, val);
-		break;
-	case CSR_PMPADDR7:
-		csr_write(CSR_PMPADDR7, val);
-		break;
-	case CSR_PMPADDR8:
-		csr_write(CSR_PMPADDR8, val);
-		break;
-	case CSR_PMPADDR9:
-		csr_write(CSR_PMPADDR9, val);
-		break;
-	case CSR_PMPADDR10:
-		csr_write(CSR_PMPADDR10, val);
-		break;
-	case CSR_PMPADDR11:
-		csr_write(CSR_PMPADDR11, val);
-		break;
-	case CSR_PMPADDR12:
-		csr_write(CSR_PMPADDR12, val);
-		break;
-	case CSR_PMPADDR13:
-		csr_write(CSR_PMPADDR13, val);
-		break;
-	case CSR_PMPADDR14:
-		csr_write(CSR_PMPADDR14, val);
-		break;
-	case CSR_PMPADDR15:
-		csr_write(CSR_PMPADDR15, val);
-		break;
+	switchcase_csr_write_16(CSR_PMPCFG0, val)
+	switchcase_csr_write_64(CSR_PMPADDR0, val)
 	default:
 		break;
 	};
+
+#undef switchcase_csr_write_64
+#undef switchcase_csr_write_32
+#undef switchcase_csr_write_16
+#undef switchcase_csr_write_8
+#undef switchcase_csr_write_4
+#undef switchcase_csr_write_2
+#undef switchcase_csr_write
 }
 
 static unsigned long ctz(unsigned long x)
@@ -224,7 +214,7 @@ int pmp_set(unsigned int n, unsigned long prot, unsigned long addr,
 
 	/* encode PMP config */
 	prot |= (log2len == PMP_SHIFT) ? PMP_A_NA4 : PMP_A_NAPOT;
-	cfgmask = ~(0xff << pmpcfg_shift);
+	cfgmask = ~(0xffUL << pmpcfg_shift);
 	pmpcfg	= (csr_read_num(pmpcfg_csr) & cfgmask);
 	pmpcfg |= ((prot << pmpcfg_shift) & ~cfgmask);
 
@@ -249,16 +239,16 @@ int pmp_set(unsigned int n, unsigned long prot, unsigned long addr,
 }
 
 int pmp_get(unsigned int n, unsigned long *prot_out, unsigned long *addr_out,
-	    unsigned long *size)
+	    unsigned long *log2len)
 {
 	int pmpcfg_csr, pmpcfg_shift, pmpaddr_csr;
 	unsigned long cfgmask, pmpcfg, prot;
-	unsigned long t1, addr, log2len;
+	unsigned long t1, addr, len;
 
 	/* check parameters */
-	if (n >= PMP_COUNT || !prot_out || !addr_out || !size)
+	if (n >= PMP_COUNT || !prot_out || !addr_out || !log2len)
 		return SBI_EINVAL;
-	*prot_out = *addr_out = *size = 0;
+	*prot_out = *addr_out = *log2len = 0;
 
 	/* calculate PMP register and offset */
 #if __riscv_xlen == 32
@@ -276,7 +266,7 @@ int pmp_get(unsigned int n, unsigned long *prot_out, unsigned long *addr_out,
 		return SBI_ENOTSUPP;
 
 	/* decode PMP config */
-	cfgmask = (0xff << pmpcfg_shift);
+	cfgmask = (0xffUL << pmpcfg_shift);
 	pmpcfg	= csr_read_num(pmpcfg_csr) & cfgmask;
 	prot	= pmpcfg >> pmpcfg_shift;
 
@@ -285,23 +275,21 @@ int pmp_get(unsigned int n, unsigned long *prot_out, unsigned long *addr_out,
 		addr = csr_read_num(pmpaddr_csr);
 		if (addr == -1UL) {
 			addr	= 0;
-			log2len = __riscv_xlen;
+			len	= __riscv_xlen;
 		} else {
 			t1	= ctz(~addr);
 			addr	= (addr & ~((1UL << t1) - 1)) << PMP_SHIFT;
-			log2len = (t1 + PMP_SHIFT + 1);
+			len	= (t1 + PMP_SHIFT + 1);
 		}
 	} else {
 		addr	= csr_read_num(pmpaddr_csr) << PMP_SHIFT;
-		log2len = PMP_SHIFT;
+		len	= PMP_SHIFT;
 	}
 
 	/* return details */
 	*prot_out    = prot;
 	*addr_out    = addr;
-
-	if (log2len < __riscv_xlen)
-		*size = (1UL << log2len);
+	*log2len     = len;
 
 	return 0;
 }

lib/sbi/riscv_atomic.c

@@ -28,25 +28,23 @@ void atomic_write(atomic_t *atom, long value)
 long atomic_add_return(atomic_t *atom, long value)
 {
 	long ret;
-
+#if __SIZEOF_LONG__ == 4
 	__asm__ __volatile__("	amoadd.w.aqrl  %1, %2, %0"
 			     : "+A"(atom->counter), "=r"(ret)
 			     : "r"(value)
 			     : "memory");
-
+#elif __SIZEOF_LONG__ == 8
+	__asm__ __volatile__("	amoadd.d.aqrl  %1, %2, %0"
+			     : "+A"(atom->counter), "=r"(ret)
+			     : "r"(value)
+			     : "memory");
+#endif
 	return ret + value;
 }
 
 long atomic_sub_return(atomic_t *atom, long value)
 {
-	long ret;
-
-	__asm__ __volatile__("	amoadd.w.aqrl  %1, %2, %0"
-			     : "+A"(atom->counter), "=r"(ret)
-			     : "r"(-value)
-			     : "memory");
-
-	return ret - value;
+	return atomic_add_return(atom, -value);
 }
 
 #define __axchg(ptr, new, size)							\

lib/sbi/riscv_locks.c

@@ -2,44 +2,76 @@
  * SPDX-License-Identifier: BSD-2-Clause
  *
  * Copyright (c) 2019 Western Digital Corporation or its affiliates.
- *
- * Authors:
- *   Anup Patel <anup.patel@wdc.com>
+ * Copyright (c) 2021 Christoph Müllner <cmuellner@linux.com>
  */
 
 #include <sbi/riscv_barrier.h>
 #include <sbi/riscv_locks.h>
 
-int spin_lock_check(spinlock_t *lock)
+static inline int spin_lock_unlocked(spinlock_t lock)
 {
-	return (lock->lock == __RISCV_SPIN_UNLOCKED) ? 0 : 1;
+	return lock.owner == lock.next;
+}
+
+bool spin_lock_check(spinlock_t *lock)
+{
+	RISCV_FENCE(r, rw);
+	return !spin_lock_unlocked(*lock);
 }
 
 int spin_trylock(spinlock_t *lock)
 {
-	int tmp = 1, busy;
+	unsigned long inc = 1u << TICKET_SHIFT;
+	unsigned long mask = 0xffffu << TICKET_SHIFT;
+	u32 l0, tmp1, tmp2;
 
 	__asm__ __volatile__(
-		"	amoswap.w %0, %2, %1\n" RISCV_ACQUIRE_BARRIER
-		: "=r"(busy), "+A"(lock->lock)
-		: "r"(tmp)
+		/* Get the current lock counters. */
+		"1:	lr.w.aq	%0, %3\n"
+		"	slli	%2, %0, %6\n"
+		"	and	%2, %2, %5\n"
+		"	and	%1, %0, %5\n"
+		/* Is the lock free right now? */
+		"	bne	%1, %2, 2f\n"
+		"	add	%0, %0, %4\n"
+		/* Acquire the lock. */
+		"	sc.w.rl	%0, %0, %3\n"
+		"	bnez	%0, 1b\n"
+		"2:"
+		: "=&r"(l0), "=&r"(tmp1), "=&r"(tmp2), "+A"(*lock)
+		: "r"(inc), "r"(mask), "I"(TICKET_SHIFT)
 		: "memory");
 
-	return !busy;
+	return !l0;
 }
 
 void spin_lock(spinlock_t *lock)
 {
-	while (1) {
-		if (spin_lock_check(lock))
-			continue;
+	unsigned long inc = 1u << TICKET_SHIFT;
+	unsigned long mask = 0xffffu;
+	u32 l0, tmp1, tmp2;
 
-		if (spin_trylock(lock))
-			break;
-	}
+	__asm__ __volatile__(
+		/* Atomically increment the next ticket. */
+		"	amoadd.w.aqrl	%0, %4, %3\n"
+
+		/* Did we get the lock? */
+		"	srli	%1, %0, %6\n"
+		"	and	%1, %1, %5\n"
+		"1:	and	%2, %0, %5\n"
+		"	beq	%1, %2, 2f\n"
+
+		/* If not, then spin on the lock. */
+		"	lw	%0, %3\n"
+		RISCV_ACQUIRE_BARRIER
+		"	j	1b\n"
+		"2:"
+		: "=&r"(l0), "=&r"(tmp1), "=&r"(tmp2), "+A"(*lock)
+		: "r"(inc), "r"(mask), "I"(TICKET_SHIFT)
+		: "memory");
 }
 
 void spin_unlock(spinlock_t *lock)
 {
-	__smp_store_release(&lock->lock, __RISCV_SPIN_UNLOCKED);
+	__smp_store_release(&lock->owner, lock->owner + 1);
 }

lib/sbi/sbi_console.c

@@ -12,7 +12,7 @@
 #include <sbi/sbi_platform.h>
 #include <sbi/sbi_scratch.h>
 
-static const struct sbi_platform *console_plat = NULL;
+static const struct sbi_console_device *console_dev = NULL;
 static spinlock_t console_out_lock	       = SPIN_LOCK_INITIALIZER;
 
 bool sbi_isprintable(char c)
@@ -26,14 +26,18 @@ bool sbi_isprintable(char c)
 
 int sbi_getc(void)
 {
-	return sbi_platform_console_getc(console_plat);
+	if (console_dev && console_dev->console_getc)
+		return console_dev->console_getc();
+	return -1;
 }
 
 void sbi_putc(char ch)
 {
-	if (ch == '\n')
-		sbi_platform_console_putc(console_plat, '\r');
-	sbi_platform_console_putc(console_plat, ch);
+	if (console_dev && console_dev->console_putc) {
+		if (ch == '\n')
+			console_dev->console_putc('\r');
+		console_dev->console_putc(ch);
+	}
 }
 
 void sbi_puts(const char *str)
@@ -390,9 +394,20 @@ int sbi_dprintf(const char *format, ...)
 	return retval;
 }
 
+const struct sbi_console_device *sbi_console_get_device(void)
+{
+	return console_dev;
+}
+
+void sbi_console_set_device(const struct sbi_console_device *dev)
+{
+	if (!dev || console_dev)
+		return;
+
+	console_dev = dev;
+}
+
 int sbi_console_init(struct sbi_scratch *scratch)
 {
-	console_plat = sbi_platform_ptr(scratch);
-
-	return sbi_platform_console_init(console_plat);
+	return sbi_platform_console_init(sbi_platform_ptr(scratch));
 }

lib/sbi/sbi_domain.c

@@ -0,0 +1,632 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel <anup.patel@wdc.com>
+ */
+
+#include <sbi/riscv_asm.h>
+#include <sbi/sbi_console.h>
+#include <sbi/sbi_domain.h>
+#include <sbi/sbi_hartmask.h>
+#include <sbi/sbi_hsm.h>
+#include <sbi/sbi_math.h>
+#include <sbi/sbi_platform.h>
+#include <sbi/sbi_scratch.h>
+#include <sbi/sbi_string.h>
+
+struct sbi_domain *hartid_to_domain_table[SBI_HARTMASK_MAX_BITS] = { 0 };
+struct sbi_domain *domidx_to_domain_table[SBI_DOMAIN_MAX_INDEX] = { 0 };
+static u32 domain_count = 0;
+static bool domain_finalized = false;
+
+static struct sbi_hartmask root_hmask = { 0 };
+
+#define ROOT_REGION_MAX	16
+static u32 root_memregs_count = 0;
+static struct sbi_domain_memregion root_fw_region;
+static struct sbi_domain_memregion root_memregs[ROOT_REGION_MAX + 1] = { 0 };
+
+struct sbi_domain root = {
+	.name = "root",
+	.possible_harts = &root_hmask,
+	.regions = root_memregs,
+	.system_reset_allowed = TRUE,
+	.system_suspend_allowed = TRUE,
+};
+
+bool sbi_domain_is_assigned_hart(const struct sbi_domain *dom, u32 hartid)
+{
+	if (dom)
+		return sbi_hartmask_test_hart(hartid, &dom->assigned_harts);
+
+	return FALSE;
+}
+
+ulong sbi_domain_get_assigned_hartmask(const struct sbi_domain *dom,
+				       ulong hbase)
+{
+	ulong ret, bword, boff;
+
+	if (!dom)
+		return 0;
+
+	bword = BIT_WORD(hbase);
+	boff = BIT_WORD_OFFSET(hbase);
+
+	ret = sbi_hartmask_bits(&dom->assigned_harts)[bword++] >> boff;
+	if (boff && bword < BIT_WORD(SBI_HARTMASK_MAX_BITS)) {
+		ret |= (sbi_hartmask_bits(&dom->assigned_harts)[bword] &
+			(BIT(boff) - 1UL)) << (BITS_PER_LONG - boff);
+	}
+
+	return ret;
+}
+
+static void domain_memregion_initfw(struct sbi_domain_memregion *reg)
+{
+	if (!reg)
+		return;
+
+	sbi_memcpy(reg, &root_fw_region, sizeof(*reg));
+}
+
+void sbi_domain_memregion_init(unsigned long addr,
+				unsigned long size,
+				unsigned long flags,
+				struct sbi_domain_memregion *reg)
+{
+	unsigned long base = 0, order;
+
+	for (order = log2roundup(size) ; order <= __riscv_xlen; order++) {
+		if (order < __riscv_xlen) {
+			base = addr & ~((1UL << order) - 1UL);
+			if ((base <= addr) &&
+			    (addr < (base + (1UL << order))) &&
+			    (base <= (addr + size - 1UL)) &&
+			    ((addr + size - 1UL) < (base + (1UL << order))))
+				break;
+		} else {
+			base = 0;
+			break;
+		}
+
+	}
+
+	if (reg) {
+		reg->base = base;
+		reg->order = order;
+		reg->flags = flags;
+	}
+}
+
+bool sbi_domain_check_addr(const struct sbi_domain *dom,
+			   unsigned long addr, unsigned long mode,
+			   unsigned long access_flags)
+{
+	bool mmio = FALSE;
+	struct sbi_domain_memregion *reg;
+	unsigned long rstart, rend, rflags, rwx = 0;
+
+	if (!dom)
+		return FALSE;
+
+	if (access_flags & SBI_DOMAIN_READ)
+		rwx |= SBI_DOMAIN_MEMREGION_READABLE;
+	if (access_flags & SBI_DOMAIN_WRITE)
+		rwx |= SBI_DOMAIN_MEMREGION_WRITEABLE;
+	if (access_flags & SBI_DOMAIN_EXECUTE)
+		rwx |= SBI_DOMAIN_MEMREGION_EXECUTABLE;
+	if (access_flags & SBI_DOMAIN_MMIO)
+		mmio = TRUE;
+
+	sbi_domain_for_each_memregion(dom, reg) {
+		rflags = reg->flags;
+		if (mode == PRV_M && !(rflags & SBI_DOMAIN_MEMREGION_MMODE))
+			continue;
+
+		rstart = reg->base;
+		rend = (reg->order < __riscv_xlen) ?
+			rstart + ((1UL << reg->order) - 1) : -1UL;
+		if (rstart <= addr && addr <= rend) {
+			if ((mmio && !(rflags & SBI_DOMAIN_MEMREGION_MMIO)) ||
+			    (!mmio && (rflags & SBI_DOMAIN_MEMREGION_MMIO)))
+				return FALSE;
+			return ((rflags & rwx) == rwx) ? TRUE : FALSE;
+		}
+	}
+
+	return (mode == PRV_M) ? TRUE : FALSE;
+}
+
+/* Check if region complies with constraints */
+static bool is_region_valid(const struct sbi_domain_memregion *reg)
+{
+	if (reg->order < 3 || __riscv_xlen < reg->order)
+		return FALSE;
+
+	if (reg->base & (BIT(reg->order) - 1))
+		return FALSE;
+
+	return TRUE;
+}
+
+/** Check if regionA is sub-region of regionB */
+static bool is_region_subset(const struct sbi_domain_memregion *regA,
+			     const struct sbi_domain_memregion *regB)
+{
+	ulong regA_start = regA->base;
+	ulong regA_end = regA->base + (BIT(regA->order) - 1);
+	ulong regB_start = regB->base;
+	ulong regB_end = regB->base + (BIT(regA->order) - 1);
+
+	if ((regB_start <= regA_start) &&
+	    (regA_start < regB_end) &&
+	    (regB_start < regA_end) &&
+	    (regA_end <= regB_end))
+		return TRUE;
+
+	return FALSE;
+}
+
+/** Check if regionA conflicts regionB */
+static bool is_region_conflict(const struct sbi_domain_memregion *regA,
+				const struct sbi_domain_memregion *regB)
+{
+	if ((is_region_subset(regA, regB) || is_region_subset(regB, regA)) &&
+	    regA->flags == regB->flags)
+		return TRUE;
+
+	return FALSE;
+}
+
+/** Check if regionA should be placed before regionB */
+static bool is_region_before(const struct sbi_domain_memregion *regA,
+			     const struct sbi_domain_memregion *regB)
+{
+	if (regA->order < regB->order)
+		return TRUE;
+
+	if ((regA->order == regB->order) &&
+	    (regA->base < regB->base))
+		return TRUE;
+
+	return FALSE;
+}
+
+static int sanitize_domain(const struct sbi_platform *plat,
+			   struct sbi_domain *dom)
+{
+	u32 i, j, count;
+	bool have_fw_reg;
+	struct sbi_domain_memregion treg, *reg, *reg1;
+
+	/* Check possible HARTs */
+	if (!dom->possible_harts) {
+		sbi_printf("%s: %s possible HART mask is NULL\n",
+			   __func__, dom->name);
+		return SBI_EINVAL;
+	}
+	sbi_hartmask_for_each_hart(i, dom->possible_harts) {
+		if (sbi_platform_hart_invalid(plat, i)) {
+			sbi_printf("%s: %s possible HART mask has invalid "
+				   "hart %d\n", __func__, dom->name, i);
+			return SBI_EINVAL;
+		}
+	};
+
+	/* Check memory regions */
+	if (!dom->regions) {
+		sbi_printf("%s: %s regions is NULL\n",
+			   __func__, dom->name);
+		return SBI_EINVAL;
+	}
+	sbi_domain_for_each_memregion(dom, reg) {
+		if (!is_region_valid(reg)) {
+			sbi_printf("%s: %s has invalid region base=0x%lx "
+				   "order=%lu flags=0x%lx\n", __func__,
+				   dom->name, reg->base, reg->order,
+				   reg->flags);
+			return SBI_EINVAL;
+		}
+	}
+
+	/* Count memory regions and check presence of firmware region */
+	count = 0;
+	have_fw_reg = FALSE;
+	sbi_domain_for_each_memregion(dom, reg) {
+		if (reg->order == root_fw_region.order &&
+		    reg->base == root_fw_region.base &&
+		    reg->flags == root_fw_region.flags)
+			have_fw_reg = TRUE;
+		count++;
+	}
+	if (!have_fw_reg) {
+		sbi_printf("%s: %s does not have firmware region\n",
+			   __func__, dom->name);
+		return SBI_EINVAL;
+	}
+
+	/* Sort the memory regions */
+	for (i = 0; i < (count - 1); i++) {
+		reg = &dom->regions[i];
+		for (j = i + 1; j < count; j++) {
+			reg1 = &dom->regions[j];
+
+			if (is_region_conflict(reg1, reg)) {
+				sbi_printf("%s: %s conflict between regions "
+					"(base=0x%lx order=%lu flags=0x%lx) and "
+					"(base=0x%lx order=%lu flags=0x%lx)\n",
+					__func__, dom->name,
+					reg->base, reg->order, reg->flags,
+					reg1->base, reg1->order, reg1->flags);
+				return SBI_EINVAL;
+			}
+
+			if (!is_region_before(reg1, reg))
+				continue;
+
+			sbi_memcpy(&treg, reg1, sizeof(treg));
+			sbi_memcpy(reg1, reg, sizeof(treg));
+			sbi_memcpy(reg, &treg, sizeof(treg));
+		}
+	}
+
+	/*
+	 * We don't need to check boot HART id of domain because if boot
+	 * HART id is not possible/assigned to this domain then it won't
+	 * be started at boot-time by sbi_domain_finalize().
+	 */
+
+	/*
+	 * Check next mode
+	 *
+	 * We only allow next mode to be S-mode or U-mode.so that we can
+	 * protect M-mode context and enforce checks on memory accesses.
+	 */
+	if (dom->next_mode != PRV_S &&
+	    dom->next_mode != PRV_U) {
+		sbi_printf("%s: %s invalid next booting stage mode 0x%lx\n",
+			   __func__, dom->name, dom->next_mode);
+		return SBI_EINVAL;
+	}
+
+	/* Check next address and next mode*/
+	if (!sbi_domain_check_addr(dom, dom->next_addr, dom->next_mode,
+				   SBI_DOMAIN_EXECUTE)) {
+		sbi_printf("%s: %s next booting stage addres 0x%lx can't "
+			   "execute\n", __func__, dom->name, dom->next_addr);
+		return SBI_EINVAL;
+	}
+
+	return 0;
+}
+
+void sbi_domain_dump(const struct sbi_domain *dom, const char *suffix)
+{
+	u32 i, k;
+	unsigned long rstart, rend;
+	struct sbi_domain_memregion *reg;
+
+	sbi_printf("Domain%d Name        %s: %s\n",
+		   dom->index, suffix, dom->name);
+
+	sbi_printf("Domain%d Boot HART   %s: %d\n",
+		   dom->index, suffix, dom->boot_hartid);
+
+	k = 0;
+	sbi_printf("Domain%d HARTs       %s: ", dom->index, suffix);
+	sbi_hartmask_for_each_hart(i, dom->possible_harts)
+		sbi_printf("%s%d%s", (k++) ? "," : "",
+			   i, sbi_domain_is_assigned_hart(dom, i) ? "*" : "");
+	sbi_printf("\n");
+
+	i = 0;
+	sbi_domain_for_each_memregion(dom, reg) {
+		rstart = reg->base;
+		rend = (reg->order < __riscv_xlen) ?
+			rstart + ((1UL << reg->order) - 1) : -1UL;
+
+#if __riscv_xlen == 32
+		sbi_printf("Domain%d Region%02d    %s: 0x%08lx-0x%08lx ",
+#else
+		sbi_printf("Domain%d Region%02d    %s: 0x%016lx-0x%016lx ",
+#endif
+			   dom->index, i, suffix, rstart, rend);
+
+		k = 0;
+		if (reg->flags & SBI_DOMAIN_MEMREGION_MMODE)
+			sbi_printf("%cM", (k++) ? ',' : '(');
+		if (reg->flags & SBI_DOMAIN_MEMREGION_MMIO)
+			sbi_printf("%cI", (k++) ? ',' : '(');
+		if (reg->flags & SBI_DOMAIN_MEMREGION_READABLE)
+			sbi_printf("%cR", (k++) ? ',' : '(');
+		if (reg->flags & SBI_DOMAIN_MEMREGION_WRITEABLE)
+			sbi_printf("%cW", (k++) ? ',' : '(');
+		if (reg->flags & SBI_DOMAIN_MEMREGION_EXECUTABLE)
+			sbi_printf("%cX", (k++) ? ',' : '(');
+		sbi_printf("%s\n", (k++) ? ")" : "()");
+
+		i++;
+	}
+
+#if __riscv_xlen == 32
+	sbi_printf("Domain%d Next Address%s: 0x%08lx\n",
+#else
+	sbi_printf("Domain%d Next Address%s: 0x%016lx\n",
+#endif
+		   dom->index, suffix, dom->next_addr);
+
+#if __riscv_xlen == 32
+	sbi_printf("Domain%d Next Arg1   %s: 0x%08lx\n",
+#else
+	sbi_printf("Domain%d Next Arg1   %s: 0x%016lx\n",
+#endif
+		   dom->index, suffix, dom->next_arg1);
+
+	sbi_printf("Domain%d Next Mode   %s: ", dom->index, suffix);
+	switch (dom->next_mode) {
+	case PRV_M:
+		sbi_printf("M-mode\n");
+		break;
+	case PRV_S:
+		sbi_printf("S-mode\n");
+		break;
+	case PRV_U:
+		sbi_printf("U-mode\n");
+		break;
+	default:
+		sbi_printf("Unknown\n");
+		break;
+	};
+
+	sbi_printf("Domain%d SysReset    %s: %s\n",
+		   dom->index, suffix, (dom->system_reset_allowed) ? "yes" : "no");
+	sbi_printf("Domain%d SysSuspend  %s: %s\n",
+		   dom->index, suffix, (dom->system_suspend_allowed) ? "yes" : "no");
+}
+
+void sbi_domain_dump_all(const char *suffix)
+{
+	u32 i;
+	const struct sbi_domain *dom;
+
+	sbi_domain_for_each(i, dom) {
+		sbi_domain_dump(dom, suffix);
+		sbi_printf("\n");
+	}
+}
+
+int sbi_domain_register(struct sbi_domain *dom,
+			const struct sbi_hartmask *assign_mask)
+{
+	u32 i;
+	int rc;
+	struct sbi_domain *tdom;
+	u32 cold_hartid = current_hartid();
+	const struct sbi_platform *plat = sbi_platform_thishart_ptr();
+
+	/* Sanity checks */
+	if (!dom || !assign_mask || domain_finalized)
+		return SBI_EINVAL;
+
+	/* Check if domain already discovered */
+	sbi_domain_for_each(i, tdom) {
+		if (tdom == dom)
+			return SBI_EALREADY;
+	}
+
+	/*
+	 * Ensure that we have room for Domain Index to
+	 * HART ID mapping
+	 */
+	if (SBI_DOMAIN_MAX_INDEX <= domain_count) {
+		sbi_printf("%s: No room for %s\n",
+			   __func__, dom->name);
+		return SBI_ENOSPC;
+	}
+
+	/* Sanitize discovered domain */
+	rc = sanitize_domain(plat, dom);
+	if (rc) {
+		sbi_printf("%s: sanity checks failed for"
+			   " %s (error %d)\n", __func__,
+			   dom->name, rc);
+		return rc;
+	}
+
+	/* Assign index to domain */
+	dom->index = domain_count++;
+	domidx_to_domain_table[dom->index] = dom;
+
+	/* Clear assigned HARTs of domain */
+	sbi_hartmask_clear_all(&dom->assigned_harts);
+
+	/* Assign domain to HART if HART is a possible HART */
+	sbi_hartmask_for_each_hart(i, assign_mask) {
+		if (!sbi_hartmask_test_hart(i, dom->possible_harts))
+			continue;
+
+		tdom = hartid_to_domain_table[i];
+		if (tdom)
+			sbi_hartmask_clear_hart(i,
+					&tdom->assigned_harts);
+		hartid_to_domain_table[i] = dom;
+		sbi_hartmask_set_hart(i, &dom->assigned_harts);
+
+		/*
+		 * If cold boot HART is assigned to this domain then
+		 * override boot HART of this domain.
+		 */
+		if (i == cold_hartid &&
+		    dom->boot_hartid != cold_hartid) {
+			sbi_printf("Domain%d Boot HARTID forced to"
+				   " %d\n", dom->index, cold_hartid);
+			dom->boot_hartid = cold_hartid;
+		}
+	}
+
+	return 0;
+}
+
+int sbi_domain_root_add_memregion(const struct sbi_domain_memregion *reg)
+{
+	int rc;
+	bool reg_merged;
+	struct sbi_domain_memregion *nreg, *nreg1, *nreg2;
+	const struct sbi_platform *plat = sbi_platform_thishart_ptr();
+
+	/* Sanity checks */
+	if (!reg || domain_finalized ||
+	    (root.regions != root_memregs) ||
+	    (ROOT_REGION_MAX <= root_memregs_count))
+		return SBI_EINVAL;
+
+	/* Check for conflicts */
+	sbi_domain_for_each_memregion(&root, nreg) {
+		if (is_region_conflict(reg, nreg))
+			return SBI_EINVAL;
+	}
+
+	/* Append the memregion to root memregions */
+	nreg = &root_memregs[root_memregs_count];
+	sbi_memcpy(nreg, reg, sizeof(*reg));
+	root_memregs_count++;
+	root_memregs[root_memregs_count].order = 0;
+
+	/* Sort and optimize root regions */
+	do {
+		/* Sanitize the root domain so that memregions are sorted */
+		rc = sanitize_domain(plat, &root);
+		if (rc) {
+			sbi_printf("%s: sanity checks failed for"
+				   " %s (error %d)\n", __func__,
+				   root.name, rc);
+			return rc;
+		}
+
+		/* Merge consecutive memregions with same order and flags */
+		reg_merged = false;
+		sbi_domain_for_each_memregion(&root, nreg) {
+			nreg1 = nreg + 1;
+			if (!nreg1->order)
+				continue;
+
+			if ((nreg->base + BIT(nreg->order)) == nreg1->base &&
+			    nreg->order == nreg1->order &&
+			    nreg->flags == nreg1->flags) {
+				nreg->order++;
+				while (nreg1->order) {
+					nreg2 = nreg1 + 1;
+					sbi_memcpy(nreg1, nreg2, sizeof(*nreg1));
+					nreg1++;
+				}
+				reg_merged = true;
+				root_memregs_count--;
+			}
+		}
+	} while (reg_merged);
+
+	return 0;
+}
+
+int sbi_domain_finalize(struct sbi_scratch *scratch, u32 cold_hartid)
+{
+	int rc;
+	u32 i, dhart;
+	struct sbi_domain *dom;
+	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
+
+	/* Initialize and populate domains for the platform */
+	rc = sbi_platform_domains_init(plat);
+	if (rc) {
+		sbi_printf("%s: platform domains_init() failed (error %d)\n",
+			   __func__, rc);
+		return rc;
+	}
+
+	/* Startup boot HART of domains */
+	sbi_domain_for_each(i, dom) {
+		/* Domain boot HART */
+		dhart = dom->boot_hartid;
+
+		/* Ignore of boot HART is off limits */
+		if (SBI_HARTMASK_MAX_BITS <= dhart)
+			continue;
+
+		/* Ignore if boot HART not possible for this domain */
+		if (!sbi_hartmask_test_hart(dhart, dom->possible_harts))
+			continue;
+
+		/* Ignore if boot HART assigned different domain */
+		if (sbi_hartid_to_domain(dhart) != dom ||
+		    !sbi_hartmask_test_hart(dhart, &dom->assigned_harts))
+			continue;
+
+		/* Startup boot HART of domain */
+		if (dhart == cold_hartid) {
+			scratch->next_addr = dom->next_addr;
+			scratch->next_mode = dom->next_mode;
+			scratch->next_arg1 = dom->next_arg1;
+		} else {
+			rc = sbi_hsm_hart_start(scratch, NULL, dhart,
+						dom->next_addr,
+						dom->next_mode,
+						dom->next_arg1);
+			if (rc) {
+				sbi_printf("%s: failed to start boot HART %d"
+					   " for %s (error %d)\n", __func__,
+					   dhart, dom->name, rc);
+				return rc;
+			}
+		}
+	}
+
+	/*
+	 * Set the finalized flag so that the root domain
+	 * regions can't be changed.
+	 */
+	domain_finalized = true;
+
+	return 0;
+}
+
+int sbi_domain_init(struct sbi_scratch *scratch, u32 cold_hartid)
+{
+	u32 i;
+	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
+
+	/* Root domain firmware memory region */
+	sbi_domain_memregion_init(scratch->fw_start, scratch->fw_size, 0,
+				  &root_fw_region);
+	domain_memregion_initfw(&root_memregs[root_memregs_count++]);
+
+	/* Root domain allow everything memory region */
+	sbi_domain_memregion_init(0, ~0UL,
+				  (SBI_DOMAIN_MEMREGION_READABLE |
+				   SBI_DOMAIN_MEMREGION_WRITEABLE |
+				   SBI_DOMAIN_MEMREGION_EXECUTABLE),
+				  &root_memregs[root_memregs_count++]);
+
+	/* Root domain memory region end */
+	root_memregs[root_memregs_count].order = 0;
+
+	/* Root domain boot HART id is same as coldboot HART id */
+	root.boot_hartid = cold_hartid;
+
+	/* Root domain next booting stage details */
+	root.next_arg1 = scratch->next_arg1;
+	root.next_addr = scratch->next_addr;
+	root.next_mode = scratch->next_mode;
+
+	/* Root domain possible and assigned HARTs */
+	for (i = 0; i < SBI_HARTMASK_MAX_BITS; i++) {
+		if (sbi_platform_hart_invalid(plat, i))
+			continue;
+		sbi_hartmask_set_hart(i, &root_hmask);
+	}
+
+	return sbi_domain_register(&root, &root_hmask);
+}

lib/sbi/sbi_ecall.c

@@ -7,6 +7,7 @@
  *   Anup Patel <anup.patel@wdc.com>
  */
 
+#include <sbi/sbi_console.h>
 #include <sbi/sbi_ecall.h>
 #include <sbi/sbi_ecall_interface.h>
 #include <sbi/sbi_error.h>
@@ -100,19 +101,11 @@ int sbi_ecall_handler(struct sbi_trap_regs *regs)
 	struct sbi_trap_info trap = {0};
 	unsigned long out_val = 0;
 	bool is_0_1_spec = 0;
-	unsigned long args[6];
-
-	args[0] = regs->a0;
-	args[1] = regs->a1;
-	args[2] = regs->a2;
-	args[3] = regs->a3;
-	args[4] = regs->a4;
-	args[5] = regs->a5;
 
 	ext = sbi_ecall_find_extension(extension_id);
 	if (ext && ext->handle) {
 		ret = ext->handle(extension_id, func_id,
-				  args, &out_val, &trap);
+				  regs, &out_val, &trap);
 		if (extension_id >= SBI_EXT_0_1_SET_TIMER &&
 		    extension_id <= SBI_EXT_0_1_SHUTDOWN)
 			is_0_1_spec = 1;
@@ -124,6 +117,13 @@ int sbi_ecall_handler(struct sbi_trap_regs *regs)
 		trap.epc = regs->mepc;
 		sbi_trap_redirect(regs, &trap);
 	} else {
+		if (ret < SBI_LAST_ERR) {
+			sbi_printf("%s: Invalid error %d for ext=0x%lx "
+				   "func=0x%lx\n", __func__, ret,
+				   extension_id, func_id);
+			ret = SBI_ERR_FAILED;
+		}
+
 		/*
 		 * This function should return non-zero value only in case of
 		 * fatal error. However, there is no good way to distinguish
@@ -159,12 +159,18 @@ int sbi_ecall_init(void)
 	if (ret)
 		return ret;
 	ret = sbi_ecall_register_extension(&ecall_hsm);
+	if (ret)
+		return ret;
+	ret = sbi_ecall_register_extension(&ecall_srst);
 	if (ret)
 		return ret;
 	ret = sbi_ecall_register_extension(&ecall_legacy);
 	if (ret)
 		return ret;
 	ret = sbi_ecall_register_extension(&ecall_vendor);
+	if (ret)
+		return ret;
+	ret = sbi_ecall_register_extension(&ecall_susp);
 	if (ret)
 		return ret;
 

lib/sbi/sbi_ecall_base.c

@@ -11,8 +11,10 @@
 #include <sbi/sbi_ecall.h>
 #include <sbi/sbi_ecall_interface.h>
 #include <sbi/sbi_error.h>
+#include <sbi/sbi_trap.h>
 #include <sbi/sbi_version.h>
 #include <sbi/riscv_asm.h>
+#include <sbi/riscv_io.h>
 
 static int sbi_ecall_base_probe(unsigned long extid, unsigned long *out_val)
 {
@@ -31,8 +33,44 @@ static int sbi_ecall_base_probe(unsigned long extid, unsigned long *out_val)
 	return 0;
 }
 
+#define SEC_SYS_BASE (0x020B0000)
+static int sbi_ecall_base_rst_c906l(void)
+{
+	unsigned int value;
+
+	value = readl((void *)0x3003024);
+	writel((value & (~(1 << 6))), (void *)0x3003024);
+
+	return 0;
+}
+
+static int sbi_ecall_base_unrst_c906l(const unsigned long address)
+{
+	unsigned int value;
+
+	value = readl((void *)SEC_SYS_BASE + 0x04);
+	writel((value | (1 << 13)), (void *)SEC_SYS_BASE + 0x04);
+	writel(address, (void *)SEC_SYS_BASE + 0x20);
+	writel((address >> 32), (void *)SEC_SYS_BASE + 0x24);
+
+	value = readl((void *)0x3003024);
+	writel((value | (1 << 6)), (void *)0x3003024);
+
+	return 0;
+}
+
+static int sbi_ecall_base_reset_c906l(const unsigned long address)
+{
+	sbi_ecall_base_rst_c906l();
+
+	sbi_ecall_base_unrst_c906l(address);
+
+	return 0;
+}
+
 static int sbi_ecall_base_handler(unsigned long extid, unsigned long funcid,
-				  unsigned long *args, unsigned long *out_val,
+				  const struct sbi_trap_regs *regs,
+				  unsigned long *out_val,
 				  struct sbi_trap_info *out_trap)
 {
 	int ret = 0;
@@ -61,7 +99,17 @@ static int sbi_ecall_base_handler(unsigned long extid, unsigned long funcid,
 		*out_val = csr_read(CSR_MIMPID);
 		break;
 	case SBI_EXT_BASE_PROBE_EXT:
-		ret = sbi_ecall_base_probe(args[0], out_val);
+		ret = sbi_ecall_base_probe(regs->a0, out_val);
+		break;
+	case SBI_EXT_BASE_RESET_C906L:
+		ret = sbi_ecall_base_reset_c906l(regs->a0);
+		*out_val = regs->a0;
+		break;
+	case SBI_EXT_BASE_RST_C906L:
+		ret = sbi_ecall_base_rst_c906l();
+		break;
+	case SBI_EXT_BASE_UNRST_C906L:
+		ret = sbi_ecall_base_unrst_c906l(regs->a0);
 		break;
 	default:
 		ret = SBI_ENOTSUPP;

lib/sbi/sbi_ecall_hsm.c

@@ -7,31 +7,41 @@
  *   Atish Patra <atish.patra@wdc.com>
  */
 
+#include <sbi/sbi_domain.h>
 #include <sbi/sbi_ecall.h>
 #include <sbi/sbi_ecall_interface.h>
 #include <sbi/sbi_error.h>
+#include <sbi/sbi_trap.h>
 #include <sbi/sbi_version.h>
 #include <sbi/sbi_hsm.h>
 #include <sbi/sbi_scratch.h>
 #include <sbi/riscv_asm.h>
 
 static int sbi_ecall_hsm_handler(unsigned long extid, unsigned long funcid,
-				 unsigned long *args, unsigned long *out_val,
+				 const struct sbi_trap_regs *regs,
+				 unsigned long *out_val,
 				 struct sbi_trap_info *out_trap)
 {
-	int ret = 0, hstate;
+	int ret = 0;
 	struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
+	ulong smode = (csr_read(CSR_MSTATUS) & MSTATUS_MPP) >>
+			MSTATUS_MPP_SHIFT;
 
 	switch (funcid) {
 	case SBI_EXT_HSM_HART_START:
-		ret = sbi_hsm_hart_start(scratch, args[0], args[1], args[2]);
+		ret = sbi_hsm_hart_start(scratch, sbi_domain_thishart_ptr(),
+					 regs->a0, regs->a1, smode, regs->a2);
 		break;
 	case SBI_EXT_HSM_HART_STOP:
 		ret = sbi_hsm_hart_stop(scratch, TRUE);
 		break;
 	case SBI_EXT_HSM_HART_GET_STATUS:
-		hstate = sbi_hsm_hart_get_state(args[0]);
-		ret = sbi_hsm_hart_state_to_status(hstate);
+		ret = sbi_hsm_hart_get_state(sbi_domain_thishart_ptr(),
+					     regs->a0);
+		break;
+	case SBI_EXT_HSM_HART_SUSPEND:
+		ret = sbi_hsm_hart_suspend(scratch, regs->a0, regs->a1,
+					   smode, regs->a2);
 		break;
 	default:
 		ret = SBI_ENOTSUPP;

lib/sbi/sbi_ecall_legacy.c

@@ -10,11 +10,13 @@
 
 #include <sbi/riscv_asm.h>
 #include <sbi/sbi_console.h>
+#include <sbi/sbi_domain.h>
 #include <sbi/sbi_ecall.h>
 #include <sbi/sbi_ecall_interface.h>
 #include <sbi/sbi_error.h>
 #include <sbi/sbi_hsm.h>
 #include <sbi/sbi_ipi.h>
+#include <sbi/sbi_platform.h>
 #include <sbi/sbi_system.h>
 #include <sbi/sbi_timer.h>
 #include <sbi/sbi_tlb.h>
@@ -32,7 +34,8 @@ static int sbi_load_hart_mask_unpriv(ulong *pmask, ulong *hmask,
 		if (uptrap->cause)
 			return SBI_ETRAP;
 	} else {
-		sbi_hsm_hart_started_mask(0, &mask);
+		sbi_hsm_hart_interruptible_mask(sbi_domain_thishart_ptr(),
+						0, &mask);
 	}
 	*hmask = mask;
 
@@ -40,7 +43,8 @@ static int sbi_load_hart_mask_unpriv(ulong *pmask, ulong *hmask,
 }
 
 static int sbi_ecall_legacy_handler(unsigned long extid, unsigned long funcid,
-				    unsigned long *args, unsigned long *out_val,
+				    const struct sbi_trap_regs *regs,
+				    unsigned long *out_val,
 				    struct sbi_trap_info *out_trap)
 {
 	int ret = 0;
@@ -51,13 +55,13 @@ static int sbi_ecall_legacy_handler(unsigned long extid, unsigned long funcid,
 	switch (extid) {
 	case SBI_EXT_0_1_SET_TIMER:
 #if __riscv_xlen == 32
-		sbi_timer_event_start((((u64)args[1] << 32) | (u64)args[0]));
+		sbi_timer_event_start((((u64)regs->a1 << 32) | (u64)regs->a0));
 #else
-		sbi_timer_event_start((u64)args[0]);
+		sbi_timer_event_start((u64)regs->a0);
 #endif
 		break;
 	case SBI_EXT_0_1_CONSOLE_PUTCHAR:
-		sbi_putc(args[0]);
+		sbi_putc(regs->a0);
 		break;
 	case SBI_EXT_0_1_CONSOLE_GETCHAR:
 		ret = sbi_getc();
@@ -66,40 +70,45 @@ static int sbi_ecall_legacy_handler(unsigned long extid, unsigned long funcid,
 		sbi_ipi_clear_smode();
 		break;
 	case SBI_EXT_0_1_SEND_IPI:
-		ret = sbi_load_hart_mask_unpriv((ulong *)args[0],
+		ret = sbi_load_hart_mask_unpriv((ulong *)regs->a0,
 						&hmask, out_trap);
 		if (ret != SBI_ETRAP)
 			ret = sbi_ipi_send_smode(hmask, 0);
 		break;
 	case SBI_EXT_0_1_REMOTE_FENCE_I:
-		ret = sbi_load_hart_mask_unpriv((ulong *)args[0],
+		ret = sbi_load_hart_mask_unpriv((ulong *)regs->a0,
 						&hmask, out_trap);
 		if (ret != SBI_ETRAP) {
-			SBI_TLB_INFO_INIT(&tlb_info, 0, 0, 0,
-					  SBI_ITLB_FLUSH, source_hart);
+			SBI_TLB_INFO_INIT(&tlb_info, 0, 0, 0, 0,
+					  sbi_tlb_local_fence_i,
+					  source_hart);
 			ret = sbi_tlb_request(hmask, 0, &tlb_info);
 		}
 		break;
 	case SBI_EXT_0_1_REMOTE_SFENCE_VMA:
-		ret = sbi_load_hart_mask_unpriv((ulong *)args[0],
+		ret = sbi_load_hart_mask_unpriv((ulong *)regs->a0,
 						&hmask, out_trap);
 		if (ret != SBI_ETRAP) {
-			SBI_TLB_INFO_INIT(&tlb_info, args[1], args[2], 0,
-					  SBI_TLB_FLUSH_VMA, source_hart);
+			SBI_TLB_INFO_INIT(&tlb_info, regs->a1, regs->a2, 0, 0,
+					  sbi_tlb_local_sfence_vma,
+					  source_hart);
 			ret = sbi_tlb_request(hmask, 0, &tlb_info);
 		}
 		break;
 	case SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID:
-		ret = sbi_load_hart_mask_unpriv((ulong *)args[0],
+		ret = sbi_load_hart_mask_unpriv((ulong *)regs->a0,
 						&hmask, out_trap);
 		if (ret != SBI_ETRAP) {
-			SBI_TLB_INFO_INIT(&tlb_info, args[1], args[2], args[3],
-					  SBI_TLB_FLUSH_VMA_ASID, source_hart);
+			SBI_TLB_INFO_INIT(&tlb_info, regs->a1,
+					  regs->a2, regs->a3, 0,
+					  sbi_tlb_local_sfence_vma_asid,
+					  source_hart);
 			ret = sbi_tlb_request(hmask, 0, &tlb_info);
 		}
 		break;
 	case SBI_EXT_0_1_SHUTDOWN:
-		sbi_system_shutdown(0);
+		sbi_system_reset(SBI_SRST_RESET_TYPE_SHUTDOWN,
+				 SBI_SRST_RESET_REASON_NONE);
 		break;
 	default:
 		ret = SBI_ENOTSUPP;

lib/sbi/sbi_ecall_replace.c

@@ -14,20 +14,23 @@
 #include <sbi/sbi_error.h>
 #include <sbi/sbi_hart.h>
 #include <sbi/sbi_ipi.h>
+#include <sbi/sbi_system.h>
 #include <sbi/sbi_timer.h>
 #include <sbi/sbi_tlb.h>
+#include <sbi/sbi_trap.h>
 
 static int sbi_ecall_time_handler(unsigned long extid, unsigned long funcid,
-				  unsigned long *args, unsigned long *out_val,
+				  const struct sbi_trap_regs *regs,
+				  unsigned long *out_val,
 				  struct sbi_trap_info *out_trap)
 {
 	int ret = 0;
 
 	if (funcid == SBI_EXT_TIME_SET_TIMER) {
 #if __riscv_xlen == 32
-		sbi_timer_event_start((((u64)args[1] << 32) | (u64)args[0]));
+		sbi_timer_event_start((((u64)regs->a1 << 32) | (u64)regs->a0));
 #else
-		sbi_timer_event_start((u64)args[0]);
+		sbi_timer_event_start((u64)regs->a0);
 #endif
 	} else
 		ret = SBI_ENOTSUPP;
@@ -42,10 +45,12 @@ struct sbi_ecall_extension ecall_time = {
 };
 
 static int sbi_ecall_rfence_handler(unsigned long extid, unsigned long funcid,
-				    unsigned long *args, unsigned long *out_val,
+				    const struct sbi_trap_regs *regs,
+				    unsigned long *out_val,
 				    struct sbi_trap_info *out_trap)
 {
 	int ret = 0;
+	unsigned long vmid;
 	struct sbi_tlb_info tlb_info;
 	u32 source_hart = current_hartid();
 
@@ -56,39 +61,45 @@ static int sbi_ecall_rfence_handler(unsigned long extid, unsigned long funcid,
 
 	switch (funcid) {
 	case SBI_EXT_RFENCE_REMOTE_FENCE_I:
-		SBI_TLB_INFO_INIT(&tlb_info, 0, 0, 0,
-				  SBI_ITLB_FLUSH, source_hart);
-		ret = sbi_tlb_request(args[0], args[1], &tlb_info);
+		SBI_TLB_INFO_INIT(&tlb_info, 0, 0, 0, 0,
+				  sbi_tlb_local_fence_i, source_hart);
+		ret = sbi_tlb_request(regs->a0, regs->a1, &tlb_info);
 		break;
 	case SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA:
-		SBI_TLB_INFO_INIT(&tlb_info, args[2], args[3], 0,
-				  SBI_TLB_FLUSH_GVMA, source_hart);
-		ret = sbi_tlb_request(args[0], args[1], &tlb_info);
+		SBI_TLB_INFO_INIT(&tlb_info, regs->a2, regs->a3, 0, 0,
+				  sbi_tlb_local_hfence_gvma, source_hart);
+		ret = sbi_tlb_request(regs->a0, regs->a1, &tlb_info);
 		break;
 	case SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID:
-		SBI_TLB_INFO_INIT(&tlb_info, args[2], args[3], args[4],
-				  SBI_TLB_FLUSH_GVMA_VMID, source_hart);
-		ret = sbi_tlb_request(args[0], args[1], &tlb_info);
+		SBI_TLB_INFO_INIT(&tlb_info, regs->a2, regs->a3, 0, regs->a4,
+				  sbi_tlb_local_hfence_gvma_vmid,
+				  source_hart);
+		ret = sbi_tlb_request(regs->a0, regs->a1, &tlb_info);
 		break;
 	case SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA:
-		SBI_TLB_INFO_INIT(&tlb_info, args[2], args[3], 0,
-				  SBI_TLB_FLUSH_VVMA, source_hart);
-		ret = sbi_tlb_request(args[0], args[1], &tlb_info);
+		vmid = (csr_read(CSR_HGATP) & HGATP_VMID_MASK);
+		vmid = vmid >> HGATP_VMID_SHIFT;
+		SBI_TLB_INFO_INIT(&tlb_info, regs->a2, regs->a3, 0, vmid,
+				  sbi_tlb_local_hfence_vvma, source_hart);
+		ret = sbi_tlb_request(regs->a0, regs->a1, &tlb_info);
 		break;
 	case SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID:
-		SBI_TLB_INFO_INIT(&tlb_info, args[2], args[3], args[4],
-				  SBI_TLB_FLUSH_VVMA_ASID, source_hart);
-		ret = sbi_tlb_request(args[0], args[1], &tlb_info);
+		vmid = (csr_read(CSR_HGATP) & HGATP_VMID_MASK);
+		vmid = vmid >> HGATP_VMID_SHIFT;
+		SBI_TLB_INFO_INIT(&tlb_info, regs->a2, regs->a3, regs->a4,
+				  vmid, sbi_tlb_local_hfence_vvma_asid,
+				  source_hart);
+		ret = sbi_tlb_request(regs->a0, regs->a1, &tlb_info);
 		break;
 	case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA:
-		SBI_TLB_INFO_INIT(&tlb_info, args[2], args[3], 0,
-				  SBI_TLB_FLUSH_VMA, source_hart);
-		ret = sbi_tlb_request(args[0], args[1], &tlb_info);
+		SBI_TLB_INFO_INIT(&tlb_info, regs->a2, regs->a3, 0, 0,
+				  sbi_tlb_local_sfence_vma, source_hart);
+		ret = sbi_tlb_request(regs->a0, regs->a1, &tlb_info);
 		break;
 	case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID:
-		SBI_TLB_INFO_INIT(&tlb_info, args[2], args[3], args[4],
-				  SBI_TLB_FLUSH_VMA_ASID, source_hart);
-		ret = sbi_tlb_request(args[0], args[1], &tlb_info);
+		SBI_TLB_INFO_INIT(&tlb_info, regs->a2, regs->a3, regs->a4, 0,
+				  sbi_tlb_local_sfence_vma_asid, source_hart);
+		ret = sbi_tlb_request(regs->a0, regs->a1, &tlb_info);
 		break;
 	default:
 		ret = SBI_ENOTSUPP;
@@ -104,13 +115,14 @@ struct sbi_ecall_extension ecall_rfence = {
 };
 
 static int sbi_ecall_ipi_handler(unsigned long extid, unsigned long funcid,
-				 unsigned long *args, unsigned long *out_val,
+				 const struct sbi_trap_regs *regs,
+				 unsigned long *out_val,
 				 struct sbi_trap_info *out_trap)
 {
 	int ret = 0;
 
 	if (funcid == SBI_EXT_IPI_SEND_IPI)
-		ret = sbi_ipi_send_smode(args[0], args[1]);
+		ret = sbi_ipi_send_smode(regs->a0, regs->a1);
 	else
 		ret = SBI_ENOTSUPP;
 
@@ -122,3 +134,63 @@ struct sbi_ecall_extension ecall_ipi = {
 	.extid_end = SBI_EXT_IPI,
 	.handle = sbi_ecall_ipi_handler,
 };
+
+static int sbi_ecall_srst_handler(unsigned long extid, unsigned long funcid,
+				  const struct sbi_trap_regs *regs,
+				  unsigned long *out_val,
+				  struct sbi_trap_info *out_trap)
+{
+	if (funcid == SBI_EXT_SRST_RESET) {
+		if ((((u32)-1U) <= ((u64)regs->a0)) ||
+		    (((u32)-1U) <= ((u64)regs->a1)))
+			return SBI_EINVAL;
+
+		switch (regs->a0) {
+		case SBI_SRST_RESET_TYPE_SHUTDOWN:
+		case SBI_SRST_RESET_TYPE_COLD_REBOOT:
+		case SBI_SRST_RESET_TYPE_WARM_REBOOT:
+			break;
+		default:
+			return SBI_ENOTSUPP;
+		}
+
+		switch (regs->a1) {
+		case SBI_SRST_RESET_REASON_NONE:
+		case SBI_SRST_RESET_REASON_SYSFAIL:
+			break;
+		default:
+			return SBI_ENOTSUPP;
+		}
+
+		if (sbi_system_reset_supported(regs->a0, regs->a1))
+			sbi_system_reset(regs->a0, regs->a1);
+	}
+
+	return SBI_ENOTSUPP;
+}
+
+static int sbi_ecall_srst_probe(unsigned long extid, unsigned long *out_val)
+{
+	u32 type, count = 0;
+
+	/*
+	 * At least one standard reset types should be supported by
+	 * the platform for SBI SRST extension to be usable.
+	 */
+
+	for (type = 0; type <= SBI_SRST_RESET_TYPE_LAST; type++) {
+		if (sbi_system_reset_supported(type,
+					SBI_SRST_RESET_REASON_NONE))
+			count++;
+	}
+
+	*out_val = (count) ? 1 : 0;
+	return 0;
+}
+
+struct sbi_ecall_extension ecall_srst = {
+	.extid_start = SBI_EXT_SRST,
+	.extid_end = SBI_EXT_SRST,
+	.handle = sbi_ecall_srst_handler,
+	.probe = sbi_ecall_srst_probe,
+};

lib/sbi/sbi_ecall_susp.c

@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: BSD-2-Clause
+#include <sbi/sbi_ecall.h>
+#include <sbi/sbi_ecall_interface.h>
+#include <sbi/sbi_error.h>
+#include <sbi/sbi_trap.h>
+#include <sbi/sbi_system.h>
+
+static int sbi_ecall_susp_handler(unsigned long extid, unsigned long funcid,
+				    const struct sbi_trap_regs *regs,
+				    unsigned long *out_val,
+				    struct sbi_trap_info *out_trap)
+{
+	int ret = SBI_ENOTSUPP;
+
+	if (funcid == SBI_EXT_SUSP_SUSPEND)
+		ret = sbi_system_suspend(regs->a0, regs->a1, regs->a2);
+
+	if (ret >= 0) {
+		*out_val = ret;
+		ret = 0;
+	}
+
+	return ret;
+}
+
+static bool susp_available(void)
+{
+	u32 type;
+
+	/*
+	 * At least one suspend type should be supported by the
+	 * platform for the SBI SUSP extension to be usable.
+	 */
+	for (type = 0; type <= SBI_SUSP_SLEEP_TYPE_LAST; type++) {
+		if (sbi_system_suspend_supported(type))
+			return true;
+	}
+
+	return false;
+}
+
+struct sbi_ecall_extension ecall_susp;
+
+static int sbi_ecall_susp_register_extensions(unsigned long extid, unsigned long *out_val)
+{
+	if (!susp_available()) {
+		*out_val = 0;
+		return 0;
+	}
+
+	*out_val = 1;
+	return 0;
+}
+
+struct sbi_ecall_extension ecall_susp = {
+	.extid_start		= SBI_EXT_SUSP,
+	.extid_end		= SBI_EXT_SUSP,
+	.probe			= sbi_ecall_susp_register_extensions,
+	.handle			= sbi_ecall_susp_handler,
+};

lib/sbi/sbi_ecall_vendor.c

@@ -12,6 +12,7 @@
 #include <sbi/sbi_ecall_interface.h>
 #include <sbi/sbi_error.h>
 #include <sbi/sbi_platform.h>
+#include <sbi/sbi_trap.h>
 
 static int sbi_ecall_vendor_probe(unsigned long extid,
 				  unsigned long *out_val)
@@ -22,11 +23,12 @@ static int sbi_ecall_vendor_probe(unsigned long extid,
 }
 
 static int sbi_ecall_vendor_handler(unsigned long extid, unsigned long funcid,
-				    unsigned long *args, unsigned long *out_val,
+				    const struct sbi_trap_regs *regs,
+				    unsigned long *out_val,
 				    struct sbi_trap_info *out_trap)
 {
 	return sbi_platform_vendor_ext_provider(sbi_platform_thishart_ptr(),
-						extid, funcid, args,
+						extid, funcid, regs,
 						out_val, out_trap);
 }
 

lib/sbi/sbi_emulate_csr.c

@@ -13,14 +13,40 @@
 #include <sbi/sbi_console.h>
 #include <sbi/sbi_emulate_csr.h>
 #include <sbi/sbi_error.h>
+#include <sbi/sbi_hart.h>
+#include <sbi/sbi_scratch.h>
 #include <sbi/sbi_timer.h>
 #include <sbi/sbi_trap.h>
 
+static bool hpm_allowed(int hpm_num, ulong prev_mode, bool virt)
+{
+	ulong cen = -1UL;
+	struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
+
+	if (prev_mode <= PRV_S) {
+		if (sbi_hart_has_feature(scratch, SBI_HART_HAS_MCOUNTEREN)) {
+			cen &= csr_read(CSR_MCOUNTEREN);
+			if (virt)
+				cen &= csr_read(CSR_HCOUNTEREN);
+		} else {
+			cen = 0;
+		}
+	}
+	if (prev_mode == PRV_U) {
+		if (sbi_hart_has_feature(scratch, SBI_HART_HAS_SCOUNTEREN))
+			cen &= csr_read(CSR_SCOUNTEREN);
+		else
+			cen = 0;
+	}
+
+	return ((cen >> hpm_num) & 1) ? TRUE : FALSE;
+}
+
 int sbi_emulate_csr_read(int csr_num, struct sbi_trap_regs *regs,
 			 ulong *csr_val)
 {
 	int ret = 0;
-	ulong cen = -1UL;
+	struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
 	ulong prev_mode = (regs->mstatus & MSTATUS_MPP) >> MSTATUS_MPP_SHIFT;
 #if __riscv_xlen == 32
 	bool virt = (regs->mstatusH & MSTATUSH_MPV) ? TRUE : FALSE;
@@ -28,9 +54,6 @@ int sbi_emulate_csr_read(int csr_num, struct sbi_trap_regs *regs,
 	bool virt = (regs->mstatus & MSTATUS_MPV) ? TRUE : FALSE;
 #endif
 
-	if (prev_mode == PRV_U)
-		cen = csr_read(CSR_SCOUNTEREN);
-
 	switch (csr_num) {
 	case CSR_HTIMEDELTA:
 		if (prev_mode == PRV_S && !virt)
@@ -39,31 +62,27 @@ int sbi_emulate_csr_read(int csr_num, struct sbi_trap_regs *regs,
 			ret = SBI_ENOTSUPP;
 		break;
 	case CSR_CYCLE:
-		if (!((cen >> (CSR_CYCLE - CSR_CYCLE)) & 1))
-			return -1;
+		if (!hpm_allowed(csr_num - CSR_CYCLE, prev_mode, virt))
+			return SBI_ENOTSUPP;
 		*csr_val = csr_read(CSR_MCYCLE);
 		break;
 	case CSR_TIME:
-		if (!((cen >> (CSR_TIME - CSR_CYCLE)) & 1))
-			return -1;
+		/*
+		 * We emulate TIME CSR for both Host (HS/U-mode) and
+		 * Guest (VS/VU-mode).
+		 *
+		 * Faster TIME CSR reads are critical for good performance
+		 * in S-mode software so we don't check CSR permissions.
+		 */
 		*csr_val = (virt) ? sbi_timer_virt_value():
 				    sbi_timer_value();
 		break;
 	case CSR_INSTRET:
-		if (!((cen >> (CSR_INSTRET - CSR_CYCLE)) & 1))
-			return -1;
+		if (!hpm_allowed(csr_num - CSR_CYCLE, prev_mode, virt))
+			return SBI_ENOTSUPP;
 		*csr_val = csr_read(CSR_MINSTRET);
 		break;
-	case CSR_MHPMCOUNTER3:
-		if (!((cen >> (3 + CSR_MHPMCOUNTER3 - CSR_MHPMCOUNTER3)) & 1))
-			return -1;
-		*csr_val = csr_read(CSR_MHPMCOUNTER3);
-		break;
-	case CSR_MHPMCOUNTER4:
-		if (!((cen >> (3 + CSR_MHPMCOUNTER4 - CSR_MHPMCOUNTER3)) & 1))
-			return -1;
-		*csr_val = csr_read(CSR_MHPMCOUNTER4);
-		break;
+
 #if __riscv_xlen == 32
 	case CSR_HTIMEDELTAH:
 		if (prev_mode == PRV_S && !virt)
@@ -72,38 +91,61 @@ int sbi_emulate_csr_read(int csr_num, struct sbi_trap_regs *regs,
 			ret = SBI_ENOTSUPP;
 		break;
 	case CSR_CYCLEH:
-		if (!((cen >> (CSR_CYCLE - CSR_CYCLE)) & 1))
-			return -1;
+		if (!hpm_allowed(csr_num - CSR_CYCLEH, prev_mode, virt))
+			return SBI_ENOTSUPP;
 		*csr_val = csr_read(CSR_MCYCLEH);
 		break;
 	case CSR_TIMEH:
-		if (!((cen >> (CSR_TIME - CSR_CYCLE)) & 1))
-			return -1;
+		/* Refer comments on TIME CSR above. */
 		*csr_val = (virt) ? sbi_timer_virt_value() >> 32:
 				    sbi_timer_value() >> 32;
 		break;
 	case CSR_INSTRETH:
-		if (!((cen >> (CSR_INSTRET - CSR_CYCLE)) & 1))
-			return -1;
+		if (!hpm_allowed(csr_num - CSR_CYCLEH, prev_mode, virt))
+			return SBI_ENOTSUPP;
 		*csr_val = csr_read(CSR_MINSTRETH);
 		break;
-	case CSR_MHPMCOUNTER3H:
-		if (!((cen >> (3 + CSR_MHPMCOUNTER3 - CSR_MHPMCOUNTER3)) & 1))
-			return -1;
-		*csr_val = csr_read(CSR_MHPMCOUNTER3H);
-		break;
-	case CSR_MHPMCOUNTER4H:
-		if (!((cen >> (3 + CSR_MHPMCOUNTER4 - CSR_MHPMCOUNTER3)) & 1))
-			return -1;
-		*csr_val = csr_read(CSR_MHPMCOUNTER4H);
-		break;
 #endif
-	case CSR_MHPMEVENT3:
-		*csr_val = csr_read(CSR_MHPMEVENT3);
-		break;
-	case CSR_MHPMEVENT4:
-		*csr_val = csr_read(CSR_MHPMEVENT4);
+
+#define switchcase_hpm(__uref, __mref, __csr)				\
+	case __csr:							\
+		if ((sbi_hart_mhpm_count(scratch) + 3) <= (__csr - __uref))\
+			return SBI_ENOTSUPP;				\
+		if (!hpm_allowed(__csr - __uref, prev_mode, virt))	\
+			return SBI_ENOTSUPP;				\
+		*csr_val = csr_read(__mref + __csr - __uref);		\
 		break;
+#define switchcase_hpm_2(__uref, __mref, __csr)			\
+	switchcase_hpm(__uref, __mref, __csr + 0)			\
+	switchcase_hpm(__uref, __mref, __csr + 1)
+#define switchcase_hpm_4(__uref, __mref, __csr)			\
+	switchcase_hpm_2(__uref, __mref, __csr + 0)			\
+	switchcase_hpm_2(__uref, __mref, __csr + 2)
+#define switchcase_hpm_8(__uref, __mref, __csr)			\
+	switchcase_hpm_4(__uref, __mref, __csr + 0)			\
+	switchcase_hpm_4(__uref, __mref, __csr + 4)
+#define switchcase_hpm_16(__uref, __mref, __csr)			\
+	switchcase_hpm_8(__uref, __mref, __csr + 0)			\
+	switchcase_hpm_8(__uref, __mref, __csr + 8)
+
+	switchcase_hpm(CSR_CYCLE, CSR_MCYCLE, CSR_HPMCOUNTER3)
+	switchcase_hpm_4(CSR_CYCLE, CSR_MCYCLE, CSR_HPMCOUNTER4)
+	switchcase_hpm_8(CSR_CYCLE, CSR_MCYCLE, CSR_HPMCOUNTER8)
+	switchcase_hpm_16(CSR_CYCLE, CSR_MCYCLE, CSR_HPMCOUNTER16)
+
+#if __riscv_xlen == 32
+	switchcase_hpm(CSR_CYCLEH, CSR_MCYCLEH, CSR_HPMCOUNTER3H)
+	switchcase_hpm_4(CSR_CYCLEH, CSR_MCYCLEH, CSR_HPMCOUNTER4H)
+	switchcase_hpm_8(CSR_CYCLEH, CSR_MCYCLEH, CSR_HPMCOUNTER8H)
+	switchcase_hpm_16(CSR_CYCLEH, CSR_MCYCLEH, CSR_HPMCOUNTER16H)
+#endif
+
+#undef switchcase_hpm_16
+#undef switchcase_hpm_8
+#undef switchcase_hpm_4
+#undef switchcase_hpm_2
+#undef switchcase_hpm
+
 	default:
 		ret = SBI_ENOTSUPP;
 		break;
@@ -134,18 +176,6 @@ int sbi_emulate_csr_write(int csr_num, struct sbi_trap_regs *regs,
 		else
 			ret = SBI_ENOTSUPP;
 		break;
-	case CSR_CYCLE:
-		csr_write(CSR_MCYCLE, csr_val);
-		break;
-	case CSR_INSTRET:
-		csr_write(CSR_MINSTRET, csr_val);
-		break;
-	case CSR_MHPMCOUNTER3:
-		csr_write(CSR_MHPMCOUNTER3, csr_val);
-		break;
-	case CSR_MHPMCOUNTER4:
-		csr_write(CSR_MHPMCOUNTER4, csr_val);
-		break;
 #if __riscv_xlen == 32
 	case CSR_HTIMEDELTAH:
 		if (prev_mode == PRV_S && !virt)
@@ -153,25 +183,7 @@ int sbi_emulate_csr_write(int csr_num, struct sbi_trap_regs *regs,
 		else
 			ret = SBI_ENOTSUPP;
 		break;
-	case CSR_CYCLEH:
-		csr_write(CSR_MCYCLEH, csr_val);
-		break;
-	case CSR_INSTRETH:
-		csr_write(CSR_MINSTRETH, csr_val);
-		break;
-	case CSR_MHPMCOUNTER3H:
-		csr_write(CSR_MHPMCOUNTER3H, csr_val);
-		break;
-	case CSR_MHPMCOUNTER4H:
-		csr_write(CSR_MHPMCOUNTER4H, csr_val);
-		break;
 #endif
-	case CSR_MHPMEVENT3:
-		csr_write(CSR_MHPMEVENT3, csr_val);
-		break;
-	case CSR_MHPMEVENT4:
-		csr_write(CSR_MHPMEVENT4, csr_val);
-		break;
 	default:
 		ret = SBI_ENOTSUPP;
 		break;

lib/sbi/sbi_expected_trap.S

@@ -11,8 +11,8 @@
 #include <sbi/sbi_trap.h>
 
 	/*
-	 * We assume that faulting unpriv load/store instruction is
-	 * is 4-byte long and blindly increment SEPC by 4.
+	 * We assume that faulting instruction is is 4-byte long and blindly
+	 * increment SEPC by 4.
 	 *
 	 * The trap info will be saved as follows:
 	 * A3 <- pointer struct sbi_trap_info
@@ -20,8 +20,8 @@
 	 */
 
 	.align 3
-	.global __sbi_unpriv_trap
-__sbi_unpriv_trap:
+	.global __sbi_expected_trap
+__sbi_expected_trap:
 	/* Without H-extension so, MTVAL2 and MTINST CSRs not available */
 	csrr	a4, CSR_MEPC
 	REG_S	a4, SBI_TRAP_INFO_OFFSET(epc)(a3)
@@ -37,8 +37,8 @@ __sbi_unpriv_trap:
 	mret
 
 	.align 3
-	.global __sbi_unpriv_trap_hext
-__sbi_unpriv_trap_hext:
+	.global __sbi_expected_trap_hext
+__sbi_expected_trap_hext:
 	/* With H-extension so, MTVAL2 and MTINST CSRs available */
 	csrr	a4, CSR_MEPC
 	REG_S	a4, SBI_TRAP_INFO_OFFSET(epc)(a3)

lib/sbi/sbi_fifo.c

@@ -18,7 +18,7 @@ void sbi_fifo_init(struct sbi_fifo *fifo, void *queue_mem, u16 entries,
 	fifo->queue	  = queue_mem;
 	fifo->num_entries = entries;
 	fifo->entry_size  = entry_size;
-	SPIN_LOCK_INIT(&fifo->qlock);
+	SPIN_LOCK_INIT(fifo->qlock);
 	fifo->avail = fifo->tail = 0;
 	sbi_memset(fifo->queue, 0, (size_t)entries * entry_size);
 }

lib/sbi/sbi_hart.c

@@ -13,18 +13,31 @@
 #include <sbi/riscv_fp.h>
 #include <sbi/sbi_bitops.h>
 #include <sbi/sbi_console.h>
+#include <sbi/sbi_domain.h>
+#include <sbi/sbi_csr_detect.h>
 #include <sbi/sbi_error.h>
 #include <sbi/sbi_hart.h>
+#include <sbi/sbi_math.h>
 #include <sbi/sbi_platform.h>
+#include <sbi/sbi_string.h>
+#include <sbi/sbi_trap.h>
 
-extern void __sbi_unpriv_trap(void);
-extern void __sbi_unpriv_trap_hext(void);
+extern void __sbi_expected_trap(void);
+extern void __sbi_expected_trap_hext(void);
 
-void (*sbi_hart_unpriv_trap)(void) = &__sbi_unpriv_trap;
+void (*sbi_hart_expected_trap)(void) = &__sbi_expected_trap;
 
-static void mstatus_init(struct sbi_scratch *scratch, u32 hartid)
+struct hart_features {
+	unsigned long features;
+	unsigned int pmp_count;
+	unsigned int pmp_addr_bits;
+	unsigned long pmp_gran;
+	unsigned int mhpm_count;
+};
+static unsigned long hart_features_offset;
+
+static void mstatus_init(struct sbi_scratch *scratch)
 {
-	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
 	unsigned long mstatus_val = 0;
 
 	/* Enable FPU */
@@ -38,9 +51,10 @@ static void mstatus_init(struct sbi_scratch *scratch, u32 hartid)
 	csr_write(CSR_MSTATUS, mstatus_val);
 
 	/* Enable user/supervisor use of perf counters */
-	if (misa_extension('S') && sbi_platform_has_scounteren(plat))
+	if (misa_extension('S') &&
+	    sbi_hart_has_feature(scratch, SBI_HART_HAS_SCOUNTEREN))
 		csr_write(CSR_SCOUNTEREN, -1);
-	if (sbi_platform_has_mcounteren(plat))
+	if (sbi_hart_has_feature(scratch, SBI_HART_HAS_MCOUNTEREN))
 		csr_write(CSR_MCOUNTEREN, -1);
 
 	/* Disable all interrupts */
@@ -51,7 +65,7 @@ static void mstatus_init(struct sbi_scratch *scratch, u32 hartid)
 		csr_write(CSR_SATP, 0);
 }
 
-static int fp_init(u32 hartid)
+static int fp_init(struct sbi_scratch *scratch)
 {
 #ifdef __riscv_flen
 	int i;
@@ -72,7 +86,7 @@ static int fp_init(u32 hartid)
 	return 0;
 }
 
-static int delegate_traps(struct sbi_scratch *scratch, u32 hartid)
+static int delegate_traps(struct sbi_scratch *scratch)
 {
 	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
 	unsigned long interrupts, exceptions;
@@ -98,9 +112,10 @@ static int delegate_traps(struct sbi_scratch *scratch, u32 hartid)
 	 * from VS-mode), Guest page faults and Virtual interrupts.
 	 */
 	if (misa_extension('H')) {
-		exceptions |= (1U << CAUSE_SUPERVISOR_ECALL);
+		exceptions |= (1U << CAUSE_VIRTUAL_SUPERVISOR_ECALL);
 		exceptions |= (1U << CAUSE_FETCH_GUEST_PAGE_FAULT);
 		exceptions |= (1U << CAUSE_LOAD_GUEST_PAGE_FAULT);
+		exceptions |= (1U << CAUSE_VIRTUAL_INST_FAULT);
 		exceptions |= (1U << CAUSE_STORE_GUEST_PAGE_FAULT);
 	}
 
@@ -110,131 +125,341 @@ static int delegate_traps(struct sbi_scratch *scratch, u32 hartid)
 	return 0;
 }
 
-void sbi_hart_delegation_dump(struct sbi_scratch *scratch)
+void sbi_hart_delegation_dump(struct sbi_scratch *scratch,
+			      const char *prefix, const char *suffix)
 {
-#if __riscv_xlen == 32
-	sbi_printf("MIDELEG : 0x%08lx\n", csr_read(CSR_MIDELEG));
-	sbi_printf("MEDELEG : 0x%08lx\n", csr_read(CSR_MEDELEG));
-#else
-	sbi_printf("MIDELEG : 0x%016lx\n", csr_read(CSR_MIDELEG));
-	sbi_printf("MEDELEG : 0x%016lx\n", csr_read(CSR_MEDELEG));
-#endif
-}
-
-unsigned long log2roundup(unsigned long x)
-{
-	unsigned long ret = 0;
-
-	while (ret < __riscv_xlen) {
-		if (x <= (1UL << ret))
-			break;
-		ret++;
-	}
-
-	return ret;
-}
-
-void sbi_hart_pmp_dump(struct sbi_scratch *scratch)
-{
-	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
-	unsigned long prot, addr, size;
-	unsigned int i;
-
-	if (!sbi_platform_has_pmp(plat))
+	if (!misa_extension('S'))
+		/* No delegation possible as mideleg does not exist*/
 		return;
 
-	for (i = 0; i < PMP_COUNT; i++) {
-		pmp_get(i, &prot, &addr, &size);
-		if (!(prot & PMP_A))
-			continue;
 #if __riscv_xlen == 32
-		sbi_printf("PMP%d    : 0x%08lx-0x%08lx (A",
+	sbi_printf("%sMIDELEG%s: 0x%08lx\n",
+		   prefix, suffix, csr_read(CSR_MIDELEG));
+	sbi_printf("%sMEDELEG%s: 0x%08lx\n",
+		   prefix, suffix, csr_read(CSR_MEDELEG));
 #else
-		sbi_printf("PMP%d    : 0x%016lx-0x%016lx (A",
+	sbi_printf("%sMIDELEG%s: 0x%016lx\n",
+		   prefix, suffix, csr_read(CSR_MIDELEG));
+	sbi_printf("%sMEDELEG%s: 0x%016lx\n",
+		   prefix, suffix, csr_read(CSR_MEDELEG));
 #endif
-			   i, addr, addr + size - 1);
-		if (prot & PMP_L)
-			sbi_printf(",L");
-		if (prot & PMP_R)
-			sbi_printf(",R");
-		if (prot & PMP_W)
-			sbi_printf(",W");
-		if (prot & PMP_X)
-			sbi_printf(",X");
-		sbi_printf(")\n");
-	}
 }
 
-int sbi_hart_pmp_check_addr(struct sbi_scratch *scratch, unsigned long addr,
-			    unsigned long attr)
+unsigned int sbi_hart_mhpm_count(struct sbi_scratch *scratch)
 {
-	unsigned long prot, size, i, tempaddr;
-	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
+	struct hart_features *hfeatures =
+			sbi_scratch_offset_ptr(scratch, hart_features_offset);
 
-	if (!sbi_platform_has_pmp(plat))
-		return SBI_OK;
-
-	for (i = 0; i < PMP_COUNT; i++) {
-		pmp_get(i, &prot, &tempaddr, &size);
-		if (!(prot & PMP_A))
-			continue;
-		if (tempaddr <= addr && addr <= tempaddr + size)
-			if (!(prot & attr))
-				return SBI_INVALID_ADDR;
-	}
-
-	return SBI_OK;
+	return hfeatures->mhpm_count;
 }
 
-static int pmp_init(struct sbi_scratch *scratch, u32 hartid)
+unsigned int sbi_hart_pmp_count(struct sbi_scratch *scratch)
 {
-	u32 i, count;
-	unsigned long fw_start, fw_size_log2;
-	ulong prot, addr, log2size;
-	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
+	struct hart_features *hfeatures =
+			sbi_scratch_offset_ptr(scratch, hart_features_offset);
 
-	if (!sbi_platform_has_pmp(plat))
+	return hfeatures->pmp_count;
+}
+
+unsigned long sbi_hart_pmp_granularity(struct sbi_scratch *scratch)
+{
+	struct hart_features *hfeatures =
+			sbi_scratch_offset_ptr(scratch, hart_features_offset);
+
+	return hfeatures->pmp_gran;
+}
+
+unsigned int sbi_hart_pmp_addrbits(struct sbi_scratch *scratch)
+{
+	struct hart_features *hfeatures =
+			sbi_scratch_offset_ptr(scratch, hart_features_offset);
+
+	return hfeatures->pmp_addr_bits;
+}
+
+int sbi_hart_pmp_configure(struct sbi_scratch *scratch)
+{
+	struct sbi_domain_memregion *reg;
+	struct sbi_domain *dom = sbi_domain_thishart_ptr();
+	unsigned int pmp_idx = 0, pmp_flags, pmp_bits, pmp_gran_log2;
+	unsigned int pmp_count = sbi_hart_pmp_count(scratch);
+	unsigned long pmp_addr = 0, pmp_addr_max = 0;
+
+	if (!pmp_count)
 		return 0;
 
-	fw_size_log2 = log2roundup(scratch->fw_size);
-	fw_start     = scratch->fw_start & ~((1UL << fw_size_log2) - 1UL);
+	pmp_gran_log2 = log2roundup(sbi_hart_pmp_granularity(scratch));
+	pmp_bits = sbi_hart_pmp_addrbits(scratch) - 1;
+	pmp_addr_max = (1UL << pmp_bits) | ((1UL << pmp_bits) - 1);
 
-	pmp_set(0, 0, fw_start, fw_size_log2);
+	sbi_domain_for_each_memregion(dom, reg) {
+		if (pmp_count <= pmp_idx)
+			break;
 
-	count = sbi_platform_pmp_region_count(plat, hartid);
-	if ((PMP_COUNT - 1) < count)
-		count = (PMP_COUNT - 1);
+		pmp_flags = 0;
+		if (reg->flags & SBI_DOMAIN_MEMREGION_READABLE)
+			pmp_flags |= PMP_R;
+		if (reg->flags & SBI_DOMAIN_MEMREGION_WRITEABLE)
+			pmp_flags |= PMP_W;
+		if (reg->flags & SBI_DOMAIN_MEMREGION_EXECUTABLE)
+			pmp_flags |= PMP_X;
+		if (reg->flags & SBI_DOMAIN_MEMREGION_MMODE)
+			pmp_flags |= PMP_L;
 
-	for (i = 0; i < count; i++) {
-		if (sbi_platform_pmp_region_info(plat, hartid, i, &prot, &addr,
-						 &log2size))
-			continue;
-		pmp_set(i + 1, prot, addr, log2size);
+		pmp_addr =  reg->base >> PMP_SHIFT;
+		if (pmp_gran_log2 <= reg->order && pmp_addr < pmp_addr_max)
+			pmp_set(pmp_idx++, pmp_flags, reg->base, reg->order);
+		else {
+			sbi_printf("Can not configure pmp for domain %s", dom->name);
+			sbi_printf("because memory region address %lx or size %lx is not in range\n",
+				    reg->base, reg->order);
+		}
 	}
 
 	return 0;
 }
 
-int sbi_hart_init(struct sbi_scratch *scratch, u32 hartid, bool cold_boot)
+/**
+ * Check whether a particular hart feature is available
+ *
+ * @param scratch pointer to the HART scratch space
+ * @param feature the feature to check
+ * @returns true (feature available) or false (feature not available)
+ */
+bool sbi_hart_has_feature(struct sbi_scratch *scratch, unsigned long feature)
+{
+	struct hart_features *hfeatures =
+			sbi_scratch_offset_ptr(scratch, hart_features_offset);
+
+	if (hfeatures->features & feature)
+		return true;
+	else
+		return false;
+}
+
+static unsigned long hart_get_features(struct sbi_scratch *scratch)
+{
+	struct hart_features *hfeatures =
+			sbi_scratch_offset_ptr(scratch, hart_features_offset);
+
+	return hfeatures->features;
+}
+
+static inline char *sbi_hart_feature_id2string(unsigned long feature)
+{
+	char *fstr = NULL;
+
+	if (!feature)
+		return NULL;
+
+	switch (feature) {
+	case SBI_HART_HAS_SCOUNTEREN:
+		fstr = "scounteren";
+		break;
+	case SBI_HART_HAS_MCOUNTEREN:
+		fstr = "mcounteren";
+		break;
+	case SBI_HART_HAS_TIME:
+		fstr = "time";
+		break;
+	default:
+		break;
+	}
+
+	return fstr;
+}
+
+/**
+ * Get the hart features in string format
+ *
+ * @param scratch pointer to the HART scratch space
+ * @param features_str pointer to a char array where the features string will be
+ *		       updated
+ * @param nfstr length of the features_str. The feature string will be truncated
+ *		if nfstr is not long enough.
+ */
+void sbi_hart_get_features_str(struct sbi_scratch *scratch,
+			       char *features_str, int nfstr)
+{
+	unsigned long features, feat = 1UL;
+	char *temp;
+	int offset = 0;
+
+	if (!features_str || nfstr <= 0)
+		return;
+	sbi_memset(features_str, 0, nfstr);
+
+	features = hart_get_features(scratch);
+	if (!features)
+		goto done;
+
+	do {
+		if (features & feat) {
+			temp = sbi_hart_feature_id2string(feat);
+			if (temp) {
+				sbi_snprintf(features_str + offset, nfstr,
+					     "%s,", temp);
+				offset = offset + sbi_strlen(temp) + 1;
+			}
+		}
+		feat = feat << 1;
+	} while (feat <= SBI_HART_HAS_LAST_FEATURE);
+
+done:
+	if (offset)
+		features_str[offset - 1] = '\0';
+	else
+		sbi_strncpy(features_str, "none", nfstr);
+}
+
+static unsigned long hart_pmp_get_allowed_addr(void)
+{
+	unsigned long val = 0;
+	struct sbi_trap_info trap = {0};
+
+	csr_write_allowed(CSR_PMPADDR0, (ulong)&trap, PMP_ADDR_MASK);			\
+	if (!trap.cause) {
+		val = csr_read_allowed(CSR_PMPADDR0, (ulong)&trap);
+		if (trap.cause)
+			val = 0;
+	}
+
+	return val;
+}
+
+static void hart_detect_features(struct sbi_scratch *scratch)
+{
+	struct sbi_trap_info trap = {0};
+	struct hart_features *hfeatures;
+	unsigned long val;
+
+	/* Reset hart features */
+	hfeatures = sbi_scratch_offset_ptr(scratch, hart_features_offset);
+	hfeatures->features = 0;
+	hfeatures->pmp_count = 0;
+	hfeatures->mhpm_count = 0;
+
+#define __check_csr(__csr, __rdonly, __wrval, __field, __skip)	\
+	val = csr_read_allowed(__csr, (ulong)&trap);			\
+	if (!trap.cause) {						\
+		if (__rdonly) {						\
+			(hfeatures->__field)++;				\
+		} else {						\
+			csr_write_allowed(__csr, (ulong)&trap, __wrval);\
+			if (!trap.cause) {				\
+				if (csr_swap(__csr, val) == __wrval)	\
+					(hfeatures->__field)++;		\
+				else					\
+					goto __skip;			\
+			} else {					\
+				goto __skip;				\
+			}						\
+		}							\
+	} else {							\
+		goto __skip;						\
+	}
+#define __check_csr_2(__csr, __rdonly, __wrval, __field, __skip)	\
+	__check_csr(__csr + 0, __rdonly, __wrval, __field, __skip)	\
+	__check_csr(__csr + 1, __rdonly, __wrval, __field, __skip)
+#define __check_csr_4(__csr, __rdonly, __wrval, __field, __skip)	\
+	__check_csr_2(__csr + 0, __rdonly, __wrval, __field, __skip)	\
+	__check_csr_2(__csr + 2, __rdonly, __wrval, __field, __skip)
+#define __check_csr_8(__csr, __rdonly, __wrval, __field, __skip)	\
+	__check_csr_4(__csr + 0, __rdonly, __wrval, __field, __skip)	\
+	__check_csr_4(__csr + 4, __rdonly, __wrval, __field, __skip)
+#define __check_csr_16(__csr, __rdonly, __wrval, __field, __skip)	\
+	__check_csr_8(__csr + 0, __rdonly, __wrval, __field, __skip)	\
+	__check_csr_8(__csr + 8, __rdonly, __wrval, __field, __skip)
+#define __check_csr_32(__csr, __rdonly, __wrval, __field, __skip)	\
+	__check_csr_16(__csr + 0, __rdonly, __wrval, __field, __skip)	\
+	__check_csr_16(__csr + 16, __rdonly, __wrval, __field, __skip)
+#define __check_csr_64(__csr, __rdonly, __wrval, __field, __skip)	\
+	__check_csr_32(__csr + 0, __rdonly, __wrval, __field, __skip)	\
+	__check_csr_32(__csr + 32, __rdonly, __wrval, __field, __skip)
+
+	/**
+	 * Detect the allowed address bits & granularity. At least PMPADDR0
+	 * should be implemented.
+	 */
+	val = hart_pmp_get_allowed_addr();
+	if (val) {
+		hfeatures->pmp_gran =  1 << (__ffs(val) + 2);
+		hfeatures->pmp_addr_bits = __fls(val) + 1;
+		/* Detect number of PMP regions. At least PMPADDR0 should be implemented*/
+		__check_csr_64(CSR_PMPADDR0, 0, val, pmp_count, __pmp_skip);
+	}
+__pmp_skip:
+
+	/* Detect number of MHPM counters */
+	__check_csr(CSR_MHPMCOUNTER3, 0, 1UL, mhpm_count, __mhpm_skip);
+	__check_csr_4(CSR_MHPMCOUNTER4, 0, 1UL, mhpm_count, __mhpm_skip);
+	__check_csr_8(CSR_MHPMCOUNTER8, 0, 1UL, mhpm_count, __mhpm_skip);
+	__check_csr_16(CSR_MHPMCOUNTER16, 0, 1UL, mhpm_count, __mhpm_skip);
+__mhpm_skip:
+
+#undef __check_csr_64
+#undef __check_csr_32
+#undef __check_csr_16
+#undef __check_csr_8
+#undef __check_csr_4
+#undef __check_csr_2
+#undef __check_csr
+
+	/* Detect if hart supports SCOUNTEREN feature */
+	val = csr_read_allowed(CSR_SCOUNTEREN, (unsigned long)&trap);
+	if (!trap.cause) {
+		csr_write_allowed(CSR_SCOUNTEREN, (unsigned long)&trap, val);
+		if (!trap.cause)
+			hfeatures->features |= SBI_HART_HAS_SCOUNTEREN;
+	}
+
+	/* Detect if hart supports MCOUNTEREN feature */
+	val = csr_read_allowed(CSR_MCOUNTEREN, (unsigned long)&trap);
+	if (!trap.cause) {
+		csr_write_allowed(CSR_MCOUNTEREN, (unsigned long)&trap, val);
+		if (!trap.cause)
+			hfeatures->features |= SBI_HART_HAS_MCOUNTEREN;
+	}
+
+	/* Detect if hart supports time CSR */
+	csr_read_allowed(CSR_TIME, (unsigned long)&trap);
+	if (!trap.cause)
+		hfeatures->features |= SBI_HART_HAS_TIME;
+}
+
+int sbi_hart_reinit(struct sbi_scratch *scratch)
 {
 	int rc;
 
+	mstatus_init(scratch);
+
+	rc = fp_init(scratch);
+	if (rc)
+		return rc;
+
+	rc = delegate_traps(scratch);
+	if (rc)
+		return rc;
+
+	return 0;
+}
+
+int sbi_hart_init(struct sbi_scratch *scratch, bool cold_boot)
+{
 	if (cold_boot) {
 		if (misa_extension('H'))
-			sbi_hart_unpriv_trap = &__sbi_unpriv_trap_hext;
+			sbi_hart_expected_trap = &__sbi_expected_trap_hext;
+
+		hart_features_offset = sbi_scratch_alloc_offset(
+						sizeof(struct hart_features),
+						"HART_FEATURES");
+		if (!hart_features_offset)
+			return SBI_ENOMEM;
 	}
 
-	mstatus_init(scratch, hartid);
+	hart_detect_features(scratch);
 
-	rc = fp_init(hartid);
-	if (rc)
-		return rc;
-
-	rc = delegate_traps(scratch, hartid);
-	if (rc)
-		return rc;
-
-	return pmp_init(scratch, hartid);
+	return sbi_hart_reinit(scratch);
 }
 
 void __attribute__((noreturn)) sbi_hart_hang(void)
@@ -299,9 +524,11 @@ sbi_hart_switch_mode(unsigned long arg0, unsigned long arg1,
 		csr_write(CSR_SIE, 0);
 		csr_write(CSR_SATP, 0);
 	} else if (next_mode == PRV_U) {
-		csr_write(CSR_UTVEC, next_addr);
-		csr_write(CSR_USCRATCH, 0);
-		csr_write(CSR_UIE, 0);
+		if (misa_extension('N')) {
+			csr_write(CSR_UTVEC, next_addr);
+			csr_write(CSR_USCRATCH, 0);
+			csr_write(CSR_UIE, 0);
+		}
 	}
 
 	register unsigned long a0 asm("a0") = arg0;

lib/sbi/sbi_hfence.S

@@ -9,67 +9,127 @@
  */
 
 	/*
-	 * Instruction encoding of hfence.gvma is:
+	 * HFENCE.GVMA rs1, rs2
+	 * HFENCE.GVMA zero, rs2
+	 * HFENCE.GVMA rs1
+	 * HFENCE.GVMA
+	 *
+	 * rs1!=zero and rs2!=zero ==> HFENCE.GVMA rs1, rs2
+	 * rs1==zero and rs2!=zero ==> HFENCE.GVMA zero, rs2
+	 * rs1!=zero and rs2==zero ==> HFENCE.GVMA rs1
+	 * rs1==zero and rs2==zero ==> HFENCE.GVMA
+	 *
+	 * Instruction encoding of HFENCE.GVMA is:
 	 * 0110001 rs2(5) rs1(5) 000 00000 1110011
 	 */
 
 	.align 3
 	.global __sbi_hfence_gvma_vmid_gpa
 __sbi_hfence_gvma_vmid_gpa:
-	/* hfence.gvma a1, a0 */
-	.word 0x62a60073
+	/*
+	 * rs1 = a0 (GPA)
+	 * rs2 = a1 (VMID)
+	 * HFENCE.GVMA a0, a1
+	 * 0110001 01011 01010 000 00000 1110011
+	 */
+	.word 0x62b50073
 	ret
 
 	.align 3
 	.global __sbi_hfence_gvma_vmid
 __sbi_hfence_gvma_vmid:
-	/* hfence.gvma zero, a0 */
+	/*
+	 * rs1 = zero
+	 * rs2 = a0 (VMID)
+	 * HFENCE.GVMA zero, a0
+	 * 0110001 01010 00000 000 00000 1110011
+	 */
 	.word 0x62a00073
 	ret
 
 	.align 3
 	.global __sbi_hfence_gvma_gpa
 __sbi_hfence_gvma_gpa:
-	/* hfence.gvma a0 */
+	/*
+	 * rs1 = a0 (GPA)
+	 * rs2 = zero
+	 * HFENCE.GVMA a0
+	 * 0110001 00000 01010 000 00000 1110011
+	 */
 	.word 0x62050073
 	ret
 
 	.align 3
 	.global __sbi_hfence_gvma_all
 __sbi_hfence_gvma_all:
-	/* hfence.gvma */
+	/*
+	 * rs1 = zero
+	 * rs2 = zero
+	 * HFENCE.GVMA
+	 * 0110001 00000 00000 000 00000 1110011
+	 */
 	.word 0x62000073
 	ret
 
 	/*
-	 * Instruction encoding of hfence.bvma is:
+	 * HFENCE.VVMA rs1, rs2
+	 * HFENCE.VVMA zero, rs2
+	 * HFENCE.VVMA rs1
+	 * HFENCE.VVMA
+	 *
+	 * rs1!=zero and rs2!=zero ==> HFENCE.VVMA rs1, rs2
+	 * rs1==zero and rs2!=zero ==> HFENCE.VVMA zero, rs2
+	 * rs1!=zero and rs2==zero ==> HFENCE.VVMA rs1
+	 * rs1==zero and rs2==zero ==> HFENCE.vVMA
+	 *
+	 * Instruction encoding of HFENCE.VVMA is:
 	 * 0010001 rs2(5) rs1(5) 000 00000 1110011
 	 */
 
 	.align 3
 	.global __sbi_hfence_vvma_asid_va
 __sbi_hfence_vvma_asid_va:
-	/* hfence.bvma a1, a0 */
-	.word 0x22a60073
+	/*
+	 * rs1 = a0 (VA)
+	 * rs2 = a1 (ASID)
+	 * HFENCE.VVMA a0, a1
+	 * 0010001 01011 01010 000 00000 1110011
+	 */
+	.word 0x22b50073
 	ret
 
 	.align 3
 	.global __sbi_hfence_vvma_asid
 __sbi_hfence_vvma_asid:
-	/* hfence.bvma zero, a0 */
+	/*
+	 * rs1 = zero
+	 * rs2 = a0 (ASID)
+	 * HFENCE.VVMA zero, a0
+	 * 0010001 01010 00000 000 00000 1110011
+	 */
 	.word 0x22a00073
 	ret
 
 	.align 3
 	.global __sbi_hfence_vvma_va
 __sbi_hfence_vvma_va:
-	/* hfence.bvma a0 */
+	/*
+	 * rs1 = a0 (VA)
+	 * rs2 = zero
+	 * HFENCE.VVMA zero, a0
+	 * 0010001 00000 01010 000 00000 1110011
+	 */
 	.word 0x22050073
 	ret
 
 	.align 3
 	.global __sbi_hfence_vvma_all
 __sbi_hfence_vvma_all:
-	/* hfence.bvma */
+	/*
+	 * rs1 = zero
+	 * rs2 = zero
+	 * HFENCE.VVMA
+	 * 0010001 00000 00000 000 00000 1110011
+	 */
 	.word 0x22000073
 	ret

lib/sbi/sbi_hsm.c

@@ -13,6 +13,7 @@
 #include <sbi/riscv_atomic.h>
 #include <sbi/sbi_bitops.h>
 #include <sbi/sbi_console.h>
+#include <sbi/sbi_domain.h>
 #include <sbi/sbi_error.h>
 #include <sbi/sbi_ecall_interface.h>
 #include <sbi/sbi_hart.h>
@@ -20,85 +21,90 @@
 #include <sbi/sbi_hsm.h>
 #include <sbi/sbi_init.h>
 #include <sbi/sbi_ipi.h>
-#include <sbi/sbi_platform.h>
+#include <sbi/sbi_scratch.h>
 #include <sbi/sbi_system.h>
 #include <sbi/sbi_timer.h>
 #include <sbi/sbi_console.h>
 
+static const struct sbi_hsm_device *hsm_dev = NULL;
 static unsigned long hart_data_offset;
 
 /** Per hart specific data to manage state transition **/
 struct sbi_hsm_data {
 	atomic_t state;
+	unsigned long suspend_type;
+	unsigned long saved_mie;
+	unsigned long saved_mip;
 };
+#define __sbi_hsm_hart_change_state(hdata, oldstate, newstate)    \
+({				\
+	long state = atomic_cmpxchg(&(hdata)->state, oldstate, newstate); \
+	if (state != (oldstate))		\
+		sbi_printf("%s: ERR: The hart is in invalid state [%lu]\n",   \
+				__func__, state);	\
+	state == (oldstate);		\
+})
 
-int sbi_hsm_hart_state_to_status(int state)
+int sbi_hsm_hart_change_state(struct sbi_scratch *scratch, long oldstate,
+				long newstate)
 {
-	int ret;
+	struct sbi_hsm_data *hdata = sbi_scratch_offset_ptr(scratch,
+					hart_data_offset);
 
-	switch (state) {
-	case SBI_HART_STOPPED:
-		ret = SBI_HSM_HART_STATUS_STOPPED;
-		break;
-	case SBI_HART_STOPPING:
-		ret = SBI_HSM_HART_STATUS_STOP_PENDING;
-		break;
-	case SBI_HART_STARTING:
-		ret = SBI_HSM_HART_STATUS_START_PENDING;
-		break;
-	case SBI_HART_STARTED:
-		ret = SBI_HSM_HART_STATUS_STARTED;
-		break;
-	default:
-		ret = SBI_EINVAL;
-	}
-
-	return ret;
+	return __sbi_hsm_hart_change_state(hdata, oldstate, newstate);
 }
 
-int sbi_hsm_hart_get_state(u32 hartid)
+int __sbi_hsm_hart_get_state(u32 hartid)
 {
 	struct sbi_hsm_data *hdata;
 	struct sbi_scratch *scratch;
 
 	scratch = sbi_hartid_to_scratch(hartid);
 	if (!scratch)
-		return SBI_HART_UNKNOWN;
+		return SBI_EINVAL;
 
 	hdata = sbi_scratch_offset_ptr(scratch, hart_data_offset);
-
 	return atomic_read(&hdata->state);
 }
 
-bool sbi_hsm_hart_started(u32 hartid)
+int sbi_hsm_hart_get_state(const struct sbi_domain *dom, u32 hartid)
 {
-	if (sbi_hsm_hart_get_state(hartid) == SBI_HART_STARTED)
-		return TRUE;
-	else
-		return FALSE;
+	if (!sbi_domain_is_assigned_hart(dom, hartid))
+		return SBI_EINVAL;
+
+	return __sbi_hsm_hart_get_state(hartid);
 }
 
 /**
  * Get ulong HART mask for given HART base ID
+ * @param dom the domain to be used for output HART mask
  * @param hbase the HART base ID
  * @param out_hmask the output ulong HART mask
  * @return 0 on success and SBI_Exxx (< 0) on failure
  * Note: the output HART mask will be set to zero on failure as well.
  */
-int sbi_hsm_hart_started_mask(ulong hbase, ulong *out_hmask)
+int sbi_hsm_hart_interruptible_mask(const struct sbi_domain *dom,
+				    ulong hbase, ulong *out_hmask)
 {
-	ulong i;
-	ulong hcount = sbi_scratch_last_hartid() + 1;
+	int hstate;
+	ulong i, hmask, dmask;
+	ulong hend = sbi_scratch_last_hartid() + 1;
 
 	*out_hmask = 0;
-	if (hcount <= hbase)
+	if (hend <= hbase)
 		return SBI_EINVAL;
-	if (BITS_PER_LONG < (hcount - hbase))
-		hcount = BITS_PER_LONG;
+	if (BITS_PER_LONG < (hend - hbase))
+		hend = hbase + BITS_PER_LONG;
 
-	for (i = hbase; i < hcount; i++) {
-		if (sbi_hsm_hart_get_state(i) == SBI_HART_STARTED)
-			*out_hmask |= 1UL << (i - hbase);
+	dmask = sbi_domain_get_assigned_hartmask(dom, hbase);
+	for (i = hbase; i < hend; i++) {
+		hmask = 1UL << (i - hbase);
+		if (dmask & hmask) {
+			hstate = __sbi_hsm_hart_get_state(i);
+			if (hstate == SBI_HSM_STATE_STARTED ||
+			    hstate == SBI_HSM_STATE_SUSPENDED)
+				*out_hmask |= hmask;
+		}
 	}
 
 	return 0;
@@ -110,16 +116,15 @@ void sbi_hsm_prepare_next_jump(struct sbi_scratch *scratch, u32 hartid)
 	struct sbi_hsm_data *hdata = sbi_scratch_offset_ptr(scratch,
 							    hart_data_offset);
 
-	oldstate = atomic_cmpxchg(&hdata->state, SBI_HART_STARTING,
-				  SBI_HART_STARTED);
-	if (oldstate != SBI_HART_STARTING)
+	oldstate = atomic_cmpxchg(&hdata->state, SBI_HSM_STATE_START_PENDING,
+				  SBI_HSM_STATE_STARTED);
+	if (oldstate != SBI_HSM_STATE_START_PENDING)
 		sbi_hart_hang();
 }
 
 static void sbi_hsm_hart_wait(struct sbi_scratch *scratch, u32 hartid)
 {
 	unsigned long saved_mie;
-	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
 	struct sbi_hsm_data *hdata = sbi_scratch_offset_ptr(scratch,
 							    hart_data_offset);
 	/* Save MIE CSR */
@@ -129,15 +134,65 @@ static void sbi_hsm_hart_wait(struct sbi_scratch *scratch, u32 hartid)
 	csr_set(CSR_MIE, MIP_MSIP);
 
 	/* Wait for hart_add call*/
-	while (atomic_read(&hdata->state) != SBI_HART_STARTING) {
+	while (atomic_read(&hdata->state) != SBI_HSM_STATE_START_PENDING) {
 		wfi();
 	};
 
 	/* Restore MIE CSR */
 	csr_write(CSR_MIE, saved_mie);
 
-	/* Clear current HART IPI */
-	sbi_platform_ipi_clear(plat, hartid);
+	/*
+	 * No need to clear IPI here because the sbi_ipi_init() will
+	 * clear it for current HART via sbi_platform_ipi_init().
+	 */
+}
+
+const struct sbi_hsm_device *sbi_hsm_get_device(void)
+{
+	return hsm_dev;
+}
+
+void sbi_hsm_set_device(const struct sbi_hsm_device *dev)
+{
+	if (!dev || hsm_dev)
+		return;
+
+	hsm_dev = dev;
+}
+
+static bool hsm_device_has_hart_hotplug(void)
+{
+	if (hsm_dev && hsm_dev->hart_start && hsm_dev->hart_stop)
+		return true;
+	return false;
+}
+
+static bool hsm_device_has_hart_secondary_boot(void)
+{
+	if (hsm_dev && hsm_dev->hart_start && !hsm_dev->hart_stop)
+		return true;
+	return false;
+}
+
+static int hsm_device_hart_start(u32 hartid, ulong saddr)
+{
+	if (hsm_dev && hsm_dev->hart_start)
+		return hsm_dev->hart_start(hartid, saddr);
+	return SBI_ENOTSUPP;
+}
+
+static int hsm_device_hart_stop(void)
+{
+	if (hsm_dev && hsm_dev->hart_stop)
+		return hsm_dev->hart_stop();
+	return SBI_ENOTSUPP;
+}
+
+static int hsm_device_hart_suspend(u32 suspend_type, ulong raddr)
+{
+	if (hsm_dev && hsm_dev->hart_suspend)
+		return hsm_dev->hart_suspend(suspend_type, raddr);
+	return SBI_ENOTSUPP;
 }
 
 int sbi_hsm_init(struct sbi_scratch *scratch, u32 hartid, bool cold_boot)
@@ -161,7 +216,9 @@ int sbi_hsm_init(struct sbi_scratch *scratch, u32 hartid, bool cold_boot)
 			hdata = sbi_scratch_offset_ptr(rscratch,
 						       hart_data_offset);
 			ATOMIC_INIT(&hdata->state,
-			(i == hartid) ? SBI_HART_STARTING : SBI_HART_STOPPED);
+				    (i == hartid) ?
+				    SBI_HSM_STATE_START_PENDING :
+				    SBI_HSM_STATE_STOPPED);
 		}
 	} else {
 		sbi_hsm_hart_wait(scratch, hartid);
@@ -173,18 +230,17 @@ int sbi_hsm_init(struct sbi_scratch *scratch, u32 hartid, bool cold_boot)
 void __noreturn sbi_hsm_exit(struct sbi_scratch *scratch)
 {
 	u32 hstate;
-	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
 	struct sbi_hsm_data *hdata = sbi_scratch_offset_ptr(scratch,
 							    hart_data_offset);
 	void (*jump_warmboot)(void) = (void (*)(void))scratch->warmboot_addr;
 
-	hstate = atomic_cmpxchg(&hdata->state, SBI_HART_STOPPING,
-				SBI_HART_STOPPED);
-	if (hstate != SBI_HART_STOPPING)
+	hstate = atomic_cmpxchg(&hdata->state, SBI_HSM_STATE_STOP_PENDING,
+				SBI_HSM_STATE_STOPPED);
+	if (hstate != SBI_HSM_STATE_STOP_PENDING)
 		goto fail_exit;
 
-	if (sbi_platform_has_hart_hotplug(plat)) {
-		sbi_platform_hart_stop(plat);
+	if (hsm_device_has_hart_hotplug()) {
+		hsm_device_hart_stop();
 		/* It should never reach here */
 		goto fail_exit;
 	}
@@ -202,47 +258,50 @@ fail_exit:
 	sbi_hart_hang();
 }
 
-int sbi_hsm_hart_start(struct sbi_scratch *scratch, u32 hartid,
-		       ulong saddr, ulong priv)
+int sbi_hsm_hart_start(struct sbi_scratch *scratch,
+		       const struct sbi_domain *dom,
+		       u32 hartid, ulong saddr, ulong smode, ulong priv)
 {
-	int rc;
 	unsigned long init_count;
 	unsigned int hstate;
 	struct sbi_scratch *rscratch;
 	struct sbi_hsm_data *hdata;
-	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
+
+	/* For now, we only allow start mode to be S-mode or U-mode. */
+	if (smode != PRV_S && smode != PRV_U)
+		return SBI_EINVAL;
+	if (dom && !sbi_domain_is_assigned_hart(dom, hartid))
+		return SBI_EINVAL;
+	if (dom && !sbi_domain_check_addr(dom, saddr, smode,
+					  SBI_DOMAIN_EXECUTE))
+		return SBI_EINVALID_ADDR;
 
 	rscratch = sbi_hartid_to_scratch(hartid);
 	if (!rscratch)
 		return SBI_EINVAL;
 	hdata = sbi_scratch_offset_ptr(rscratch, hart_data_offset);
-	hstate = atomic_cmpxchg(&hdata->state, SBI_HART_STOPPED,
-				SBI_HART_STARTING);
-	if (hstate == SBI_HART_STARTED)
-		return SBI_EALREADY_STARTED;
+	hstate = atomic_cmpxchg(&hdata->state, SBI_HSM_STATE_STOPPED,
+				SBI_HSM_STATE_START_PENDING);
+	if (hstate == SBI_HSM_STATE_STARTED)
+		return SBI_EALREADY;
 
 	/**
 	 * if a hart is already transition to start or stop, another start call
 	 * is considered as invalid request.
 	 */
-	if (hstate != SBI_HART_STOPPED)
+	if (hstate != SBI_HSM_STATE_STOPPED)
 		return SBI_EINVAL;
 
-	rc = sbi_hart_pmp_check_addr(scratch, saddr, PMP_X);
-	if (rc)
-		return rc;
-	//TODO: We also need to check saddr for valid physical address as well.
-
 	init_count = sbi_init_count(hartid);
 	rscratch->next_arg1 = priv;
 	rscratch->next_addr = saddr;
+	rscratch->next_mode = smode;
 
-	if (sbi_platform_has_hart_hotplug(plat) ||
-	   (sbi_platform_has_hart_secondary_boot(plat) && !init_count)) {
-		return sbi_platform_hart_start(plat, hartid,
-					       scratch->warmboot_addr);
+	if (hsm_device_has_hart_hotplug() ||
+	   (hsm_device_has_hart_secondary_boot() && !init_count)) {
+		return hsm_device_hart_start(hartid, scratch->warmboot_addr);
 	} else {
-		sbi_platform_ipi_send(plat, hartid);
+		sbi_ipi_raw_send(hartid);
 	}
 
 	return 0;
@@ -251,19 +310,19 @@ int sbi_hsm_hart_start(struct sbi_scratch *scratch, u32 hartid,
 int sbi_hsm_hart_stop(struct sbi_scratch *scratch, bool exitnow)
 {
 	int oldstate;
-	u32 hartid = current_hartid();
+	const struct sbi_domain *dom = sbi_domain_thishart_ptr();
 	struct sbi_hsm_data *hdata = sbi_scratch_offset_ptr(scratch,
 							    hart_data_offset);
 
-	if (!sbi_hsm_hart_started(hartid))
-		return SBI_EINVAL;
+	if (!dom)
+		return SBI_EFAIL;
 
-	oldstate = atomic_cmpxchg(&hdata->state, SBI_HART_STARTED,
-				  SBI_HART_STOPPING);
-	if (oldstate != SBI_HART_STARTED) {
+	oldstate = atomic_cmpxchg(&hdata->state, SBI_HSM_STATE_STARTED,
+				  SBI_HSM_STATE_STOP_PENDING);
+	if (oldstate != SBI_HSM_STATE_STARTED) {
 		sbi_printf("%s: ERR: The hart is in invalid state [%u]\n",
 			   __func__, oldstate);
-		return SBI_DENIED;
+		return SBI_EFAIL;
 	}
 
 	if (exitnow)
@@ -271,3 +330,181 @@ int sbi_hsm_hart_stop(struct sbi_scratch *scratch, bool exitnow)
 
 	return 0;
 }
+
+static int __sbi_hsm_suspend_ret_default(struct sbi_scratch *scratch)
+{
+	/* Wait for interrupt */
+	wfi();
+
+	return 0;
+}
+
+void __sbi_hsm_suspend_non_ret_save(struct sbi_scratch *scratch)
+{
+	struct sbi_hsm_data *hdata = sbi_scratch_offset_ptr(scratch,
+							    hart_data_offset);
+
+	/*
+	 * We will be resuming in warm-boot path so the MIE and MIP CSRs
+	 * will be back to initial state. It is possible that HART has
+	 * configured timer event before going to suspend state so we
+	 * should save MIE and MIP CSRs and restore it after resuming.
+	 *
+	 * Further, the M-mode bits in MIP CSR are read-only and set by
+	 * external devices (such as interrupt controller) whereas all
+	 * VS-mode bits in MIP are read-only alias of bits in HVIP CSR.
+	 *
+	 * This means we should only save/restore S-mode bits of MIP CSR
+	 * such as MIP.SSIP and MIP.STIP.
+	 */
+
+	hdata->saved_mie = csr_read(CSR_MIE);
+	hdata->saved_mip = csr_read(CSR_MIP) & (MIP_SSIP | MIP_STIP);
+}
+
+static void __sbi_hsm_suspend_non_ret_restore(struct sbi_scratch *scratch)
+{
+	struct sbi_hsm_data *hdata = sbi_scratch_offset_ptr(scratch,
+							    hart_data_offset);
+
+	csr_write(CSR_MIE, hdata->saved_mie);
+	csr_write(CSR_MIP, (hdata->saved_mip & (MIP_SSIP | MIP_STIP)));
+}
+
+static int __sbi_hsm_suspend_non_ret_default(struct sbi_scratch *scratch,
+					     ulong raddr)
+{
+	void (*jump_warmboot)(void) = (void (*)(void))scratch->warmboot_addr;
+
+	/*
+	 * Save some of the M-mode CSRs which should be restored after
+	 * resuming from suspend state
+	 */
+	__sbi_hsm_suspend_non_ret_save(scratch);
+
+	/* Wait for interrupt */
+	wfi();
+
+	/*
+	 * Directly jump to warm reboot to simulate resume from a
+	 * non-retentive suspend.
+	 */
+	jump_warmboot();
+
+	return 0;
+}
+
+void sbi_hsm_hart_resume_start(struct sbi_scratch *scratch)
+{
+	int oldstate;
+	struct sbi_hsm_data *hdata = sbi_scratch_offset_ptr(scratch,
+							    hart_data_offset);
+
+	/* If current HART was SUSPENDED then set RESUME_PENDING state */
+	oldstate = atomic_cmpxchg(&hdata->state, SBI_HSM_STATE_SUSPENDED,
+			SBI_HSM_STATE_RESUME_PENDING);
+	if (oldstate != SBI_HSM_STATE_SUSPENDED) {
+		sbi_printf("%s: ERR: The hart is in invalid state [%u]\n",
+			   __func__, oldstate);
+		sbi_hart_hang();
+	}
+}
+
+void sbi_hsm_hart_resume_finish(struct sbi_scratch *scratch)
+{
+	u32 oldstate;
+	struct sbi_hsm_data *hdata = sbi_scratch_offset_ptr(scratch,
+							    hart_data_offset);
+
+	/* If current HART was RESUME_PENDING then set STARTED state */
+	oldstate = atomic_cmpxchg(&hdata->state, SBI_HSM_STATE_RESUME_PENDING,
+				  SBI_HSM_STATE_STARTED);
+	if (oldstate != SBI_HSM_STATE_RESUME_PENDING) {
+		sbi_printf("%s: ERR: The hart is in invalid state [%u]\n",
+			   __func__, oldstate);
+		sbi_hart_hang();
+	}
+
+	/*
+	 * Restore some of the M-mode CSRs which we are re-configured by
+	 * the warm-boot sequence.
+	 */
+	__sbi_hsm_suspend_non_ret_restore(scratch);
+}
+
+int sbi_hsm_hart_suspend(struct sbi_scratch *scratch, u32 suspend_type,
+			 ulong raddr, ulong rmode, ulong priv)
+{
+	int oldstate, ret;
+	const struct sbi_domain *dom = sbi_domain_thishart_ptr();
+	struct sbi_hsm_data *hdata = sbi_scratch_offset_ptr(scratch,
+							    hart_data_offset);
+
+	/* For now, we only allow suspend from S-mode or U-mode. */
+
+	/* Sanity check on domain assigned to current HART */
+	if (!dom)
+		return SBI_EINVAL;
+
+	/* Sanity check on suspend type */
+	if (SBI_HSM_SUSPEND_RET_DEFAULT < suspend_type &&
+	    suspend_type < SBI_HSM_SUSPEND_RET_PLATFORM)
+		return SBI_EINVAL;
+	if (SBI_HSM_SUSPEND_NON_RET_DEFAULT < suspend_type &&
+	    suspend_type < SBI_HSM_SUSPEND_NON_RET_PLATFORM)
+		return SBI_EINVAL;
+
+	/* Additional sanity check for non-retentive suspend */
+	if (suspend_type & SBI_HSM_SUSP_NON_RET_BIT) {
+		if (rmode != PRV_S && rmode != PRV_U)
+			return SBI_EINVAL;
+		if (dom && !sbi_domain_check_addr(dom, raddr, rmode,
+						  SBI_DOMAIN_EXECUTE))
+			return SBI_EINVALID_ADDR;
+	}
+
+	/* Save the resume address and resume mode */
+	scratch->next_arg1 = priv;
+	scratch->next_addr = raddr;
+	scratch->next_mode = rmode;
+
+	/* Directly move from STARTED to SUSPENDED state */
+	oldstate = atomic_cmpxchg(&hdata->state, SBI_HSM_STATE_STARTED,
+				  SBI_HSM_STATE_SUSPENDED);
+	if (oldstate != SBI_HSM_STATE_STARTED) {
+		sbi_printf("%s: ERR: The hart is in invalid state [%u]\n",
+			   __func__, oldstate);
+		ret = SBI_EDENIED;
+		goto fail_restore_state;
+	}
+
+	/* Save the suspend type */
+	hdata->suspend_type = suspend_type;
+
+	/* Try platform specific suspend */
+	ret = hsm_device_hart_suspend(suspend_type, scratch->warmboot_addr);
+	if (ret == SBI_ENOTSUPP) {
+		/* Try generic implementation of default suspend types */
+		if (suspend_type == SBI_HSM_SUSPEND_RET_DEFAULT) {
+			ret = __sbi_hsm_suspend_ret_default(scratch);
+		} else if (suspend_type == SBI_HSM_SUSPEND_NON_RET_DEFAULT) {
+			ret = __sbi_hsm_suspend_non_ret_default(scratch,
+						scratch->warmboot_addr);
+		}
+	}
+
+fail_restore_state:
+	/*
+	 * We might have successfully resumed from retentive suspend
+	 * or suspend failed. In both cases, we restore state of hart.
+	 */
+	oldstate = atomic_cmpxchg(&hdata->state, SBI_HSM_STATE_SUSPENDED,
+				  SBI_HSM_STATE_STARTED);
+	if (oldstate != SBI_HSM_STATE_SUSPENDED) {
+		sbi_printf("%s: ERR: The hart is in invalid state [%u]\n",
+			   __func__, oldstate);
+		sbi_hart_hang();
+	}
+
+	return ret;
+}

lib/sbi/sbi_illegal_insn.c

@@ -38,17 +38,7 @@ static int system_opcode_insn(ulong insn, struct sbi_trap_regs *regs)
 	int csr_num   = (u32)insn >> 20;
 	ulong csr_val, new_csr_val;
 
-	/*
-	 * WFI always traps as illegal instruction when executed from
-	 * VS/VU mode so we just forward it to HS-mode.
-	 */
-#if __riscv_xlen == 32
-	if ((regs->mstatusH & MSTATUSH_MPV) &&
-#else
-	if ((regs->mstatus & MSTATUS_MPV) &&
-#endif
-	    (insn & INSN_MASK_WFI) == INSN_MATCH_WFI)
-		return truly_illegal_insn(insn, regs);
+	/* TODO: Ensure that we got CSR read/write instruction */
 
 	if (sbi_emulate_csr_read(csr_num, regs, &csr_val))
 		return truly_illegal_insn(insn, regs);
@@ -128,13 +118,22 @@ int sbi_illegal_insn_handler(ulong insn, struct sbi_trap_regs *regs)
 {
 	struct sbi_trap_info uptrap;
 
+	/*
+	 * We only deal with 32-bit (or longer) illegal instructions. If we
+	 * see instruction is zero OR instruction is 16-bit then we fetch and
+	 * check the instruction encoding using unprivilege access.
+	 *
+	 * The program counter (PC) in RISC-V world is always 2-byte aligned
+	 * so handling only 32-bit (or longer) illegal instructions also help
+	 * the case where MTVAL CSR contains instruction address for illegal
+	 * instruction trap.
+	 */
+
 	if (unlikely((insn & 3) != 3)) {
-		if (insn == 0) {
-			insn = sbi_get_insn(regs->mepc, &uptrap);
-			if (uptrap.cause) {
-				uptrap.epc = regs->mepc;
-				return sbi_trap_redirect(regs, &uptrap);
-			}
+		insn = sbi_get_insn(regs->mepc, &uptrap);
+		if (uptrap.cause) {
+			uptrap.epc = regs->mepc;
+			return sbi_trap_redirect(regs, &uptrap);
 		}
 		if ((insn & 3) != 3)
 			return truly_illegal_insn(insn, regs);

lib/sbi/sbi_init.c

@@ -9,8 +9,10 @@
 
 #include <sbi/riscv_asm.h>
 #include <sbi/riscv_atomic.h>
+#include <sbi/riscv_barrier.h>
 #include <sbi/riscv_locks.h>
 #include <sbi/sbi_console.h>
+#include <sbi/sbi_domain.h>
 #include <sbi/sbi_ecall.h>
 #include <sbi/sbi_hart.h>
 #include <sbi/sbi_hartmask.h>
@@ -18,6 +20,7 @@
 #include <sbi/sbi_ipi.h>
 #include <sbi/sbi_platform.h>
 #include <sbi/sbi_system.h>
+#include <sbi/sbi_string.h>
 #include <sbi/sbi_timer.h>
 #include <sbi/sbi_tlb.h>
 #include <sbi/sbi_version.h>
@@ -32,11 +35,10 @@
 	"        | |\n"                                     \
 	"        |_|\n\n"
 
-static void sbi_boot_prints(struct sbi_scratch *scratch, u32 hartid)
+static void sbi_boot_print_banner(struct sbi_scratch *scratch)
 {
-	int xlen;
-	char str[64];
-	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
+	if (scratch->options & SBI_SCRATCH_NO_BOOT_PRINTS)
+		return;
 
 #ifdef OPENSBI_VERSION_GIT
 	sbi_printf("\nOpenSBI %s\n", OPENSBI_VERSION_GIT);
@@ -46,6 +48,76 @@ static void sbi_boot_prints(struct sbi_scratch *scratch, u32 hartid)
 #endif
 
 	sbi_printf(BANNER);
+}
+
+static void sbi_boot_print_general(struct sbi_scratch *scratch)
+{
+	char str[128];
+	const struct sbi_hsm_device *hdev;
+	const struct sbi_ipi_device *idev;
+	const struct sbi_timer_device *tdev;
+	const struct sbi_console_device *cdev;
+	const struct sbi_system_reset_device *srdev;
+	const struct sbi_system_suspend_device *susp_dev;
+	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
+
+	if (scratch->options & SBI_SCRATCH_NO_BOOT_PRINTS)
+		return;
+
+	/* Platform details */
+	sbi_printf("Platform Name             : %s\n",
+		   sbi_platform_name(plat));
+	sbi_platform_get_features_str(plat, str, sizeof(str));
+	sbi_printf("Platform Features         : %s\n", str);
+	sbi_printf("Platform HART Count       : %u\n",
+		   sbi_platform_hart_count(plat));
+	idev = sbi_ipi_get_device();
+	sbi_printf("Platform IPI Device       : %s\n",
+		   (idev) ? idev->name : "---");
+	tdev = sbi_timer_get_device();
+	sbi_printf("Platform Timer Device     : %s\n",
+		   (tdev) ? tdev->name : "---");
+	cdev = sbi_console_get_device();
+	sbi_printf("Platform Console Device   : %s\n",
+		   (cdev) ? cdev->name : "---");
+	hdev = sbi_hsm_get_device();
+	sbi_printf("Platform HSM Device       : %s\n",
+		   (hdev) ? hdev->name : "---");
+	srdev = sbi_system_reset_get_device();
+	sbi_printf("Platform SysReset Device  : %s\n",
+		   (srdev) ? srdev->name : "---");
+	susp_dev = sbi_system_suspend_get_device();
+	sbi_printf("Platform Suspend Device   : %s\n",
+		   (susp_dev) ? susp_dev->name : "---");
+
+	/* Firmware details */
+	sbi_printf("Firmware Base             : 0x%lx\n", scratch->fw_start);
+	sbi_printf("Firmware Size             : %d KB\n",
+		   (u32)(scratch->fw_size / 1024));
+
+	/* SBI details */
+	sbi_printf("Runtime SBI Version       : %d.%d\n",
+		   sbi_ecall_version_major(), sbi_ecall_version_minor());
+	sbi_printf("\n");
+}
+
+static void sbi_boot_print_domains(struct sbi_scratch *scratch)
+{
+	if (scratch->options & SBI_SCRATCH_NO_BOOT_PRINTS)
+		return;
+
+	/* Domain details */
+	sbi_domain_dump_all("      ");
+}
+
+static void sbi_boot_print_hart(struct sbi_scratch *scratch, u32 hartid)
+{
+	int xlen;
+	char str[128];
+	const struct sbi_domain *dom = sbi_domain_thishart_ptr();
+
+	if (scratch->options & SBI_SCRATCH_NO_BOOT_PRINTS)
+		return;
 
 	/* Determine MISA XLEN and MISA string */
 	xlen = misa_xlen();
@@ -53,34 +125,35 @@ static void sbi_boot_prints(struct sbi_scratch *scratch, u32 hartid)
 		sbi_printf("Error %d getting MISA XLEN\n", xlen);
 		sbi_hart_hang();
 	}
-	xlen = 16 * (1 << xlen);
-	misa_string(str, sizeof(str));
 
-	/* Platform details */
-	sbi_printf("Platform Name          : %s\n", sbi_platform_name(plat));
-	sbi_printf("Platform HART Features : RV%d%s\n", xlen, str);
-	sbi_printf("Current Hart           : %u\n", hartid);
-	/* Firmware details */
-	sbi_printf("Firmware Base          : 0x%lx\n", scratch->fw_start);
-	sbi_printf("Firmware Size          : %d KB\n",
-		   (u32)(scratch->fw_size / 1024));
-	/* Generic details */
-	sbi_printf("Runtime SBI Version    : %d.%d\n",
-		   sbi_ecall_version_major(), sbi_ecall_version_minor());
-	sbi_printf("\n");
-
-	sbi_hart_delegation_dump(scratch);
-	sbi_hart_pmp_dump(scratch);
+	/* Boot HART details */
+	sbi_printf("Boot HART ID              : %u\n", hartid);
+	sbi_printf("Boot HART Domain          : %s\n", dom->name);
+	misa_string(xlen, str, sizeof(str));
+	sbi_printf("Boot HART ISA             : %s\n", str);
+	sbi_hart_get_features_str(scratch, str, sizeof(str));
+	sbi_printf("Boot HART Features        : %s\n", str);
+	sbi_printf("Boot HART PMP Count       : %d\n",
+		   sbi_hart_pmp_count(scratch));
+	sbi_printf("Boot HART PMP Granularity : %lu\n",
+		   sbi_hart_pmp_granularity(scratch));
+	sbi_printf("Boot HART PMP Address Bits: %d\n",
+		   sbi_hart_pmp_addrbits(scratch));
+	sbi_printf("Boot HART MHPM Count      : %d\n",
+		   sbi_hart_mhpm_count(scratch));
+	sbi_printf("Boot HART MHPM Count      : %d\n",
+		   sbi_hart_mhpm_count(scratch));
+	sbi_hart_delegation_dump(scratch, "Boot HART ", "         ");
 }
 
 static spinlock_t coldboot_lock = SPIN_LOCK_INITIALIZER;
-static unsigned long coldboot_done = 0;
 static struct sbi_hartmask coldboot_wait_hmask = { 0 };
 
+static unsigned long coldboot_done;
+
 static void wait_for_coldboot(struct sbi_scratch *scratch, u32 hartid)
 {
 	unsigned long saved_mie, cmip;
-	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
 
 	/* Save MIE CSR */
 	saved_mie = csr_read(CSR_MIE);
@@ -94,16 +167,20 @@ static void wait_for_coldboot(struct sbi_scratch *scratch, u32 hartid)
 	/* Mark current HART as waiting */
 	sbi_hartmask_set_hart(hartid, &coldboot_wait_hmask);
 
+	/* Release coldboot lock */
+	spin_unlock(&coldboot_lock);
+
 	/* Wait for coldboot to finish using WFI */
-	while (!coldboot_done) {
-		spin_unlock(&coldboot_lock);
+	while (!__smp_load_acquire(&coldboot_done)) {
 		do {
 			wfi();
 			cmip = csr_read(CSR_MIP);
 		 } while (!(cmip & MIP_MSIP));
-		spin_lock(&coldboot_lock);
 	};
 
+	/* Acquire coldboot lock */
+	spin_lock(&coldboot_lock);
+
 	/* Unmark current HART as waiting */
 	sbi_hartmask_clear_hart(hartid, &coldboot_wait_hmask);
 
@@ -113,25 +190,29 @@ static void wait_for_coldboot(struct sbi_scratch *scratch, u32 hartid)
 	/* Restore MIE CSR */
 	csr_write(CSR_MIE, saved_mie);
 
-	/* Clear current HART IPI */
-	sbi_platform_ipi_clear(plat, hartid);
+	/*
+	 * The wait for coldboot is common for both warm startup and
+	 * warm resume path so clearing IPI here would result in losing
+	 * an IPI in warm resume path.
+	 *
+	 * Also, the sbi_platform_ipi_init() called from sbi_ipi_init()
+	 * will automatically clear IPI for current HART.
+	 */
 }
 
 static void wake_coldboot_harts(struct sbi_scratch *scratch, u32 hartid)
 {
-	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
+	/* Mark coldboot done */
+	__smp_store_release(&coldboot_done, 1);
 
 	/* Acquire coldboot lock */
 	spin_lock(&coldboot_lock);
 
-	/* Mark coldboot done */
-	coldboot_done = 1;
-
 	/* Send an IPI to all HARTs waiting for coldboot */
 	for (int i = 0; i <= sbi_scratch_last_hartid(); i++) {
 		if ((i != hartid) &&
 		    sbi_hartmask_test_hart(i, &coldboot_wait_hmask))
-			sbi_platform_ipi_send(plat, i);
+			sbi_ipi_raw_send(i);
 	}
 
 	/* Release coldboot lock */
@@ -144,13 +225,20 @@ static void __noreturn init_coldboot(struct sbi_scratch *scratch, u32 hartid)
 {
 	int rc;
 	unsigned long *init_count;
+#ifndef CONFIG_OPENSBI_FASTBOOT
 	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
+#endif
 
 	/* Note: This has to be first thing in coldboot init sequence */
 	rc = sbi_scratch_init(scratch);
 	if (rc)
 		sbi_hart_hang();
 
+	/* Note: This has to be second thing in coldboot init sequence */
+	rc = sbi_domain_init(scratch, hartid);
+	if (rc)
+		sbi_hart_hang();
+
 	init_count_offset = sbi_scratch_alloc_offset(__SIZEOF_POINTER__,
 						     "INIT_COUNT");
 	if (!init_count_offset)
@@ -160,44 +248,95 @@ static void __noreturn init_coldboot(struct sbi_scratch *scratch, u32 hartid)
 	if (rc)
 		sbi_hart_hang();
 
+#ifndef CONFIG_OPENSBI_FASTBOOT
 	rc = sbi_platform_early_init(plat, TRUE);
 	if (rc)
 		sbi_hart_hang();
+#endif
 
-	rc = sbi_hart_init(scratch, hartid, TRUE);
+	rc = sbi_hart_init(scratch, TRUE);
 	if (rc)
 		sbi_hart_hang();
 
+#ifndef CONFIG_OPENSBI_FASTBOOT
 	rc = sbi_console_init(scratch);
 	if (rc)
 		sbi_hart_hang();
+#endif
 
+	sbi_boot_print_banner(scratch);
+
+#ifndef CONFIG_OPENSBI_FASTBOOT
 	rc = sbi_platform_irqchip_init(plat, TRUE);
-	if (rc)
+	if (rc) {
+		sbi_printf("%s: platform irqchip init failed (error %d)\n",
+			   __func__, rc);
 		sbi_hart_hang();
+	}
 
 	rc = sbi_ipi_init(scratch, TRUE);
-	if (rc)
+	if (rc) {
+		sbi_printf("%s: ipi init failed (error %d)\n", __func__, rc);
 		sbi_hart_hang();
+	}
+#endif
 
 	rc = sbi_tlb_init(scratch, TRUE);
-	if (rc)
+	if (rc) {
+		sbi_printf("%s: tlb init failed (error %d)\n", __func__, rc);
 		sbi_hart_hang();
+	}
 
 	rc = sbi_timer_init(scratch, TRUE);
-	if (rc)
+	if (rc) {
+		sbi_printf("%s: timer init failed (error %d)\n", __func__, rc);
 		sbi_hart_hang();
+	}
 
 	rc = sbi_ecall_init();
-	if (rc)
+	if (rc) {
+		sbi_printf("%s: ecall init failed (error %d)\n", __func__, rc);
 		sbi_hart_hang();
+	}
 
+	sbi_boot_print_general(scratch);
+
+	/*
+	 * Note: Finalize domains after HSM initialization so that we
+	 * can startup non-root domains.
+	 * Note: Finalize domains before HART PMP configuration so
+	 * that we use correct domain for configuring PMP.
+	 */
+	rc = sbi_domain_finalize(scratch, hartid);
+	if (rc) {
+		sbi_printf("%s: domain finalize failed (error %d)\n",
+			   __func__, rc);
+		sbi_hart_hang();
+	}
+
+	sbi_boot_print_domains(scratch);
+
+	rc = sbi_hart_pmp_configure(scratch);
+	if (rc) {
+		sbi_printf("%s: PMP configure failed (error %d)\n",
+			   __func__, rc);
+		sbi_hart_hang();
+	}
+
+	/*
+	 * Note: Platform final initialization should be last so that
+	 * it sees correct domain assignment and PMP configuration.
+	 */
+#ifndef CONFIG_OPENSBI_FASTBOOT
 	rc = sbi_platform_final_init(plat, TRUE);
-	if (rc)
+	if (rc) {
+		sbi_printf("%s: platform final init failed (error %d)\n",
+			   __func__, rc);
 		sbi_hart_hang();
+	}
+#endif
 
-	if (!(scratch->options & SBI_SCRATCH_NO_BOOT_PRINTS))
-		sbi_boot_prints(scratch, hartid);
+	sbi_boot_print_hart(scratch, hartid);
 
 	wake_coldboot_harts(scratch, hartid);
 
@@ -209,14 +348,12 @@ static void __noreturn init_coldboot(struct sbi_scratch *scratch, u32 hartid)
 			     scratch->next_mode, FALSE);
 }
 
-static void __noreturn init_warmboot(struct sbi_scratch *scratch, u32 hartid)
+static void init_warm_startup(struct sbi_scratch *scratch, u32 hartid)
 {
 	int rc;
 	unsigned long *init_count;
 	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
 
-	wait_for_coldboot(scratch, hartid);
-
 	if (!init_count_offset)
 		sbi_hart_hang();
 
@@ -228,7 +365,7 @@ static void __noreturn init_warmboot(struct sbi_scratch *scratch, u32 hartid)
 	if (rc)
 		sbi_hart_hang();
 
-	rc = sbi_hart_init(scratch, hartid, FALSE);
+	rc = sbi_hart_init(scratch, FALSE);
 	if (rc)
 		sbi_hart_hang();
 
@@ -248,6 +385,10 @@ static void __noreturn init_warmboot(struct sbi_scratch *scratch, u32 hartid)
 	if (rc)
 		sbi_hart_hang();
 
+	rc = sbi_hart_pmp_configure(scratch);
+	if (rc)
+		sbi_hart_hang();
+
 	rc = sbi_platform_final_init(plat, FALSE);
 	if (rc)
 		sbi_hart_hang();
@@ -256,6 +397,40 @@ static void __noreturn init_warmboot(struct sbi_scratch *scratch, u32 hartid)
 	(*init_count)++;
 
 	sbi_hsm_prepare_next_jump(scratch, hartid);
+}
+
+static void init_warm_resume(struct sbi_scratch *scratch)
+{
+	int rc;
+
+	sbi_hsm_hart_resume_start(scratch);
+
+	rc = sbi_hart_reinit(scratch);
+	if (rc)
+		sbi_hart_hang();
+
+	rc = sbi_hart_pmp_configure(scratch);
+	if (rc)
+		sbi_hart_hang();
+
+	sbi_hsm_hart_resume_finish(scratch);
+}
+
+static void __noreturn init_warmboot(struct sbi_scratch *scratch, u32 hartid)
+{
+	int hstate;
+
+	wait_for_coldboot(scratch, hartid);
+
+	hstate = sbi_hsm_hart_get_state(sbi_domain_thishart_ptr(), hartid);
+	if (hstate < 0)
+		sbi_hart_hang();
+
+	if (hstate == SBI_HSM_STATE_SUSPENDED)
+		init_warm_resume(scratch);
+	else
+		init_warm_startup(scratch, hartid);
+
 	sbi_hart_switch_mode(hartid, scratch->next_arg1,
 			     scratch->next_addr,
 			     scratch->next_mode, FALSE);
@@ -277,6 +452,7 @@ static atomic_t coldboot_lottery = ATOMIC_INITIALIZER(0);
  */
 void __noreturn sbi_init(struct sbi_scratch *scratch)
 {
+	bool next_mode_supported	= FALSE;
 	bool coldboot			= FALSE;
 	u32 hartid			= current_hartid();
 	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
@@ -285,7 +461,33 @@ void __noreturn sbi_init(struct sbi_scratch *scratch)
 	    sbi_platform_hart_invalid(plat, hartid))
 		sbi_hart_hang();
 
-	if (atomic_xchg(&coldboot_lottery, 1) == 0)
+	switch (scratch->next_mode) {
+	case PRV_M:
+		next_mode_supported = TRUE;
+		break;
+	case PRV_S:
+		if (misa_extension('S'))
+			next_mode_supported = TRUE;
+		break;
+	case PRV_U:
+		if (misa_extension('U'))
+			next_mode_supported = TRUE;
+		break;
+	default:
+		sbi_hart_hang();
+	}
+
+	/*
+	 * Only the HART supporting privilege mode specified in the
+	 * scratch->next_mode should be allowed to become the coldboot
+	 * HART because the coldboot HART will be directly jumping to
+	 * the next booting stage.
+	 *
+	 * We use a lottery mechanism to select coldboot HART among
+	 * HARTs which satisfy above condition.
+	 */
+
+	if (next_mode_supported && atomic_xchg(&coldboot_lottery, 1) == 0)
 		coldboot = TRUE;
 
 	if (coldboot)

lib/sbi/sbi_ipi.c

@@ -12,6 +12,7 @@
 #include <sbi/riscv_atomic.h>
 #include <sbi/riscv_barrier.h>
 #include <sbi/sbi_bitops.h>
+#include <sbi/sbi_domain.h>
 #include <sbi/sbi_error.h>
 #include <sbi/sbi_hart.h>
 #include <sbi/sbi_hsm.h>
@@ -24,7 +25,7 @@ struct sbi_ipi_data {
 };
 
 static unsigned long ipi_data_off;
-
+static const struct sbi_ipi_device *ipi_dev = NULL;
 static const struct sbi_ipi_event_ops *ipi_ops_array[SBI_IPI_EVENT_MAX];
 
 static int sbi_ipi_send(struct sbi_scratch *scratch, u32 remote_hartid,
@@ -32,7 +33,6 @@ static int sbi_ipi_send(struct sbi_scratch *scratch, u32 remote_hartid,
 {
 	int ret;
 	struct sbi_scratch *remote_scratch = NULL;
-	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
 	struct sbi_ipi_data *ipi_data;
 	const struct sbi_ipi_event_ops *ipi_ops;
 
@@ -60,7 +60,9 @@ static int sbi_ipi_send(struct sbi_scratch *scratch, u32 remote_hartid,
 	 */
 	atomic_raw_set_bit(event, &ipi_data->ipi_type);
 	smp_wmb();
-	sbi_platform_ipi_send(plat, remote_hartid);
+
+	if (ipi_dev && ipi_dev->ipi_send)
+		ipi_dev->ipi_send(remote_hartid);
 
 	if (ipi_ops->sync)
 		ipi_ops->sync(scratch);
@@ -77,10 +79,11 @@ int sbi_ipi_send_many(ulong hmask, ulong hbase, u32 event, void *data)
 {
 	int rc;
 	ulong i, m;
+	struct sbi_domain *dom = sbi_domain_thishart_ptr();
 	struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
 
 	if (hbase != -1UL) {
-		rc = sbi_hsm_hart_started_mask(hbase, &m);
+		rc = sbi_hsm_hart_interruptible_mask(dom, hbase, &m);
 		if (rc)
 			return rc;
 		m &= hmask;
@@ -92,7 +95,7 @@ int sbi_ipi_send_many(ulong hmask, ulong hbase, u32 event, void *data)
 		}
 	} else {
 		hbase = 0;
-		while (!sbi_hsm_hart_started_mask(hbase, &m)) {
+		while (!sbi_hsm_hart_interruptible_mask(dom, hbase, &m)) {
 			/* Send IPIs */
 			for (i = hbase; m; i++, m >>= 1) {
 				if (m & 1UL)
@@ -176,12 +179,12 @@ void sbi_ipi_process(void)
 	unsigned int ipi_event;
 	const struct sbi_ipi_event_ops *ipi_ops;
 	struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
-	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
 	struct sbi_ipi_data *ipi_data =
 			sbi_scratch_offset_ptr(scratch, ipi_data_off);
-
 	u32 hartid = current_hartid();
-	sbi_platform_ipi_clear(plat, hartid);
+
+	if (ipi_dev && ipi_dev->ipi_clear)
+		ipi_dev->ipi_clear(hartid);
 
 	ipi_type = atomic_raw_xchg_ulong(&ipi_data->ipi_type, 0);
 	ipi_event = 0;
@@ -199,6 +202,25 @@ skip:
 	};
 }
 
+void sbi_ipi_raw_send(u32 target_hart)
+{
+	if (ipi_dev && ipi_dev->ipi_send)
+		ipi_dev->ipi_send(target_hart);
+}
+
+const struct sbi_ipi_device *sbi_ipi_get_device(void)
+{
+	return ipi_dev;
+}
+
+void sbi_ipi_set_device(const struct sbi_ipi_device *dev)
+{
+	if (!dev || ipi_dev)
+		return;
+
+	ipi_dev = dev;
+}
+
 int sbi_ipi_init(struct sbi_scratch *scratch, bool cold_boot)
 {
 	int ret;
@@ -228,7 +250,10 @@ int sbi_ipi_init(struct sbi_scratch *scratch, bool cold_boot)
 	ipi_data = sbi_scratch_offset_ptr(scratch, ipi_data_off);
 	ipi_data->ipi_type = 0x00;
 
-	/* Platform init */
+	/*
+	 * Initialize platform IPI support. This will also clear any
+	 * pending IPIs for current/calling HART.
+	 */
 	ret = sbi_platform_ipi_init(sbi_platform_ptr(scratch), cold_boot);
 	if (ret)
 		return ret;

lib/sbi/sbi_math.c

@@ -0,0 +1,23 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Common helper functions used across OpenSBI project.
+ *
+ * Authors:
+ *   Atish Patra <atish.patra@wdc.com>
+ */
+
+unsigned long log2roundup(unsigned long x)
+{
+	unsigned long ret = 0;
+
+	while (ret < __riscv_xlen) {
+		if (x <= (1UL << ret))
+			break;
+		ret++;
+	}
+
+	return ret;
+}

lib/sbi/sbi_misaligned_ldst.c

@@ -24,7 +24,7 @@ union reg_data {
 int sbi_misaligned_load_handler(ulong addr, ulong tval2, ulong tinst,
 				struct sbi_trap_regs *regs)
 {
-	ulong insn;
+	ulong insn, insn_len;
 	union reg_data val;
 	struct sbi_trap_info uptrap;
 	int i, fp = 0, shift = 0, len = 0;
@@ -35,6 +35,7 @@ int sbi_misaligned_load_handler(ulong addr, ulong tval2, ulong tinst,
 		 * transformed instruction or custom instruction.
 		 */
 		insn = tinst | INSN_16BIT_MASK;
+		insn_len = (tinst & 0x2) ? INSN_LEN(insn) : 2;
 	} else {
 		/*
 		 * Bit[0] == 0 implies trapped instruction value is
@@ -45,6 +46,7 @@ int sbi_misaligned_load_handler(ulong addr, ulong tval2, ulong tinst,
 			uptrap.epc = regs->mepc;
 			return sbi_trap_redirect(regs, &uptrap);
 		}
+		insn_len = INSN_LEN(insn);
 	}
 
 	if ((insn & INSN_MASK_LW) == INSN_MATCH_LW) {
@@ -126,7 +128,7 @@ int sbi_misaligned_load_handler(ulong addr, ulong tval2, ulong tinst,
 	}
 
 	if (!fp)
-		SET_RD(insn, regs, val.data_ulong << shift >> shift);
+		SET_RD(insn, regs, ((long)(val.data_ulong << shift)) >> shift);
 #ifdef __riscv_flen
 	else if (len == 8)
 		SET_F64_RD(insn, regs, val.data_u64);
@@ -134,7 +136,7 @@ int sbi_misaligned_load_handler(ulong addr, ulong tval2, ulong tinst,
 		SET_F32_RD(insn, regs, val.data_ulong);
 #endif
 
-	regs->mepc += INSN_LEN(insn);
+	regs->mepc += insn_len;
 
 	return 0;
 }
@@ -142,7 +144,7 @@ int sbi_misaligned_load_handler(ulong addr, ulong tval2, ulong tinst,
 int sbi_misaligned_store_handler(ulong addr, ulong tval2, ulong tinst,
 				 struct sbi_trap_regs *regs)
 {
-	ulong insn;
+	ulong insn, insn_len;
 	union reg_data val;
 	struct sbi_trap_info uptrap;
 	int i, len = 0;
@@ -153,6 +155,7 @@ int sbi_misaligned_store_handler(ulong addr, ulong tval2, ulong tinst,
 		 * transformed instruction or custom instruction.
 		 */
 		insn = tinst | INSN_16BIT_MASK;
+		insn_len = (tinst & 0x2) ? INSN_LEN(insn) : 2;
 	} else {
 		/*
 		 * Bit[0] == 0 implies trapped instruction value is
@@ -163,6 +166,7 @@ int sbi_misaligned_store_handler(ulong addr, ulong tval2, ulong tinst,
 			uptrap.epc = regs->mepc;
 			return sbi_trap_redirect(regs, &uptrap);
 		}
+		insn_len = INSN_LEN(insn);
 	}
 
 	val.data_ulong = GET_RS2(insn, regs);
@@ -233,7 +237,7 @@ int sbi_misaligned_store_handler(ulong addr, ulong tval2, ulong tinst,
 		}
 	}
 
-	regs->mepc += INSN_LEN(insn);
+	regs->mepc += insn_len;
 
 	return 0;
 }

lib/sbi/sbi_platform.c

@@ -0,0 +1,81 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Atish Patra <atish.patra@wdc.com>
+ */
+
+#include <sbi/sbi_console.h>
+#include <sbi/sbi_platform.h>
+#include <sbi/sbi_string.h>
+
+static inline char *sbi_platform_feature_id2string(unsigned long feature)
+{
+	char *fstr = NULL;
+
+	if (!feature)
+		return NULL;
+
+	switch (feature) {
+	case SBI_PLATFORM_HAS_MFAULTS_DELEGATION:
+		fstr = "mfdeleg";
+		break;
+	default:
+		break;
+	}
+
+	return fstr;
+}
+
+void sbi_platform_get_features_str(const struct sbi_platform *plat,
+				   char *features_str, int nfstr)
+{
+	unsigned long features, feat = 1UL;
+	char *temp;
+	int offset = 0;
+
+	if (!plat || !features_str || !nfstr)
+		return;
+	sbi_memset(features_str, 0, nfstr);
+
+	features = sbi_platform_get_features(plat);
+	if (!features)
+		goto done;
+
+	do {
+		if (features & feat) {
+			temp = sbi_platform_feature_id2string(feat);
+			if (temp) {
+				sbi_snprintf(features_str + offset, nfstr,
+					     "%s,", temp);
+				offset = offset + sbi_strlen(temp) + 1;
+			}
+		}
+		feat = feat << 1;
+	} while (feat <= SBI_PLATFORM_HAS_LAST_FEATURE);
+
+done:
+	if (offset)
+		features_str[offset - 1] = '\0';
+	else
+		sbi_strncpy(features_str, "none", nfstr);
+}
+
+u32 sbi_platform_hart_index(const struct sbi_platform *plat, u32 hartid)
+{
+	u32 i;
+
+	if (!plat)
+		return -1U;
+	if (plat->hart_index2id) {
+		for (i = 0; i < plat->hart_count; i++) {
+			if (plat->hart_index2id[i] == hartid)
+				return i;
+		}
+		return -1U;
+	}
+
+	return hartid;
+}

lib/sbi/sbi_string.c

@@ -14,6 +14,10 @@
 
 #include <sbi/sbi_string.h>
 
+/*
+  Provides sbi_strcmp for the completeness of supporting string functions.
+  it is not recommended to use sbi_strcmp() but use sbi_strncmp instead.
+*/
 int sbi_strcmp(const char *a, const char *b)
 {
 	/* search first diff or end of string */
@@ -23,6 +27,15 @@ int sbi_strcmp(const char *a, const char *b)
 	return *a - *b;
 }
 
+int sbi_strncmp(const char *a, const char *b, size_t count)
+{
+	/* search first diff or end of string */
+	for (; count > 0 && *a == *b && *a != '\0'; a++, b++, count--)
+		;
+
+	return *a - *b;
+}
+
 size_t sbi_strlen(const char *str)
 {
 	unsigned long ret = 0;

lib/sbi/sbi_system.c

@@ -10,6 +10,7 @@
 
 #include <sbi/riscv_asm.h>
 #include <sbi/sbi_bitops.h>
+#include <sbi/sbi_domain.h>
 #include <sbi/sbi_hart.h>
 #include <sbi/sbi_hsm.h>
 #include <sbi/sbi_platform.h>
@@ -17,14 +18,40 @@
 #include <sbi/sbi_ipi.h>
 #include <sbi/sbi_init.h>
 
-void __noreturn sbi_system_reboot(u32 type)
+static const struct sbi_system_reset_device *reset_dev = NULL;
+
+const struct sbi_system_reset_device *sbi_system_reset_get_device(void)
+{
+	return reset_dev;
+}
+
+void sbi_system_reset_set_device(const struct sbi_system_reset_device *dev)
+{
+	if (!dev || reset_dev)
+		return;
+
+	reset_dev = dev;
+}
+
+bool sbi_system_reset_supported(u32 reset_type, u32 reset_reason)
+{
+	if (reset_dev && reset_dev->system_reset_check &&
+	    reset_dev->system_reset_check(reset_type, reset_reason))
+		return TRUE;
+
+	return FALSE;
+}
+
+#include <sbi/riscv_io.h>
+void __noreturn sbi_system_reset(u32 reset_type, u32 reset_reason)
 {
 	ulong hbase = 0, hmask;
 	u32 cur_hartid = current_hartid();
+	struct sbi_domain *dom = sbi_domain_thishart_ptr();
 	struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
 
 	/* Send HALT IPI to every hart other than the current hart */
-	while (!sbi_hsm_hart_started_mask(hbase, &hmask)) {
+	while (!sbi_hsm_hart_interruptible_mask(dom, hbase, &hmask)) {
 		if (hbase <= cur_hartid)
 			hmask &= ~(1UL << (cur_hartid - hbase));
 		if (hmask)
@@ -35,34 +62,98 @@ void __noreturn sbi_system_reboot(u32 type)
 	/* Stop current HART */
 	sbi_hsm_hart_stop(scratch, FALSE);
 
-	/* Platform specific reooot */
-	sbi_platform_system_reboot(sbi_platform_ptr(scratch), type);
+	/* Platform specific reset if domain allowed system reset */
+	if (dom->system_reset_allowed &&
+	    reset_dev && reset_dev->system_reset)
+		reset_dev->system_reset(reset_type, reset_reason);
 
-	/* If platform specific reboot did not work then do sbi_exit() */
+	writew(0x5555, (void *)0x100000); // qemu poweroff
+
+	/* If platform specific reset did not work then do sbi_exit() */
 	sbi_exit(scratch);
 }
 
-void __noreturn sbi_system_shutdown(u32 type)
-{
-	ulong hbase = 0, hmask;
-	u32 cur_hartid = current_hartid();
-	struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
+static const struct sbi_system_suspend_device *suspend_dev;
 
-	/* Send HALT IPI to every hart other than the current hart */
-	while (!sbi_hsm_hart_started_mask(hbase, &hmask)) {
-		if (hbase <= cur_hartid)
-			hmask &= ~(1UL << (cur_hartid - hbase));
-		if (hmask)
-			sbi_ipi_send_halt(hmask, hbase);
-		hbase += BITS_PER_LONG;
+const struct sbi_system_suspend_device *sbi_system_suspend_get_device(void)
+{
+	return suspend_dev;
+}
+
+void sbi_system_suspend_set_device(struct sbi_system_suspend_device *dev)
+{
+	if (!dev || suspend_dev)
+		return;
+
+	suspend_dev = dev;
+}
+
+bool sbi_system_suspend_supported(u32 sleep_type)
+{
+	return suspend_dev && suspend_dev->system_suspend_check &&
+	       suspend_dev->system_suspend_check(sleep_type) == 0;
+}
+
+int sbi_system_suspend(u32 sleep_type, ulong resume_addr, ulong opaque)
+{
+	const struct sbi_domain *dom = sbi_domain_thishart_ptr();
+	struct sbi_scratch *scratch  = sbi_scratch_thishart_ptr();
+	void (*jump_warmboot)(void)  = (void (*)(void))scratch->warmboot_addr;
+	//unsigned int hartid = current_hartid();
+	unsigned long prev_mode;
+	//unsigned long i, j;
+	int ret;
+
+	if (!dom || !dom->system_suspend_allowed)
+		return SBI_EFAIL;
+
+	if (!suspend_dev || !suspend_dev->system_suspend ||
+			!suspend_dev->system_suspend_check)
+		return SBI_EFAIL;
+
+	ret = suspend_dev->system_suspend_check(sleep_type);
+	if (ret != SBI_OK)
+		return ret;
+
+	prev_mode = (csr_read(CSR_MSTATUS) & MSTATUS_MPP) >> MSTATUS_MPP_SHIFT;
+	if (prev_mode != PRV_S && prev_mode != PRV_U)
+		return SBI_EFAIL;
+
+	//FIX ME: hartindex to hart
+	//sbi_hartmask_for_each_hartindex(j, &dom->assigned_harts) {
+	//        //i = sbi_hartindex_to_hartid(j);
+	//        if (i == hartid)
+	//                continue;
+	//        if (__sbi_hsm_hart_get_state(i) != SBI_HSM_STATE_STOPPED)
+	//                return SBI_ERR_DENIED;
+	//}
+
+	if (!sbi_domain_check_addr(dom, resume_addr, prev_mode,
+				   SBI_DOMAIN_EXECUTE))
+		return SBI_EINVALID_ADDR;
+
+	if (!sbi_hsm_hart_change_state(scratch, SBI_HSM_STATE_STARTED,
+				       SBI_HSM_STATE_SUSPENDED))
+		return SBI_EFAIL;
+
+	/* Prepare for resume */
+	scratch->next_mode = prev_mode;
+	scratch->next_addr = resume_addr;
+	scratch->next_arg1 = opaque;
+
+	__sbi_hsm_suspend_non_ret_save(scratch);
+
+	/* Suspend */
+	ret = suspend_dev->system_suspend(sleep_type, scratch->warmboot_addr);
+	if (ret != SBI_OK) {
+		if (!sbi_hsm_hart_change_state(scratch, SBI_HSM_STATE_SUSPENDED,
+					       SBI_HSM_STATE_STARTED))
+			sbi_hart_hang();
+		return ret;
 	}
 
-	/* Stop current HART */
-	sbi_hsm_hart_stop(scratch, FALSE);
+	/* Resume */
+	jump_warmboot();
 
-	/* Platform specific shutdown */
-	sbi_platform_system_shutdown(sbi_platform_ptr(scratch), type);
-
-	/* If platform specific shutdown did not work then do sbi_exit() */
-	sbi_exit(scratch);
+	__builtin_unreachable();
 }

lib/sbi/sbi_timer.c

@@ -10,14 +10,17 @@
 #include <sbi/riscv_asm.h>
 #include <sbi/riscv_encoding.h>
 #include <sbi/sbi_error.h>
+#include <sbi/sbi_hart.h>
 #include <sbi/sbi_platform.h>
 #include <sbi/sbi_scratch.h>
 #include <sbi/sbi_timer.h>
 
 static unsigned long time_delta_off;
+static u64 (*get_time_val)(void);
+static const struct sbi_timer_device *timer_dev = NULL;
 
 #if __riscv_xlen == 32
-u64 get_ticks(void)
+static u64 get_ticks(void)
 {
 	u32 lo, hi, tmp;
 	__asm__ __volatile__("1:\n"
@@ -29,7 +32,7 @@ u64 get_ticks(void)
 	return ((u64)hi << 32) | lo;
 }
 #else
-u64 get_ticks(void)
+static u64 get_ticks(void)
 {
 	unsigned long n;
 
@@ -38,14 +41,16 @@ u64 get_ticks(void)
 }
 #endif
 
+static u64 get_platform_ticks(void)
+{
+	return timer_dev->timer_value();
+}
+
 u64 sbi_timer_value(void)
 {
-	const struct sbi_platform *plat = sbi_platform_thishart_ptr();
-
-	if (sbi_platform_has_timer_value(plat))
-		return sbi_platform_timer_value(plat);
-	else
-		return get_ticks();
+	if (get_time_val)
+		return get_time_val();
+	return 0;
 }
 
 u64 sbi_timer_virt_value(void)
@@ -83,7 +88,8 @@ void sbi_timer_set_delta_upper(ulong delta_upper)
 
 void sbi_timer_event_start(u64 next_event)
 {
-	sbi_platform_timer_event_start(sbi_platform_thishart_ptr(), next_event);
+	if (timer_dev && timer_dev->timer_event_start)
+		timer_dev->timer_event_start(next_event);
 	csr_clear(CSR_MIP, MIP_STIP);
 	csr_set(CSR_MIE, MIP_MTIP);
 }
@@ -94,15 +100,34 @@ void sbi_timer_process(void)
 	csr_set(CSR_MIP, MIP_STIP);
 }
 
+const struct sbi_timer_device *sbi_timer_get_device(void)
+{
+	return timer_dev;
+}
+
+void sbi_timer_set_device(const struct sbi_timer_device *dev)
+{
+	if (!dev || timer_dev)
+		return;
+
+	timer_dev = dev;
+	if (!get_time_val && timer_dev->timer_value)
+		get_time_val = get_platform_ticks;
+}
+
 int sbi_timer_init(struct sbi_scratch *scratch, bool cold_boot)
 {
 	u64 *time_delta;
+	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
 
 	if (cold_boot) {
 		time_delta_off = sbi_scratch_alloc_offset(sizeof(*time_delta),
 							  "TIME_DELTA");
 		if (!time_delta_off)
 			return SBI_ENOMEM;
+
+		if (sbi_hart_has_feature(scratch, SBI_HART_HAS_TIME))
+			get_time_val = get_ticks;
 	} else {
 		if (!time_delta_off)
 			return SBI_ENOMEM;
@@ -111,12 +136,13 @@ int sbi_timer_init(struct sbi_scratch *scratch, bool cold_boot)
 	time_delta = sbi_scratch_offset_ptr(scratch, time_delta_off);
 	*time_delta = 0;
 
-	return sbi_platform_timer_init(sbi_platform_ptr(scratch), cold_boot);
+	return sbi_platform_timer_init(plat, cold_boot);
 }
 
 void sbi_timer_exit(struct sbi_scratch *scratch)
 {
-	sbi_platform_timer_event_stop(sbi_platform_ptr(scratch));
+	if (timer_dev && timer_dev->timer_event_stop)
+		timer_dev->timer_event_stop();
 
 	csr_clear(CSR_MIP, MIP_STIP);
 	csr_clear(CSR_MIE, MIP_MTIP);