platform: generic: sophgo: add mango soc support
The mango cpu of sophgo is a 64 cores C920 CPU. The board with mango can have at most two sockets. The CPU have the following features: 1) support RV64GCV 2) one seperate timer each cluster 3) T-HEAD pmu device Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
This commit is contained in:
committed by
xingxg2022
parent
c6a092cd80
commit
35fb234d39
@@ -35,6 +35,7 @@ struct aclint_mtimer_data {
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u32 hart_count;
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u32 hart_count;
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bool has_64bit_mmio;
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bool has_64bit_mmio;
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bool has_shared_mtime;
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bool has_shared_mtime;
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bool use_extern_domain;
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/* Private details (initialized and used by ACLINT MTIMER library) */
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/* Private details (initialized and used by ACLINT MTIMER library) */
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struct aclint_mtimer_data *time_delta_reference;
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struct aclint_mtimer_data *time_delta_reference;
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unsigned long time_delta_computed;
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unsigned long time_delta_computed;
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@@ -274,6 +274,10 @@ struct sbi_trap_regs *sbi_trap_handler(struct sbi_trap_regs *regs)
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}
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}
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if (mcause & (1UL << (__riscv_xlen - 1))) {
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if (mcause & (1UL << (__riscv_xlen - 1))) {
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if (misa_extension('S')) {
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__asm__ __volatile__("sfence.vma");
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}
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if (sbi_hart_has_extension(sbi_scratch_thishart_ptr(),
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if (sbi_hart_has_extension(sbi_scratch_thishart_ptr(),
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SBI_HART_EXT_SMAIA))
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SBI_HART_EXT_SMAIA))
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rc = sbi_trap_aia_irq(regs, mcause);
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rc = sbi_trap_aia_irq(regs, mcause);
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@@ -318,6 +322,10 @@ struct sbi_trap_regs *sbi_trap_handler(struct sbi_trap_regs *regs)
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trap.tinst = mtinst;
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trap.tinst = mtinst;
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trap.gva = sbi_regs_gva(regs);
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trap.gva = sbi_regs_gva(regs);
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if (misa_extension('S')) {
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__asm__ __volatile__("sfence.vma");
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}
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rc = sbi_trap_redirect(regs, &trap);
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rc = sbi_trap_redirect(regs, &trap);
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break;
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break;
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};
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};
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@@ -57,6 +57,7 @@ static const struct fdt_match ipi_mswi_match[] = {
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{ .compatible = "riscv,clint0", .data = &clint_offset },
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{ .compatible = "riscv,clint0", .data = &clint_offset },
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{ .compatible = "sifive,clint0", .data = &clint_offset },
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{ .compatible = "sifive,clint0", .data = &clint_offset },
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{ .compatible = "thead,c900-clint", .data = &clint_offset },
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{ .compatible = "thead,c900-clint", .data = &clint_offset },
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{ .compatible = "thead,c900-clint-mswi", .data = &clint_offset },
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{ .compatible = "riscv,aclint-mswi" },
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{ .compatible = "riscv,aclint-mswi" },
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{ },
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{ },
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};
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};
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@@ -202,7 +202,7 @@ int aclint_mtimer_cold_init(struct aclint_mtimer_data *mt,
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SBI_DOMAIN_MEMREGION_M_WRITABLE));
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SBI_DOMAIN_MEMREGION_M_WRITABLE));
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if (rc)
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if (rc)
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return rc;
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return rc;
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} else {
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} else if (!mt->use_extern_domain) {
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rc = sbi_domain_root_add_memrange(mt->mtime_addr,
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rc = sbi_domain_root_add_memrange(mt->mtime_addr,
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mt->mtime_size, MTIMER_REGION_ALIGN,
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mt->mtime_size, MTIMER_REGION_ALIGN,
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(SBI_DOMAIN_MEMREGION_MMIO |
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(SBI_DOMAIN_MEMREGION_MMIO |
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@@ -13,12 +13,13 @@
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#include <sbi_utils/timer/fdt_timer.h>
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#include <sbi_utils/timer/fdt_timer.h>
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#include <sbi_utils/timer/aclint_mtimer.h>
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#include <sbi_utils/timer/aclint_mtimer.h>
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#define MTIMER_MAX_NR 16
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#define MTIMER_MAX_NR 32
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struct timer_mtimer_quirks {
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struct timer_mtimer_quirks {
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unsigned int mtime_offset;
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unsigned int mtime_offset;
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bool has_64bit_mmio;
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bool has_64bit_mmio;
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bool without_mtime;
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bool without_mtime;
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bool use_extern_domain;
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};
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};
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static unsigned long mtimer_count = 0;
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static unsigned long mtimer_count = 0;
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@@ -66,6 +67,7 @@ static int timer_mtimer_cold_init(void *fdt, int nodeoff,
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mt->mtimecmp_addr += quirks->mtime_offset;
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mt->mtimecmp_addr += quirks->mtime_offset;
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/* Apply additional CLINT quirks */
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/* Apply additional CLINT quirks */
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mt->has_64bit_mmio = quirks->has_64bit_mmio;
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mt->has_64bit_mmio = quirks->has_64bit_mmio;
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mt->use_extern_domain = quirks->use_extern_domain;
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} else { /* RISC-V ACLINT MTIMER */
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} else { /* RISC-V ACLINT MTIMER */
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/* Set ACLINT MTIMER addresses */
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/* Set ACLINT MTIMER addresses */
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mt->mtime_addr = addr[0];
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mt->mtime_addr = addr[0];
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@@ -129,10 +131,18 @@ static const struct timer_mtimer_quirks thead_clint_quirks = {
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.without_mtime = true,
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.without_mtime = true,
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};
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};
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static const struct timer_mtimer_quirks thead_clint_sep_quirks = {
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.mtime_offset = CLINT_MTIMER_OFFSET,
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.without_mtime = true,
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.use_extern_domain = true,
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};
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static const struct fdt_match timer_mtimer_match[] = {
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static const struct fdt_match timer_mtimer_match[] = {
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{ .compatible = "riscv,clint0", .data = &sifive_clint_quirks },
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{ .compatible = "riscv,clint0", .data = &sifive_clint_quirks },
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{ .compatible = "sifive,clint0", .data = &sifive_clint_quirks },
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{ .compatible = "sifive,clint0", .data = &sifive_clint_quirks },
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{ .compatible = "thead,c900-clint", .data = &thead_clint_quirks },
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{ .compatible = "thead,c900-clint", .data = &thead_clint_quirks },
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{ .compatible = "thead,c900-clint-mtimer",
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.data = &thead_clint_sep_quirks },
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{ .compatible = "riscv,aclint-mtimer" },
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{ .compatible = "riscv,aclint-mtimer" },
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{ },
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{ },
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};
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};
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@@ -51,6 +51,10 @@ config PLATFORM_STARFIVE_JH7110
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bool "StarFive JH7110 support"
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bool "StarFive JH7110 support"
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default n
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default n
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config PLATFORM_SOPHGO_MANGO
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bool "Sophgo MANGO support"
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default n
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source "$(OPENSBI_SRC_DIR)/platform/generic/andes/Kconfig"
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source "$(OPENSBI_SRC_DIR)/platform/generic/andes/Kconfig"
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endif
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endif
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@@ -4,6 +4,7 @@ CONFIG_PLATFORM_RENESAS_RZFIVE=y
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CONFIG_PLATFORM_SIFIVE_FU540=y
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CONFIG_PLATFORM_SIFIVE_FU540=y
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CONFIG_PLATFORM_SIFIVE_FU740=y
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CONFIG_PLATFORM_SIFIVE_FU740=y
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CONFIG_PLATFORM_STARFIVE_JH7110=y
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CONFIG_PLATFORM_STARFIVE_JH7110=y
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CONFIG_PLATFORM_SOPHGO_MANGO=y
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CONFIG_FDT_GPIO=y
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CONFIG_FDT_GPIO=y
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CONFIG_FDT_GPIO_SIFIVE=y
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CONFIG_FDT_GPIO_SIFIVE=y
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CONFIG_FDT_GPIO_STARFIVE=y
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CONFIG_FDT_GPIO_STARFIVE=y
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@@ -124,4 +124,6 @@
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#define THEAD_C9XX_IRQ_PMU_OVF 17
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#define THEAD_C9XX_IRQ_PMU_OVF 17
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#define THEAD_C9XX_MIP_MOIP (_UL(1) << THEAD_C9XX_IRQ_PMU_OVF)
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#define THEAD_C9XX_MIP_MOIP (_UL(1) << THEAD_C9XX_IRQ_PMU_OVF)
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extern const struct sbi_pmu_device thead_c9xx_pmu_device;
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#endif
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#endif
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67
platform/generic/sophgo/mango.c
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67
platform/generic/sophgo/mango.c
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@@ -0,0 +1,67 @@
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/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c)
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*
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* Authors:
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* Inochi Amaoto <inochiama@outlook.com>
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* YuQing Cai <caiyuqing_hz@163.com>
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* ZhenYu Zhang <1204122531@qq.com>
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*/
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#include <platform_override.h>
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#include <thead_c9xx.h>
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_encoding.h>
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#include <sbi/sbi_const.h>
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#include <sbi/sbi_ecall_interface.h>
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#include <sbi/sbi_pmu.h>
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#include <sbi/sbi_domain.h>
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#include <sbi/sbi_platform.h>
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#include <sbi_utils/fdt/fdt_helper.h>
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#include <sbi_utils/timer/aclint_mtimer.h>
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#define SOPHGO_MANGO_TIMER_BASE 0x70ac000000UL
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#define SOPHGO_MANGO_TIMER_OFFSET 0x10000UL
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int mango_early_init(bool cold_boot, const struct fdt_match *match)
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{
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const struct sbi_platform * plat = sbi_platform_thishart_ptr();
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/*
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* Sophgo mango board use seperate 16/32 timers while initiating,
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* merge them as a single domain to avoid wasting.
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*/
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if (cold_boot)
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return sbi_domain_root_add_memrange(SOPHGO_MANGO_TIMER_BASE,
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SOPHGO_MANGO_TIMER_OFFSET *
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sbi_platform_hart_count(plat),
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MTIMER_REGION_ALIGN,
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(SBI_DOMAIN_MEMREGION_MMIO |
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SBI_DOMAIN_MEMREGION_M_READABLE |
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SBI_DOMAIN_MEMREGION_M_WRITABLE));
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return 0;
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}
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static int mango_extensions_init(const struct fdt_match *match,
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struct sbi_hart_features *hfeatures)
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{
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sbi_pmu_set_device(&thead_c9xx_pmu_device);
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/* auto-detection doesn't work on t-head c9xx cores */
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hfeatures->mhpm_count = 29;
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hfeatures->mhpm_bits = 64;
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return 0;
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}
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static const struct fdt_match sophgo_mango_match[] = {
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{ .compatible = "sophgo,mango" },
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{ },
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};
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const struct platform_override sophgo_mango = {
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.match_table = sophgo_mango_match,
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.early_init = mango_early_init,
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.extensions_init = mango_extensions_init,
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};
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6
platform/generic/sophgo/objects.mk
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6
platform/generic/sophgo/objects.mk
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@@ -0,0 +1,6 @@
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#
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# SPDX-License-Identifier: BSD-2-Clause
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#
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carray-platform_override_modules-$(CONFIG_PLATFORM_SOPHGO_MANGO) += sophgo_mango
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platform-objs-$(CONFIG_PLATFORM_SOPHGO_MANGO) += sophgo/mango.o
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