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platform: generic: sophgo: add mango soc support

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The mango cpu of sophgo is a 64 cores C920 CPU. The board with mango can
have at most two sockets. The CPU have the following features:

 1) support RV64GCV
 2) one seperate timer each cluster
 3) T-HEAD pmu device

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
This commit is contained in:
Inochi Amaoto
2023-03-18 18:40:49 +08:00
committed by xingxg2022
parent c6a092cd80
commit 35fb234d39
10 changed files with 102 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
lib/sbi/sbi_trap.c
View File

@@ -274,6 +274,10 @@ struct sbi_trap_regs *sbi_trap_handler(struct sbi_trap_regs *regs)
}
if (mcause & (1UL << (__riscv_xlen - 1))) {
if (misa_extension('S')) {
__asm__ __volatile__("sfence.vma");
}
if (sbi_hart_has_extension(sbi_scratch_thishart_ptr(),
SBI_HART_EXT_SMAIA))
rc = sbi_trap_aia_irq(regs, mcause);
@@ -318,6 +322,10 @@ struct sbi_trap_regs *sbi_trap_handler(struct sbi_trap_regs *regs)
trap.tinst = mtinst;
trap.gva = sbi_regs_gva(regs);
if (misa_extension('S')) {
__asm__ __volatile__("sfence.vma");
}
rc = sbi_trap_redirect(regs, &trap);
break;
};

1
lib/utils/ipi/fdt_ipi_mswi.c
View File

@@ -57,6 +57,7 @@ static const struct fdt_match ipi_mswi_match[] = {
{ .compatible = "riscv,clint0", .data = &clint_offset },
{ .compatible = "sifive,clint0", .data = &clint_offset },
{ .compatible = "thead,c900-clint", .data = &clint_offset },
{ .compatible = "thead,c900-clint-mswi", .data = &clint_offset },
{ .compatible = "riscv,aclint-mswi" },
{ },
};

2
lib/utils/timer/aclint_mtimer.c
View File

@@ -202,7 +202,7 @@ int aclint_mtimer_cold_init(struct aclint_mtimer_data *mt,
SBI_DOMAIN_MEMREGION_M_WRITABLE));
if (rc)
return rc;
} else {
} else if (!mt->use_extern_domain) {
rc = sbi_domain_root_add_memrange(mt->mtime_addr,
mt->mtime_size, MTIMER_REGION_ALIGN,
(SBI_DOMAIN_MEMREGION_MMIO |

12
lib/utils/timer/fdt_timer_mtimer.c
View File

@@ -13,12 +13,13 @@
#include <sbi_utils/timer/fdt_timer.h>
#include <sbi_utils/timer/aclint_mtimer.h>
#define MTIMER_MAX_NR 16
#define MTIMER_MAX_NR 32
struct timer_mtimer_quirks {
unsigned int mtime_offset;
bool has_64bit_mmio;
bool without_mtime;
bool use_extern_domain;
};
static unsigned long mtimer_count = 0;
@@ -66,6 +67,7 @@ static int timer_mtimer_cold_init(void *fdt, int nodeoff,
mt->mtimecmp_addr += quirks->mtime_offset;
/* Apply additional CLINT quirks */
mt->has_64bit_mmio = quirks->has_64bit_mmio;
mt->use_extern_domain = quirks->use_extern_domain;
} else { /* RISC-V ACLINT MTIMER */
/* Set ACLINT MTIMER addresses */
mt->mtime_addr = addr[0];
@@ -129,10 +131,18 @@ static const struct timer_mtimer_quirks thead_clint_quirks = {
.without_mtime = true,
};
static const struct timer_mtimer_quirks thead_clint_sep_quirks = {
.mtime_offset = CLINT_MTIMER_OFFSET,
.without_mtime = true,
.use_extern_domain = true,
};
static const struct fdt_match timer_mtimer_match[] = {
{ .compatible = "riscv,clint0", .data = &sifive_clint_quirks },
{ .compatible = "sifive,clint0", .data = &sifive_clint_quirks },
{ .compatible = "thead,c900-clint", .data = &thead_clint_quirks },
{ .compatible = "thead,c900-clint-mtimer",
.data = &thead_clint_sep_quirks },
{ .compatible = "riscv,aclint-mtimer" },
{ },
};