Files
orangepi-build/external/cache/sources/linuxpg/8125APEF.cfg
orangepi-xunlong 4b897b01ff Add linuxpg
2023-04-21 17:12:13 +08:00

81 lines
2.0 KiB
INI

NODEID = 00 E0 4C 68 00 01
;ENDID = 00 E0 4C 68 FF FF
;VID = 10 EC
;DID = 81 25
SVID = 10 EC
SMID = 01 23
;Do not change following parameters without Realtek approval
;CONFIG0 = 07
;CONFIG1 = CF
CONFIGx = 3C
;For add-on device, please set CONFIG3 to 60H
;CONFIG3 = 60
;CONFIG4 = 14
;CONFIG5 = 02
;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1
;CONFIG5 = 0A
;PMC = C3 FF
;ROMBAR = 00
;LEDXCFG = High-Byte Low-Byte
;LEDX Bit 11: Low power mode enable
;LEDX Bit 10: Preboot enable
;Please make sure CONFIGx LED low power bit enabled
;(IO reg offset 0x53 bit 2 set to 0) before modifying LED low power mode or LED preboot
;LED0CFG = 02 01
;LED1CFG = 02 02
;LED2CFG = 02 08
;LED3CFG = 02 20
;LED Feature Functions
;Set BIT 0 to 0 : V1 led table.
;Set BIT 0 to 1 : V2 led table.
;BIT 1 to BIT 7 : Reserved
;LEDFEATUREFUNC = 60
;ROMCONF = 3F
;Bit 7-6 Boot Protocol
; 00 ==> PXE protocol
; 01 ==> RPL protocol
;Bit 5-4 Boot order (method)
; 00 ==> ROM disable
; 01 ==> Int 18h
; 10 ==> Int 19h
; 11 ==> PnP/BEV(BBS)
;Bit 3 Show Config Message
; 0 ==> Enable
; 1 ==> Disable
;Bit 2 Shift+F10 Menu Entry
; 0 ==> Enable
; 1 ==> Disable
;Bit 1-0 Show Config Time
; 00 ==> 3 Seconds
; 01 ==> 5 Seconds
; 10 ==> 1 Seconds
; 11 ==> 0 Second
;Serial Number in PCI Config Space
SN = 00 E0 4C 68 00 00 00 01
;LANCFG
;BIT 0:LAN Disable BIT 1:PHY Disable BIT 2:Link OK
;BIT 31:Clear LANCFG
;LANCFG = 00 00 00 00
;MDI swap
;MDI non-swap set to 00H, MDI swap set to 20H
;MDISWAP = 00
;Tx polarity swap
;BIT 7: P3 non-swap set to 0, P3 swap set to 1
;BIT 6: P2 non-swap set to 1, P2 swap set to 0
;BIT 5: P1 non-swap set to 0, P1 swap set to 1
;BIT 4: P0 non-swap set to 1, P0 swap set to 0
;BIT 0 to BIT 3 : Reserved
;TXPOLSWAP = 50
;DISFUNCXIOBAR = 00
;Disable: 00, Enable: 01
;Secure boot
;SECUREBOOT = 01
VERSION = 1.031