First Commit

external/patch/atf/atf-rk3399/add-trust-ini.patch

@@ -0,0 +1,21 @@
+diff --git a/trust.ini b/trust.ini
+new file mode 100644
+index 0000000..4af021a
+--- /dev/null
++++ b/trust.ini
+@@ -0,0 +1,15 @@
++[VERSION]
++MAJOR=1
++MINOR=0
++[BL30_OPTION]
++SEC=0
++[BL31_OPTION]
++SEC=1
++PATH=./build/rk3399/debug/bl31/bl31.elf
++ADDR=0x10000
++[BL32_OPTION]
++SEC=0
++[BL33_OPTION]
++SEC=0
++[OUTPUT]
++PATH=trust.bin

external/patch/atf/atf-rk3399/enable-logging.patch

@@ -0,0 +1,31 @@
+diff --git a/plat/rockchip/rk3399/rk3399_def.h b/plat/rockchip/rk3399/rk3399_def.h
+index ba83242..8d6ecfb 100644
+--- a/plat/rockchip/rk3399/rk3399_def.h
++++ b/plat/rockchip/rk3399/rk3399_def.h
+@@ -17,7 +17,7 @@
+ /**************************************************************************
+  * UART related constants
+  **************************************************************************/
+-#define RK3399_BAUDRATE			115200
++#define RK3399_BAUDRATE			1500000
+ #define RK3399_UART_CLOCK		24000000
+
+ /******************************************************************************
+diff --git a/plat/rockchip/common/bl31_plat_setup.c b/plat/rockchip/common/bl31_plat_setup.c
+index c4a0359..22d07e0 100644
+--- a/plat/rockchip/common/bl31_plat_setup.c
++++ b/plat/rockchip/common/bl31_plat_setup.c
+@@ -61,10 +61,13 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+
+ 	params_early_setup(arg1);
+
+-	if (rockchip_get_uart_base() != 0)
++	if (rockchip_get_uart_base() != 0) {
+ 		console_16550_register(rockchip_get_uart_base(),
+ 				       rockchip_get_uart_clock(),
+ 				       rockchip_get_uart_baudrate(), &console);
++		console_set_scope(&console.console,
++				  CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
++	}
+
+ 	VERBOSE("bl31_setup\n");

external/patch/atf/atf-rk3399/fix-reset-in-v2.2.patch

@@ -0,0 +1,56 @@
+From f4707a3c40bfc752a24c427263f7cbe8d7adfcd6 Mon Sep 17 00:00:00 2001
+From: Vasily Khoruzhick <anarsoul@gmail.com>
+Date: Fri, 15 Nov 2019 08:25:02 -0800
+Subject: [PATCH] plat/rockchip: initialize reset and poweroff GPIOs with known
+ invalid value
+
+And return NULL if we didn't get them in bl aux params otherwise reset and poweroff
+will be broken on platforms that do not have reset and poweroff GPIOs.
+
+Fixes: c1185ffde17c ("plat/rockchip: Switch to use new common BL aux parameter library")
+Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
+---
+ plat/rockchip/common/params_setup.c | 11 +++++++++--
+ 1 file changed, 9 insertions(+), 2 deletions(-)
+
+diff --git a/plat/rockchip/common/params_setup.c b/plat/rockchip/common/params_setup.c
+index 8c2e5e911b..b2fd2011e4 100644
+--- a/plat/rockchip/common/params_setup.c
++++ b/plat/rockchip/common/params_setup.c
+@@ -6,6 +6,7 @@
+ 
+ #include <assert.h>
+ #include <errno.h>
++#include <limits.h>
+ #include <string.h>
+ 
+ #include <lib/bl_aux_params/bl_aux_params.h>
+@@ -21,8 +22,8 @@
+ #include <plat_params.h>
+ #include <plat_private.h>
+ 
+-static struct bl_aux_gpio_info rst_gpio;
+-static struct bl_aux_gpio_info poweroff_gpio;
++static struct bl_aux_gpio_info rst_gpio = { .index = UINT_MAX } ;
++static struct bl_aux_gpio_info poweroff_gpio = { .index = UINT_MAX };
+ static struct bl_aux_gpio_info suspend_gpio[10];
+ uint32_t suspend_gpio_cnt;
+ static struct bl_aux_rk_apio_info suspend_apio;
+@@ -174,11 +175,17 @@ uint32_t rockchip_get_uart_clock(void)
+ 
+ struct bl_aux_gpio_info *plat_get_rockchip_gpio_reset(void)
+ {
++	if (rst_gpio.index == UINT_MAX)
++		return NULL;
++
+ 	return &rst_gpio;
+ }
+ 
+ struct bl_aux_gpio_info *plat_get_rockchip_gpio_poweroff(void)
+ {
++	if (poweroff_gpio.index == UINT_MAX)
++		return NULL;
++
+ 	return &poweroff_gpio;
+ }
+ 

external/patch/atf/atf-rk3399/switch-power-domains-on-before-reset.patch

@@ -0,0 +1,63 @@
+diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.c b/plat/rockchip/rk3399/drivers/pmu/pmu.c
+index 42589b9..8f2a419 100644
+--- a/plat/rockchip/rk3399/drivers/pmu/pmu.c
++++ b/plat/rockchip/rk3399/drivers/pmu/pmu.c
+@@ -400,7 +400,26 @@ static void pmu_power_domains_resume(void)
+ 	clk_gate_con_restore();
+ }
+ 
+-void rk3399_flush_l2_b(void)
++void pmu_power_domains_on(void)
++{
++	clk_gate_con_disable();
++	pmu_set_power_domain(PD_VDU, pmu_pd_on);
++	pmu_set_power_domain(PD_VCODEC, pmu_pd_on);
++	pmu_set_power_domain(PD_RGA, pmu_pd_on);
++	pmu_set_power_domain(PD_IEP, pmu_pd_on);
++	pmu_set_power_domain(PD_EDP, pmu_pd_on);
++	pmu_set_power_domain(PD_GMAC, pmu_pd_on);
++	pmu_set_power_domain(PD_SDIOAUDIO, pmu_pd_on);
++	pmu_set_power_domain(PD_HDCP, pmu_pd_on);
++	pmu_set_power_domain(PD_ISP1, pmu_pd_on);
++	pmu_set_power_domain(PD_ISP0, pmu_pd_on);
++	pmu_set_power_domain(PD_VO, pmu_pd_on);
++	pmu_set_power_domain(PD_TCPD1, pmu_pd_on);
++	pmu_set_power_domain(PD_TCPD0, pmu_pd_on);
++	pmu_set_power_domain(PD_GPU, pmu_pd_on);
++}
++
++void rk3399_flush_l2_b(void)
+ {
+ 	uint32_t wait_cnt = 0;
+ 
+diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.h b/plat/rockchip/rk3399/drivers/pmu/pmu.h
+index e1ba410..27a453b 100644
+--- a/plat/rockchip/rk3399/drivers/pmu/pmu.h
++++ b/plat/rockchip/rk3399/drivers/pmu/pmu.h
+@@ -136,5 +136,6 @@ struct pmu_slpdata_s {
+ extern uint32_t clst_warmboot_data[PLATFORM_CLUSTER_COUNT];
+ 
+ extern void sram_func_set_ddrctl_pll(uint32_t pll_src);
++void pmu_power_domains_on(void);
+ 
+ #endif /* PMU_H */
+diff --git a/plat/rockchip/rk3399/drivers/soc/soc.c b/plat/rockchip/rk3399/drivers/soc/soc.c
+index c877dbd..98b5ad6 100644
+--- a/plat/rockchip/rk3399/drivers/soc/soc.c
++++ b/plat/rockchip/rk3399/drivers/soc/soc.c
+@@ -17,6 +17,7 @@
+ #include <dram.h>
+ #include <m0_ctl.h>
+ #include <plat_private.h>
++#include <pmu.h>
+ #include <rk3399_def.h>
+ #include <secure.h>
+ #include <soc.h>
+@@ -327,6 +328,7 @@ void soc_global_soft_reset_init(void)
+ 
+ void __dead2 soc_global_soft_reset(void)
+ {
++	pmu_power_domains_on();
+ 	set_pll_slow_mode(VPLL_ID);
+ 	set_pll_slow_mode(NPLL_ID);
+ 	set_pll_slow_mode(GPLL_ID);

external/patch/atf/atf-rockchip64/add-trust-ini.patch

@@ -0,0 +1,21 @@
+diff --git a/trust.ini b/trust.ini
+new file mode 100644
+index 0000000..4af021a
+--- /dev/null
++++ b/trust.ini
+@@ -0,0 +1,15 @@
++[VERSION]
++MAJOR=1
++MINOR=2
++[BL30_OPTION]
++SEC=0
++[BL31_OPTION]
++SEC=1
++PATH=./build/rk322xh/debug/bl31/bl31.elf
++ADDR=0x10000
++[BL32_OPTION]
++SEC=0
++[BL33_OPTION]
++SEC=0
++[OUTPUT]
++PATH=trust.bin

external/patch/atf/atf-rockchip64/board_pinebook-pro/add-trust-ini.patch

@@ -0,0 +1,21 @@
+diff --git a/trust.ini b/trust.ini
+new file mode 100644
+index 0000000..4af021a
+--- /dev/null
++++ b/trust.ini
+@@ -0,0 +1,15 @@
++[VERSION]
++MAJOR=1
++MINOR=0
++[BL30_OPTION]
++SEC=0
++[BL31_OPTION]
++SEC=1
++PATH=./build/rk3399/debug/bl31/bl31.elf
++ADDR=0x10000
++[BL32_OPTION]
++SEC=0
++[BL33_OPTION]
++SEC=0
++[OUTPUT]
++PATH=trust.bin

external/patch/atf/atf-rockchip64/board_rockpro64/add-trust-ini.patch

@@ -0,0 +1,21 @@
+diff --git a/trust.ini b/trust.ini
+new file mode 100644
+index 0000000..4af021a
+--- /dev/null
++++ b/trust.ini
+@@ -0,0 +1,15 @@
++[VERSION]
++MAJOR=1
++MINOR=0
++[BL30_OPTION]
++SEC=0
++[BL31_OPTION]
++SEC=1
++PATH=./build/rk3399/debug/bl31/bl31.elf
++ADDR=0x10000
++[BL32_OPTION]
++SEC=0
++[BL33_OPTION]
++SEC=0
++[OUTPUT]
++PATH=trust.bin

external/patch/atf/atf-sunxi64/0001-Fix-reset-issue-on-H6-by-using-R_WDOG.patch

@@ -0,0 +1,29 @@
+From 82fa50eadf11f01e6315f5e2c2a29845e2a516b8 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megous@megous.com>
+Date: Mon, 8 Apr 2019 03:49:26 +0200
+Subject: [PATCH] Fix reset issue on H6 by using R_WDOG
+
+Inspired by froezuses patch here:
+
+https://forum.armbian.com/topic/9833-h6-famous-reboot-problem/?page=3
+
+Signed-off-by: Ondrej Jirman <megous@megous.com>
+---
+ plat/allwinner/sun50i_h6/include/sunxi_mmap.h | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/plat/allwinner/sun50i_h6/include/sunxi_mmap.h b/plat/allwinner/sun50i_h6/include/sunxi_mmap.h
+index f36491a8..f01745a4 100644
+--- a/plat/allwinner/sun50i_h6/include/sunxi_mmap.h
++++ b/plat/allwinner/sun50i_h6/include/sunxi_mmap.h
+@@ -58,4 +58,7 @@
+ #define SUNXI_R_UART_BASE		0x07080000
+ #define SUNXI_R_PIO_BASE		0x07022000
+ 
++#undef SUNXI_WDOG_BASE
++#define SUNXI_WDOG_BASE			SUNXI_R_WDOG_BASE
++
+ #endif /* SUNXI_MMAP_H */
+-- 
+2.21.0
+

external/patch/atf/atf-sunxi64/add-SRAM-mapping-for-SCPI.patch.disabled

@@ -0,0 +1,29 @@
+From 5ff3a09d64b6b9172d9007e3f77116902b9c2965 Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Mon, 8 Aug 2016 02:34:27 +0100
+Subject: [PATCH] sunxi: add SRAM regions to EL3 mapping
+
+Currently we only map the MMIO regions for actual peripheral devices
+in EL3. For the SCPI implementation we need access to the SRAM regions
+as well.
+Add a mapping entry that covers all three SRAM regions on the A64.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+---
+ plat/sun50iw1p1/aarch64/sunxi_common.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/plat/sun50iw1p1/aarch64/sunxi_common.c b/plat/sun50iw1p1/aarch64/sunxi_common.c
+index a2fa37a39..8ebcd9852 100644
+--- a/plat/sun50iw1p1/aarch64/sunxi_common.c
++++ b/plat/sun50iw1p1/aarch64/sunxi_common.c
+@@ -56,6 +56,9 @@ plat_config_t plat_config;
+  */
+ const mmap_region_t sunxi_mmap[] = {
+ 
++	// SRAM regions
++	{ 0x0010000,			0x0010000,
++		0x0030000,			MT_DEVICE | MT_RW | MT_NS },
+ 	// MMI/O region used by peripherals from 0x100.0000 to 0x200.0000
+ 	{ 0x1000000,			0x1000000,
+ 		0x1000000,			MT_DEVICE | MT_RW | MT_SECURE },

external/patch/atf/atf-sunxi64/enable-a53-errata-workaround.patch.disabled

@@ -0,0 +1,28 @@
+From 3efb52570e581d79f6e451ef88933423a61a9b55 Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Mon, 27 Mar 2017 21:56:08 +0100
+Subject: [PATCH] Makefile: (re-)enable A53 errata workaround
+
+The --fix-cortex-a53-843418 option to the linker was disabled before to
+also support older toolchains which don't know of this option.
+To not loose the bugfix for more recent toolchains introduce a feature
+check, which enables the option if the linker knows about it.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+---
+ Makefile | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/Makefile b/Makefile
+index f96e2cb37..87c307ded 100644
+--- a/Makefile
++++ b/Makefile
+@@ -234,7 +234,7 @@ CFLAGS			+= 	-nostdinc -pedantic -ffreestanding -Wall	\
+ CFLAGS			+=	-ffunction-sections -fdata-sections
+ LDFLAGS			+=	--fatal-warnings -O1
+ LDFLAGS			+=	--gc-sections
+-#LDFLAGS		+=	--fix-cortex-a53-843419
++LDFLAGS			+=	$(if $(shell $(LD) -v --fix-cortex-a53-843419 > /dev/null 2>&1 && echo 1),--fix-cortex-a53-843419)
+ 
+ 
+ CC			:=	${CROSS_COMPILE}gcc

external/patch/atf/atf-sunxi64/enable-additional-regulators.patch.disabled

@@ -0,0 +1,34 @@
+diff --git a/plat/sun50iw1p1/sunxi_power.c b/plat/sun50iw1p1/sunxi_power.c
+index a2ded04..75574b9
+--- a/plat/sun50iw1p1/sunxi_power.c
++++ b/plat/sun50iw1p1/sunxi_power.c
+@@ -229,8 +229,8 @@ static int pmic_setup(const char *dt_name)
+
+ 	/* Enable DC1SW to power PHY, DLDO4 for WiFi and DLDO1 for HDMI */
+ 	ret = sunxi_pmic_read(0x12);
+-	if ((ret & 0xc8) != 0xc8) {
+-		ret = sunxi_pmic_write(0x12, ret | 0xc8);
++	if ((ret & 0xd9) != 0xd9) {
++		ret = sunxi_pmic_write(0x12, ret | 0xd8);
+ 		if (ret < 0) {
+ 			NOTICE("PMIC: error %d enabling DC1SW/DLDO4/DLDO1\n",
+ 			       ret);
+@@ -272,8 +272,17 @@ static int pmic_setup(const char *dt_name)
+ 
+ 		INFO("PMIC: enabled Pinebook display\n");
+ 	}
+- 
++
+ 	sunxi_pmic_write(0x15, 0x1a);	/* DLDO1 = VCC3V3_HDMI voltage = 3.3V */
++	sunxi_pmic_write(0x21, 60);		/* Set DCDC2/CPU voltage to 1.1V */
++	sunxi_pmic_write(0x16, 0x12);	/* DLDO2 = VCC2V5_EDP voltage = 2.5V */
++	sunxi_pmic_write(0x1c, 0xa);	/* FLDO1 = VCC1V2_EDP voltage = 1.2V */
++	sunxi_pmic_write(0x91, 0x1a);	/* GPIO0LDO voltage = 3.3V */
++	sunxi_pmic_write(0x90, 0x3);	/* Enable GPIO0LDO */
++	sunxi_pmic_write(0x30, sunxi_pmic_read(0x30) | BIT(2)); /* Enable USB at Lime64 */
++	ret = sunxi_pmic_read(0x13);
++	/* Enable FLDO1 to power up eDP bridge */
++	ret = sunxi_pmic_write(0x13, ret | 0x4);
+ 
+ 	return 0;
+ }

external/patch/atf/atf-sunxi64/set-rsb-to-nonsec.patch.disabled

@@ -0,0 +1,15 @@
+diff --git a/plat/sun50iw1p1/sunxi_security.c b/plat/sun50iw1p1/sunxi_security.c
+index c0036c12..76d296bd 100644
+--- a/plat/sun50iw1p1/sunxi_security.c
++++ b/plat/sun50iw1p1/sunxi_security.c
+@@ -58,8 +58,9 @@ void sunxi_security_setup(void)
+ 	for (i = 0; i < 6; i++)
+ 		mmio_write_32(SPC_DECPORT_SET_REG(i), 0xff);
+ 
+-	/* switch RSB to secure */
++	/* switch RSB to secure
+ 	mmio_write_32(SPC_DECPORT_CLR_REG(3), 0x08);
++	*/
+ 	
+ 	/* set CCMU mbus_sec, bus_sec, pll_sec to non-secure */
+ 	mmio_write_32(0x01c20000+0x2f0, 0x7);