mirror of
https://github.com/DrHo1y/orangepi-build.git
synced 2026-11-08 08:47:20 +07:00
Support Orange Pi Zero3
This commit is contained in:
orangepi-xunlong
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BIN
external/packages/pack-uboot/sun50iw9/bin/boot0_sdcard.fex-linux5.4
vendored
Executable file
BIN
external/packages/pack-uboot/sun50iw9/bin/boot0_sdcard.fex-linux5.4
vendored
Executable file
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6
external/packages/pack-uboot/sun50iw9/bin/boot_package.cfg-linux5.4
vendored
Executable file
6
external/packages/pack-uboot/sun50iw9/bin/boot_package.cfg-linux5.4
vendored
Executable file
@@ -0,0 +1,6 @@
|
||||
[package]
|
||||
item=u-boot, u-boot.fex
|
||||
item=monitor, monitor.fex
|
||||
item=dtbo, p1.dtbo
|
||||
item=optee, optee.fex
|
||||
item=dtb, sunxi.fex
|
||||
3056
external/packages/pack-uboot/sun50iw9/bin/dts/orangepir1b-u-boot-current.dts
vendored
Normal file
3056
external/packages/pack-uboot/sun50iw9/bin/dts/orangepir1b-u-boot-current.dts
vendored
Normal file
File diff suppressed because it is too large
Load Diff
5998
external/packages/pack-uboot/sun50iw9/bin/dts/orangepir1b-u-boot-legacy.dts
vendored
Executable file
5998
external/packages/pack-uboot/sun50iw9/bin/dts/orangepir1b-u-boot-legacy.dts
vendored
Executable file
File diff suppressed because it is too large
Load Diff
3044
external/packages/pack-uboot/sun50iw9/bin/dts/orangepir1b-u-boot.dts
vendored
Normal file
3044
external/packages/pack-uboot/sun50iw9/bin/dts/orangepir1b-u-boot.dts
vendored
Normal file
File diff suppressed because it is too large
Load Diff
@@ -1476,10 +1476,10 @@
|
||||
};
|
||||
|
||||
twi1@0 {
|
||||
allwinner,pins = "PA2", "PA3";
|
||||
allwinner,pins = "PH0", "PH1";
|
||||
allwinner,pname = "twi1_scl", "twi1_sda";
|
||||
allwinner,function = "twi1";
|
||||
allwinner,muxsel = <0x4>;
|
||||
allwinner,muxsel = <0x5>;
|
||||
allwinner,drive = <0x1>;
|
||||
allwinner,pull = <0x0>;
|
||||
linux,phandle = <0x3f>;
|
||||
@@ -1487,7 +1487,7 @@
|
||||
};
|
||||
|
||||
twi1@1 {
|
||||
allwinner,pins = "PA2", "PA3";
|
||||
allwinner,pins = "PH0", "PH1";
|
||||
allwinner,function = "io_disabled";
|
||||
allwinner,muxsel = <0x7>;
|
||||
allwinner,drive = <0x1>;
|
||||
@@ -1497,7 +1497,7 @@
|
||||
};
|
||||
|
||||
twi2@0 {
|
||||
allwinner,pins = "PE20", "PE21";
|
||||
allwinner,pins = "PH2", "PH3";
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||||
allwinner,pname = "twi2_scl", "twi2_sda";
|
||||
allwinner,function = "twi2";
|
||||
allwinner,muxsel = <0x5>;
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||||
@@ -1508,7 +1508,7 @@
|
||||
};
|
||||
|
||||
twi2@1 {
|
||||
allwinner,pins = "PE20", "PE21";
|
||||
allwinner,pins = "PH2", "PH3";
|
||||
allwinner,function = "io_disabled";
|
||||
allwinner,muxsel = <0x7>;
|
||||
allwinner,drive = <0x1>;
|
||||
@@ -3478,7 +3478,7 @@
|
||||
//sd-uhs-ddr50;
|
||||
//sd-uhs-sdr104;
|
||||
ctl-spec-caps = <0x8>;
|
||||
vdmmc-supply = <®_dcdc5>;
|
||||
//vdmmc-supply = <®_dcdc5>;
|
||||
};
|
||||
|
||||
sdmmc@04021000 {
|
||||
|
||||
@@ -1371,7 +1371,7 @@
|
||||
};
|
||||
|
||||
uart2@0 {
|
||||
allwinner,pins = "PG15", "PG16", "PG17", "PG18";
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||||
allwinner,pins = "PH5", "PH6", "PH7", "PH8";
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||||
allwinner,pname = "uart2_tx", "uart2_rx", "uart2_rts", "uart2_cts";
|
||||
allwinner,function = "uart2";
|
||||
allwinner,muxsel = <0x2>;
|
||||
@@ -1382,7 +1382,7 @@
|
||||
};
|
||||
|
||||
uart2@1 {
|
||||
allwinner,pins = "PG15", "PG16", "PG17", "PG18";
|
||||
allwinner,pins = "PH5", "PH6", "PH7", "PH8";
|
||||
allwinner,function = "io_disabled";
|
||||
allwinner,muxsel = <0x7>;
|
||||
allwinner,drive = <0x1>;
|
||||
@@ -1476,10 +1476,10 @@
|
||||
};
|
||||
|
||||
twi1@0 {
|
||||
allwinner,pins = "PA2", "PA3";
|
||||
allwinner,pins = "PH0", "PH1";
|
||||
allwinner,pname = "twi1_scl", "twi1_sda";
|
||||
allwinner,function = "twi1";
|
||||
allwinner,muxsel = <0x4>;
|
||||
allwinner,muxsel = <0x5>;
|
||||
allwinner,drive = <0x1>;
|
||||
allwinner,pull = <0x0>;
|
||||
linux,phandle = <0x3f>;
|
||||
@@ -1487,7 +1487,7 @@
|
||||
};
|
||||
|
||||
twi1@1 {
|
||||
allwinner,pins = "PA2", "PA3";
|
||||
allwinner,pins = "PH0", "PH1";
|
||||
allwinner,function = "io_disabled";
|
||||
allwinner,muxsel = <0x7>;
|
||||
allwinner,drive = <0x1>;
|
||||
@@ -1497,7 +1497,7 @@
|
||||
};
|
||||
|
||||
twi2@0 {
|
||||
allwinner,pins = "PE20", "PE21";
|
||||
allwinner,pins = "PH2", "PH3";
|
||||
allwinner,pname = "twi2_scl", "twi2_sda";
|
||||
allwinner,function = "twi2";
|
||||
allwinner,muxsel = <0x5>;
|
||||
@@ -1508,7 +1508,7 @@
|
||||
};
|
||||
|
||||
twi2@1 {
|
||||
allwinner,pins = "PE20", "PE21";
|
||||
allwinner,pins = "PH2", "PH3";
|
||||
allwinner,function = "io_disabled";
|
||||
allwinner,muxsel = <0x7>;
|
||||
allwinner,drive = <0x1>;
|
||||
@@ -1539,7 +1539,7 @@
|
||||
};
|
||||
|
||||
twi4@0 {
|
||||
allwinner,pins = "PG15", "PG16";
|
||||
allwinner,pins = "PH6", "PH7";
|
||||
allwinner,pname = "twi4_scl", "twi4_sda";
|
||||
allwinner,function = "twi4";
|
||||
allwinner,muxsel = <0x5>;
|
||||
@@ -1550,7 +1550,7 @@
|
||||
};
|
||||
|
||||
twi4@1 {
|
||||
allwinner,pins = "PG15", "PG16";
|
||||
allwinner,pins = "PH6", "PH7";
|
||||
allwinner,function = "io_disabled";
|
||||
allwinner,muxsel = <0x7>;
|
||||
allwinner,drive = <0x1>;
|
||||
@@ -2565,7 +2565,7 @@
|
||||
phandle = <0x11a>;
|
||||
};
|
||||
|
||||
uart@05000000 {
|
||||
uart0: uart@05000000 {
|
||||
compatible = "allwinner,sun50i-uart";
|
||||
device_type = "uart0";
|
||||
reg = <0x0 0x5000000 0x0 0x400>;
|
||||
@@ -2581,7 +2581,7 @@
|
||||
pinctrl-0 = <0x187>;
|
||||
};
|
||||
|
||||
uart@05000400 {
|
||||
uart1: uart@05000400 {
|
||||
compatible = "allwinner,sun50i-uart";
|
||||
device_type = "uart1";
|
||||
reg = <0x0 0x5000400 0x0 0x400>;
|
||||
@@ -2597,7 +2597,7 @@
|
||||
phandle = <0x11c>;
|
||||
};
|
||||
|
||||
uart@05000800 {
|
||||
uart2: uart@05000800 {
|
||||
compatible = "allwinner,sun50i-uart";
|
||||
device_type = "uart2";
|
||||
reg = <0x0 0x5000800 0x0 0x400>;
|
||||
@@ -2607,13 +2607,11 @@
|
||||
pinctrl-0 = <0x30>;
|
||||
pinctrl-1 = <0x31>;
|
||||
uart2_port = <0x2>;
|
||||
uart2_type = <0x4>;
|
||||
uart2_type = <0x2>;
|
||||
status = "disabled";
|
||||
linux,phandle = <0x11d>;
|
||||
phandle = <0x11d>;
|
||||
};
|
||||
|
||||
uart@05000c00 {
|
||||
uart3: uart@05000c00 {
|
||||
compatible = "allwinner,sun50i-uart";
|
||||
device_type = "uart3";
|
||||
reg = <0x0 0x5000c00 0x0 0x400>;
|
||||
@@ -2629,7 +2627,7 @@
|
||||
phandle = <0x11e>;
|
||||
};
|
||||
|
||||
uart@05001000 {
|
||||
uart4: uart@05001000 {
|
||||
compatible = "allwinner,sun50i-uart";
|
||||
device_type = "uart4";
|
||||
reg = <0x0 0x5001000 0x0 0x400>;
|
||||
@@ -2645,7 +2643,7 @@
|
||||
phandle = <0x11f>;
|
||||
};
|
||||
|
||||
uart@05001400 {
|
||||
uart5: uart@05001400 {
|
||||
compatible = "allwinner,sun50i-uart";
|
||||
device_type = "uart5";
|
||||
reg = <0x0 0x5001400 0x0 0x400>;
|
||||
@@ -2661,7 +2659,7 @@
|
||||
phandle = <0x120>;
|
||||
};
|
||||
|
||||
twi@0x05002000 {
|
||||
i2c0: twi@0x05002000 {
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
compatible = "allwinner,sun50i-twi";
|
||||
@@ -2678,7 +2676,7 @@
|
||||
phandle = <0x121>;
|
||||
};
|
||||
|
||||
twi@0x05002400 {
|
||||
i2c1: twi@0x05002400 {
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
compatible = "allwinner,sun50i-twi";
|
||||
@@ -2695,7 +2693,7 @@
|
||||
phandle = <0x122>;
|
||||
};
|
||||
|
||||
twi@0x05002800 {
|
||||
i2c2: twi@0x05002800 {
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
compatible = "allwinner,sun50i-twi";
|
||||
@@ -2712,7 +2710,7 @@
|
||||
phandle = <0x123>;
|
||||
};
|
||||
|
||||
twi@0x05002c00 {
|
||||
i2c3: twi@0x05002c00 {
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
compatible = "allwinner,sun50i-twi";
|
||||
@@ -2729,7 +2727,7 @@
|
||||
phandle = <0x124>;
|
||||
};
|
||||
|
||||
twi@0x05003000 {
|
||||
i2c4: twi@0x05003000 {
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
compatible = "allwinner,sun50i-twi";
|
||||
@@ -2742,11 +2740,9 @@
|
||||
pinctrl-0 = <0x48>;
|
||||
pinctrl-1 = <0x49>;
|
||||
status = "disabled";
|
||||
linux,phandle = <0x125>;
|
||||
phandle = <0x125>;
|
||||
};
|
||||
|
||||
twi@0x07081400 {
|
||||
i2c5: twi@0x07081400 {
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
compatible = "allwinner,sun50i-twi";
|
||||
@@ -2760,78 +2756,149 @@
|
||||
pinctrl-1 = <0x4c>;
|
||||
status = "okay";
|
||||
no_suspend = <0x1>;
|
||||
linux,phandle = <0x126>;
|
||||
phandle = <0x126>;
|
||||
|
||||
pmu {
|
||||
compatible = "x-powers,axp1530";
|
||||
pmu0: pmu {
|
||||
compatible = "x-powers,axp806";
|
||||
reg = <0x36>;
|
||||
wakeup-source;
|
||||
linux,phandle = <0x127>;
|
||||
phandle = <0x127>;
|
||||
|
||||
standby_param {
|
||||
vcc-dram = <0x4>;
|
||||
linux,phandle = <0x128>;
|
||||
phandle = <0x128>;
|
||||
vcc-dram = <0x8>;
|
||||
};
|
||||
|
||||
regulators {
|
||||
|
||||
dcdc1 {
|
||||
regulator-name = "axp1530-dcdc1";
|
||||
regulator-min-microvolt = <0x7a120>;
|
||||
regulator-max-microvolt = <0x33e140>;
|
||||
regulator-step-delay-us = <0x19>;
|
||||
regulator-final-delay-us = <0x32>;
|
||||
reg_dcdc1: dcdca {
|
||||
regulator-name = "axp806-dcdca";
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <1520000>;
|
||||
regulator-step-delay-us = <25>;
|
||||
regulator-final-delay-us = <50>;
|
||||
regulator-always-on;
|
||||
linux,phandle = <0x129>;
|
||||
phandle = <0x129>;
|
||||
};
|
||||
|
||||
dcdc2 {
|
||||
regulator-name = "axp1530-dcdc2";
|
||||
regulator-min-microvolt = <0x7a120>;
|
||||
regulator-max-microvolt = <0x177fa0>;
|
||||
regulator-step-delay-us = <0x19>;
|
||||
regulator-final-delay-us = <0x32>;
|
||||
regulator-ramp-delay = <0xc8>;
|
||||
regulator-always-on;
|
||||
linux,phandle = <0xd6>;
|
||||
phandle = <0xd6>;
|
||||
reg_dcdc2: dcdcb {
|
||||
regulator-name = "axp806-dcdcb";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <2550000>;
|
||||
regulator-step-delay-us = <25>;
|
||||
regulator-final-delay-us = <50>;
|
||||
};
|
||||
|
||||
dcdc3 {
|
||||
regulator-name = "axp1530-dcdc3";
|
||||
regulator-min-microvolt = <0x16e360>;
|
||||
regulator-max-microvolt = <0x16e360>;
|
||||
regulator-step-delay-us = <0x19>;
|
||||
regulator-final-delay-us = <0x32>;
|
||||
reg_dcdc3: dcdcc {
|
||||
regulator-name = "axp806-dcdcc";
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <1520000>;
|
||||
regulator-step-delay-us = <25>;
|
||||
regulator-final-delay-us = <50>;
|
||||
regulator-always-on;
|
||||
linux,phandle = <0x12a>;
|
||||
phandle = <0x12a>;
|
||||
};
|
||||
|
||||
ldo1 {
|
||||
regulator-name = "axp1530-aldo1";
|
||||
regulator-min-microvolt = <0x1b7740>;
|
||||
regulator-max-microvolt = <0x1b7740>;
|
||||
regulator-step-delay-us = <0x19>;
|
||||
regulator-final-delay-us = <0x32>;
|
||||
reg_dcdc4: dcdcd {
|
||||
regulator-name = "axp806-dcdcd";
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-step-delay-us = <25>;
|
||||
regulator-final-delay-us = <50>;
|
||||
regulator-always-on;
|
||||
linux,phandle = <0x68>;
|
||||
phandle = <0x68>;
|
||||
};
|
||||
|
||||
ldo2 {
|
||||
regulator-name = "axp1530-dldo1";
|
||||
regulator-min-microvolt = <0x325aa0>;
|
||||
regulator-max-microvolt = <0x325aa0>;
|
||||
regulator-step-delay-us = <0x19>;
|
||||
regulator-final-delay-us = <0x32>;
|
||||
reg_dcdc5: dcdce {
|
||||
regulator-name = "axp806-dcdce";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-step-delay-us = <25>;
|
||||
regulator-final-delay-us = <50>;
|
||||
regulator-always-on;
|
||||
linux,phandle = <0x69>;
|
||||
phandle = <0x69>;
|
||||
};
|
||||
|
||||
reg_aldo1: aldo1 {
|
||||
regulator-name = "axp806-aldo1";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-step-delay-us = <25>;
|
||||
regulator-final-delay-us = <50>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_aldo2: aldo2 {
|
||||
regulator-name = "axp806-aldo2";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-step-delay-us = <25>;
|
||||
regulator-final-delay-us = <50>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_aldo3: aldo3 {
|
||||
regulator-name = "axp806-aldo3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-step-delay-us = <25>;
|
||||
regulator-final-delay-us = <50>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_bldo1: bldo1 {
|
||||
regulator-name = "axp806-bldo1";
|
||||
regulator-min-microvolt = <180000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-step-delay-us = <25>;
|
||||
regulator-final-delay-us = <50>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_bldo2: bldo2 {
|
||||
regulator-name = "axp806-bldo2";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1900000>;
|
||||
regulator-step-delay-us = <25>;
|
||||
regulator-final-delay-us = <50>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_bldo3: bldo3 {
|
||||
regulator-name = "axp806-bldo3";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1900000>;
|
||||
regulator-step-delay-us = <25>;
|
||||
regulator-final-delay-us = <50>;
|
||||
};
|
||||
|
||||
reg_bldo4: bldo4 {
|
||||
regulator-name = "axp806-bldo4";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1900000>;
|
||||
regulator-step-delay-us = <25>;
|
||||
regulator-final-delay-us = <50>;
|
||||
};
|
||||
|
||||
reg_cldo1: cldo1 {
|
||||
regulator-name = "axp806-cldo1";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-step-delay-us = <25>;
|
||||
regulator-final-delay-us = <50>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_cldo2: cldo2 {
|
||||
regulator-name = "axp806-cldo2";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <4200000>;
|
||||
regulator-step-delay-us = <25>;
|
||||
regulator-final-delay-us = <50>;
|
||||
};
|
||||
|
||||
reg_cldo3: cldo3 {
|
||||
regulator-name = "axp806-cldo3";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-step-delay-us = <25>;
|
||||
regulator-final-delay-us = <50>;
|
||||
};
|
||||
|
||||
reg_sw: sw {
|
||||
regulator-name = "axp806-sw";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -3384,8 +3451,6 @@
|
||||
ctl-spec-caps = <0x8>;
|
||||
vmmc-supply = <0x69>;
|
||||
vqmmc-supply = <0x68>;
|
||||
linux,phandle = <0x145>;
|
||||
phandle = <0x145>;
|
||||
};
|
||||
|
||||
sdmmc@04020000 {
|
||||
@@ -3402,24 +3467,18 @@
|
||||
max-frequency = <0x8f0d180>;
|
||||
bus-width = <0x4>;
|
||||
cd-gpios = <0x53 0x5 0x6 0x6 0x1 0x3 0xffffffff>;
|
||||
cap-sd-highspeed;
|
||||
//cap-sd-highspeed;
|
||||
cap-wait-while-busy;
|
||||
no-sdio;
|
||||
no-mmc;
|
||||
sunxi-power-save-mode;
|
||||
status = "okay";
|
||||
cd-used-24M;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-ddr50;
|
||||
sd-uhs-sdr104;
|
||||
//sd-uhs-sdr50;
|
||||
//sd-uhs-ddr50;
|
||||
//sd-uhs-sdr104;
|
||||
ctl-spec-caps = <0x8>;
|
||||
vmmc-supply = <0x69>;
|
||||
vqmmc33sw-supply = <0x69>;
|
||||
vdmmc33sw-supply = <0x69>;
|
||||
vqmmc18sw-supply = <0x68>;
|
||||
vdmmc18sw-supply = <0x68>;
|
||||
linux,phandle = <0x146>;
|
||||
phandle = <0x146>;
|
||||
//vdmmc-supply = <®_dcdc5>;
|
||||
};
|
||||
|
||||
sdmmc@04021000 {
|
||||
@@ -4434,13 +4493,6 @@
|
||||
dldo1_vol = <0xf4f24>;
|
||||
};
|
||||
|
||||
axp1530_power_sply {
|
||||
device_type = "axp1530_power_sply";
|
||||
dcdc2_vol = <0xf4628>;
|
||||
aldo1_vol = <0xf4948>;
|
||||
dldo1_vol = <0xf4f24>;
|
||||
};
|
||||
|
||||
axp806_power_sply {
|
||||
device_type = "axp806_power_sply";
|
||||
dcdce_vol = <0xf4f24>;
|
||||
@@ -4448,6 +4500,7 @@
|
||||
aldo1_vol = <0xf4f24>;
|
||||
bldo1_vol = <0xf4948>;
|
||||
bldo2_vol = <0xf4948>;
|
||||
cldo1_vol = <0xf4948>;
|
||||
};
|
||||
|
||||
card_boot {
|
||||
|
||||
@@ -5,7 +5,7 @@
|
||||
interrupt-parent = <0x1>;
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x2>;
|
||||
model = "Orange Pi 400";
|
||||
model = "Orange Pi Zero 2";
|
||||
compatible = "allwinner,h616", "arm,sun50iw9p1";
|
||||
|
||||
clocks {
|
||||
@@ -532,12 +532,10 @@
|
||||
phandle = <0xf3>;
|
||||
};
|
||||
|
||||
pwm {
|
||||
clk_pwm: pwm {
|
||||
#clock-cells = <0x0>;
|
||||
compatible = "allwinner,periph-clock";
|
||||
clock-output-names = "pwm";
|
||||
linux,phandle = <0x9b>;
|
||||
phandle = <0x9b>;
|
||||
};
|
||||
|
||||
iommu {
|
||||
@@ -1321,7 +1319,7 @@
|
||||
phandle = <0xd2>;
|
||||
};
|
||||
|
||||
/*s_cir0@0 {
|
||||
s_cir0@0 {
|
||||
allwinner,pins = "PH10";
|
||||
allwinner,function = "ir";
|
||||
allwinner,muxsel = <0x3>;
|
||||
@@ -1329,15 +1327,7 @@
|
||||
allwinner,pull = <0x1>;
|
||||
linux,phandle = <0x24>;
|
||||
phandle = <0x24>;
|
||||
};*/
|
||||
|
||||
hp_det: hp-det {
|
||||
allwinner,pins = "PH10";
|
||||
allwinner,function = "gpio_in";
|
||||
allwinner,muxsel = <0x0>;
|
||||
allwinner,drive = <0x2>;
|
||||
allwinner,pull = <0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
vdevice@0 {
|
||||
allwinner,pins = "PA1", "PA2";
|
||||
@@ -1381,7 +1371,7 @@
|
||||
};
|
||||
|
||||
uart2@0 {
|
||||
allwinner,pins = "PG15", "PG16", "PG17", "PG18";
|
||||
allwinner,pins = "PH5", "PH6", "PH7", "PH8";
|
||||
allwinner,pname = "uart2_tx", "uart2_rx", "uart2_rts", "uart2_cts";
|
||||
allwinner,function = "uart2";
|
||||
allwinner,muxsel = <0x2>;
|
||||
@@ -1392,7 +1382,7 @@
|
||||
};
|
||||
|
||||
uart2@1 {
|
||||
allwinner,pins = "PG15", "PG16", "PG17", "PG18";
|
||||
allwinner,pins = "PH5", "PH6", "PH7", "PH8";
|
||||
allwinner,function = "io_disabled";
|
||||
allwinner,muxsel = <0x7>;
|
||||
allwinner,drive = <0x1>;
|
||||
@@ -1486,10 +1476,10 @@
|
||||
};
|
||||
|
||||
twi1@0 {
|
||||
allwinner,pins = "PA2", "PA3";
|
||||
allwinner,pins = "PH0", "PH1";
|
||||
allwinner,pname = "twi1_scl", "twi1_sda";
|
||||
allwinner,function = "twi1";
|
||||
allwinner,muxsel = <0x4>;
|
||||
allwinner,muxsel = <0x5>;
|
||||
allwinner,drive = <0x1>;
|
||||
allwinner,pull = <0x0>;
|
||||
linux,phandle = <0x3f>;
|
||||
@@ -1497,7 +1487,7 @@
|
||||
};
|
||||
|
||||
twi1@1 {
|
||||
allwinner,pins = "PA2", "PA3";
|
||||
allwinner,pins = "PH0", "PH1";
|
||||
allwinner,function = "io_disabled";
|
||||
allwinner,muxsel = <0x7>;
|
||||
allwinner,drive = <0x1>;
|
||||
@@ -1549,7 +1539,7 @@
|
||||
};
|
||||
|
||||
twi4@0 {
|
||||
allwinner,pins = "PG15", "PG16";
|
||||
allwinner,pins = "PH6", "PH7";
|
||||
allwinner,pname = "twi4_scl", "twi4_sda";
|
||||
allwinner,function = "twi4";
|
||||
allwinner,muxsel = <0x5>;
|
||||
@@ -1560,7 +1550,7 @@
|
||||
};
|
||||
|
||||
twi4@1 {
|
||||
allwinner,pins = "PG15", "PG16";
|
||||
allwinner,pins = "PH6", "PH7";
|
||||
allwinner,function = "io_disabled";
|
||||
allwinner,muxsel = <0x7>;
|
||||
allwinner,drive = <0x1>;
|
||||
@@ -1817,7 +1807,7 @@
|
||||
|
||||
ahub_daudio2@0 {
|
||||
allwinner,pins = "PG11", "PG12", "PG13", "PG14";
|
||||
allwinner,function = "h_i2s2";
|
||||
allwinner,function = "h_pcm2";
|
||||
allwinner,muxsel = <0x2>;
|
||||
allwinner,drive = <0x1>;
|
||||
allwinner,pull = <0x0>;
|
||||
@@ -1837,7 +1827,7 @@
|
||||
|
||||
ahub_daudio3@0 {
|
||||
allwinner,pins = "PH5", "PH6", "PH7", "PH8", "PH9";
|
||||
allwinner,function = "h_i2s3";
|
||||
allwinner,function = "h_pcm3";
|
||||
allwinner,muxsel = <0x3>;
|
||||
allwinner,drive = <0x1>;
|
||||
allwinner,pull = <0x0>;
|
||||
@@ -2187,26 +2177,94 @@
|
||||
phandle = <0x9a>;
|
||||
};
|
||||
|
||||
pwm5@0 {
|
||||
pwm1_pin: pwm1-pin {
|
||||
allwinner,pins = "PH3";
|
||||
allwinner,function = "pwm1";
|
||||
allwinner,muxsel = <0x4>;
|
||||
allwinner,drive = <0xffffffff>;
|
||||
allwinner,pull = <0x0>;
|
||||
allwinner,data = <0xffffffff>;
|
||||
};
|
||||
|
||||
pwm1_pin_sleep: pwm1-pin-sleep {
|
||||
allwinner,pins = "PH3";
|
||||
allwinner,function = "io_disabled";
|
||||
allwinner,muxsel = <0x7>;
|
||||
allwinner,drive = <0xffffffff>;
|
||||
allwinner,pull = <0x0>;
|
||||
allwinner,data = <0xffffffff>;
|
||||
};
|
||||
|
||||
pwm2_pin: pwm2-pin {
|
||||
allwinner,pins = "PH2";
|
||||
allwinner,function = "pwm2";
|
||||
allwinner,muxsel = <0x4>;
|
||||
allwinner,drive = <0xffffffff>;
|
||||
allwinner,pull = <0x0>;
|
||||
allwinner,data = <0xffffffff>;
|
||||
};
|
||||
|
||||
pwm2_pin_sleep: pwm2-pin-sleep {
|
||||
allwinner,pins = "PH2";
|
||||
allwinner,function = "io_disabled";
|
||||
allwinner,muxsel = <0x7>;
|
||||
allwinner,drive = <0xffffffff>;
|
||||
allwinner,pull = <0x0>;
|
||||
allwinner,data = <0xffffffff>;
|
||||
};
|
||||
|
||||
pwm3_pin: pwm3-pin {
|
||||
allwinner,pins = "PH0";
|
||||
allwinner,function = "pwm3";
|
||||
allwinner,muxsel = <0x4>;
|
||||
allwinner,drive = <0xffffffff>;
|
||||
allwinner,pull = <0x0>;
|
||||
allwinner,data = <0xffffffff>;
|
||||
};
|
||||
|
||||
pwm3_pin_sleep: pwm3-pin-sleep {
|
||||
allwinner,pins = "PH0";
|
||||
allwinner,function = "io_disabled";
|
||||
allwinner,muxsel = <0x7>;
|
||||
allwinner,drive = <0xffffffff>;
|
||||
allwinner,pull = <0x0>;
|
||||
allwinner,data = <0xffffffff>;
|
||||
};
|
||||
|
||||
pwm4_pin: pwm4-pin {
|
||||
allwinner,pins = "PH1";
|
||||
allwinner,function = "pwm4";
|
||||
allwinner,muxsel = <0x4>;
|
||||
allwinner,drive = <0xffffffff>;
|
||||
allwinner,pull = <0x0>;
|
||||
allwinner,data = <0xffffffff>;
|
||||
};
|
||||
|
||||
pwm4_pin_sleep: pwm4-pin-sleep {
|
||||
allwinner,pins = "PH1";
|
||||
allwinner,function = "io_disabled";
|
||||
allwinner,muxsel = <0x7>;
|
||||
allwinner,drive = <0xffffffff>;
|
||||
allwinner,pull = <0x0>;
|
||||
allwinner,data = <0xffffffff>;
|
||||
};
|
||||
|
||||
pwm5_pin: pwm5-pin {
|
||||
allwinner,pins = "PA12";
|
||||
allwinner,function = "pwm5";
|
||||
allwinner,muxsel = <0x2>;
|
||||
allwinner,drive = <0xffffffff>;
|
||||
allwinner,pull = <0x0>;
|
||||
allwinner,data = <0xffffffff>;
|
||||
linux,phandle = <0xa2>;
|
||||
phandle = <0xa2>;
|
||||
};
|
||||
|
||||
pwm5@1 {
|
||||
pwm5_pin_sleep: pwm5_pin_sleep {
|
||||
allwinner,pins = "PA12";
|
||||
allwinner,function = "io_disabled";
|
||||
allwinner,muxsel = <0x7>;
|
||||
allwinner,drive = <0xffffffff>;
|
||||
allwinner,pull = <0x0>;
|
||||
allwinner,data = <0xffffffff>;
|
||||
linux,phandle = <0xa3>;
|
||||
phandle = <0xa3>;
|
||||
};
|
||||
|
||||
standby@0 {
|
||||
@@ -2429,7 +2487,7 @@
|
||||
clocks = <0x9 0x25>;
|
||||
supply = "vcc-pl";
|
||||
supply_vol = "3300000";
|
||||
status = "disabled";
|
||||
status = "okay";
|
||||
s_cir0_used = <0x1>;
|
||||
ir_power_key_code0 = <0x40>;
|
||||
ir_addr_code0 = <0xfe01>;
|
||||
@@ -2507,7 +2565,7 @@
|
||||
phandle = <0x11a>;
|
||||
};
|
||||
|
||||
uart@05000000 {
|
||||
uart0: uart@05000000 {
|
||||
compatible = "allwinner,sun50i-uart";
|
||||
device_type = "uart0";
|
||||
reg = <0x0 0x5000000 0x0 0x400>;
|
||||
@@ -2523,7 +2581,7 @@
|
||||
pinctrl-0 = <0x187>;
|
||||
};
|
||||
|
||||
uart@05000400 {
|
||||
uart1: uart@05000400 {
|
||||
compatible = "allwinner,sun50i-uart";
|
||||
device_type = "uart1";
|
||||
reg = <0x0 0x5000400 0x0 0x400>;
|
||||
@@ -2539,7 +2597,7 @@
|
||||
phandle = <0x11c>;
|
||||
};
|
||||
|
||||
uart@05000800 {
|
||||
uart2: uart@05000800 {
|
||||
compatible = "allwinner,sun50i-uart";
|
||||
device_type = "uart2";
|
||||
reg = <0x0 0x5000800 0x0 0x400>;
|
||||
@@ -2549,13 +2607,11 @@
|
||||
pinctrl-0 = <0x30>;
|
||||
pinctrl-1 = <0x31>;
|
||||
uart2_port = <0x2>;
|
||||
uart2_type = <0x4>;
|
||||
uart2_type = <0x2>;
|
||||
status = "disabled";
|
||||
linux,phandle = <0x11d>;
|
||||
phandle = <0x11d>;
|
||||
};
|
||||
|
||||
uart@05000c00 {
|
||||
uart3: uart@05000c00 {
|
||||
compatible = "allwinner,sun50i-uart";
|
||||
device_type = "uart3";
|
||||
reg = <0x0 0x5000c00 0x0 0x400>;
|
||||
@@ -2571,7 +2627,7 @@
|
||||
phandle = <0x11e>;
|
||||
};
|
||||
|
||||
uart@05001000 {
|
||||
uart4: uart@05001000 {
|
||||
compatible = "allwinner,sun50i-uart";
|
||||
device_type = "uart4";
|
||||
reg = <0x0 0x5001000 0x0 0x400>;
|
||||
@@ -2587,7 +2643,7 @@
|
||||
phandle = <0x11f>;
|
||||
};
|
||||
|
||||
uart@05001400 {
|
||||
uart5: uart@05001400 {
|
||||
compatible = "allwinner,sun50i-uart";
|
||||
device_type = "uart5";
|
||||
reg = <0x0 0x5001400 0x0 0x400>;
|
||||
@@ -2598,12 +2654,12 @@
|
||||
pinctrl-1 = <0x3a>;
|
||||
uart5_port = <0x5>;
|
||||
uart5_type = <0x2>;
|
||||
status = "disabled";
|
||||
status = "okay";
|
||||
linux,phandle = <0x120>;
|
||||
phandle = <0x120>;
|
||||
};
|
||||
|
||||
twi@0x05002000 {
|
||||
i2c0: twi@0x05002000 {
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
compatible = "allwinner,sun50i-twi";
|
||||
@@ -2620,7 +2676,7 @@
|
||||
phandle = <0x121>;
|
||||
};
|
||||
|
||||
twi@0x05002400 {
|
||||
i2c1: twi@0x05002400 {
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
compatible = "allwinner,sun50i-twi";
|
||||
@@ -2637,7 +2693,24 @@
|
||||
phandle = <0x122>;
|
||||
};
|
||||
|
||||
twi@0x05002c00 {
|
||||
i2c2: twi@0x05002800 {
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
compatible = "allwinner,sun50i-twi";
|
||||
device_type = "twi2";
|
||||
reg = <0x0 0x5002800 0x0 0x400>;
|
||||
interrupts = <0x0 0x8 0x4>;
|
||||
clocks = <0x41>;
|
||||
clock-frequency = <0x30d40>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <0x42>;
|
||||
pinctrl-1 = <0x43>;
|
||||
status = "disabled";
|
||||
linux,phandle = <0x123>;
|
||||
phandle = <0x123>;
|
||||
};
|
||||
|
||||
i2c3: twi@0x05002c00 {
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
compatible = "allwinner,sun50i-twi";
|
||||
@@ -2649,12 +2722,12 @@
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <0x45>;
|
||||
pinctrl-1 = <0x46>;
|
||||
status = "disabled";
|
||||
status = "okay";
|
||||
linux,phandle = <0x124>;
|
||||
phandle = <0x124>;
|
||||
};
|
||||
|
||||
twi@0x05003000 {
|
||||
i2c4: twi@0x05003000 {
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
compatible = "allwinner,sun50i-twi";
|
||||
@@ -2667,11 +2740,9 @@
|
||||
pinctrl-0 = <0x48>;
|
||||
pinctrl-1 = <0x49>;
|
||||
status = "disabled";
|
||||
linux,phandle = <0x125>;
|
||||
phandle = <0x125>;
|
||||
};
|
||||
|
||||
twi@0x07081400 {
|
||||
i2c5: twi@0x07081400 {
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
compatible = "allwinner,sun50i-twi";
|
||||
@@ -2685,22 +2756,14 @@
|
||||
pinctrl-1 = <0x4c>;
|
||||
status = "okay";
|
||||
no_suspend = <0x1>;
|
||||
linux,phandle = <0x126>;
|
||||
phandle = <0x126>;
|
||||
|
||||
pmu {
|
||||
compatible = "x-powers,axp1530";
|
||||
//compatible = "x-powers,axp806";
|
||||
reg = <0x36>;
|
||||
wakeup-source;
|
||||
linux,phandle = <0x127>;
|
||||
phandle = <0x127>;
|
||||
|
||||
interrupt-parent = <0x53>;
|
||||
interrupts = <0x8 0x6 0x8>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
standby_param {
|
||||
vcc-dram = <0x4>;
|
||||
linux,phandle = <0x128>;
|
||||
@@ -2764,84 +2827,21 @@
|
||||
linux,phandle = <0x69>;
|
||||
phandle = <0x69>;
|
||||
};
|
||||
|
||||
/* cldo2 {
|
||||
regulator-name = "axp806-cldo2";
|
||||
regulator-min-microvolt = <0x00325aa0>;
|
||||
regulator-max-microvolt = <0x00325aa0>;
|
||||
regulator-step-delay-us = <0x00000019>;
|
||||
regulator-final-delay-us = <0x00000032>;
|
||||
regulator-always-on;
|
||||
linux,phandle = <0x579>;
|
||||
phandle = <0x579>;
|
||||
};*/
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
twi@0x05002800 {
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
compatible = "allwinner,sun50i-twi";
|
||||
device_type = "twi2";
|
||||
reg = <0x0 0x5002800 0x0 0x400>;
|
||||
interrupts = <0x0 0x8 0x4>;
|
||||
clocks = <0x41>;
|
||||
clock-frequency = <0x61A80>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <0x42>;
|
||||
pinctrl-1 = <0x43>;
|
||||
status = "okay";
|
||||
linux,phandle = <0x123>;
|
||||
phandle = <0x123>;
|
||||
|
||||
pca9555: pca9555@20{
|
||||
compatible = "nxp,pca9555";
|
||||
interrupt-parent = <0x53>;
|
||||
interrupts = <0x7 0x4 0x4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x20>;
|
||||
};
|
||||
|
||||
es8316: es8316@11 {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "everest,es8316";
|
||||
//pinctrl-names = "default";
|
||||
//pinctrl-0 = <&hp_det>;
|
||||
//hp-det-gpio = <0x53 7 10 0x6 1 0xffffffff 0xffffffff>;
|
||||
reg = <0x11>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
i2c-gpio@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
compatible = "i2c-gpio";
|
||||
gpios = <&pca9555 2 3 /* sda */
|
||||
&pca9555 3 3 /* scl */ >;
|
||||
|
||||
i2c-gpio,delay-us = <2>;
|
||||
|
||||
/* status = "okay"; */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbc0@0 {
|
||||
device_type = "usbc0";
|
||||
compatible = "allwinner,sunxi-otg-manager";
|
||||
usb_port_type = <0x1>;
|
||||
usb_detect_type = <0x0>;
|
||||
usb_port_type = <0x0>;
|
||||
usb_detect_type = <0x1>;
|
||||
usb_id_gpio;
|
||||
usb_det_vbus_gpio;
|
||||
usb_drv_vbus_gpio;
|
||||
usb_host_init_state = <0x1>;
|
||||
usb_host_init_state = <0x0>;
|
||||
usb_regulator_io = "nocare";
|
||||
usb_wakeup_suspend = <0x1>;
|
||||
usb_wakeup_suspend = <0x2>;
|
||||
usb_luns = <0x3>;
|
||||
usb_serial_unique = <0x0>;
|
||||
usb_serial_number = "20080411";
|
||||
@@ -3034,8 +3034,7 @@
|
||||
linein_gain = <0x3>;
|
||||
digital_vol = <0x0>;
|
||||
lineout_vol = <0x1a>;
|
||||
gpio-spk = <&pca9555 0 1>;
|
||||
pa_ctl_level = <0x0>;
|
||||
pa_ctl_level = <0x1>;
|
||||
pa_msleep_time = <0x64>;
|
||||
ramp_func_used = <0x1>;
|
||||
avcc-supply = <0x68>;
|
||||
@@ -3080,6 +3079,15 @@
|
||||
phandle = <0x7b>;
|
||||
};
|
||||
|
||||
cpudai3-controller@0x05097000 {
|
||||
compatible = "allwinner,sunxi-ahub-cpudai";
|
||||
reg = <0x0 0x5097000 0x0 0xadf>;
|
||||
id = <0x3>;
|
||||
status = "okay";
|
||||
linux,phandle = <0x139>;
|
||||
phandle = <0x139>;
|
||||
};
|
||||
|
||||
ahub_codec@0x05097000 {
|
||||
compatible = "allwinner,sunxi-ahub";
|
||||
reg = <0x0 0x5097000 0x0 0xadf>;
|
||||
@@ -3155,9 +3163,8 @@
|
||||
phandle = <0x73>;
|
||||
};
|
||||
|
||||
ahub_daudio3:ahub_daudio3@0x05097000 {
|
||||
ahub_daudio3@0x05097000 {
|
||||
compatible = "allwinner,sunxi-ahub-daudio";
|
||||
#sound-dai-cells = <0>;
|
||||
reg = <0x0 0x5097000 0x0 0xadf>;
|
||||
clocks = <0x60 0x7 0x6a>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
@@ -3165,7 +3172,7 @@
|
||||
pinctrl-1 = <0x70>;
|
||||
tdm_num = <0x3>;
|
||||
device_type = "ahub_daudio3";
|
||||
status = "okay";
|
||||
status = "disabled";
|
||||
pinconfig = <0x1>;
|
||||
frametype = <0x0>;
|
||||
pcm_lrck_period = <0x20>;
|
||||
@@ -3207,12 +3214,10 @@
|
||||
};
|
||||
|
||||
sound@3 {
|
||||
compatible = "allwinner,sunxi-rt5651-sound";
|
||||
compatible = "allwinner,sunxi-daudio3-machine";
|
||||
sunxi,cpudai-controller = <0x74>;
|
||||
device_type = "snddaudio3";
|
||||
status = "disabled";
|
||||
sunxi,snddaudio-codec = "rt5651.2-001a";
|
||||
sunxi,snddaudio-codec-dai = "rt5651-aif1";
|
||||
linux,phandle = <0x13d>;
|
||||
phandle = <0x13d>;
|
||||
};
|
||||
@@ -3271,10 +3276,19 @@
|
||||
pinctrl-1 = <0x80>;
|
||||
spi0_cs_number = <0x1>;
|
||||
spi0_cs_bitmap = <0x1>;
|
||||
status = "disabled";
|
||||
status = "okay";
|
||||
spi_slave_mode = <0x0>;
|
||||
linux,phandle = <0x142>;
|
||||
phandle = <0x142>;
|
||||
|
||||
spi_board0 {
|
||||
device_type = "spi_board0";
|
||||
compatible = "rohm,dh2228fv";
|
||||
spi-max-frequency = <0x1000000>;
|
||||
reg = <0x0>;
|
||||
spi-rx-bus-width = <0x1>;
|
||||
spi-tx-bus-width = <0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
spi@05011000 {
|
||||
@@ -3291,33 +3305,19 @@
|
||||
pinctrl-1 = <0x84>;
|
||||
spi1_cs_number = <0x2>;
|
||||
spi1_cs_bitmap = <0x2>;
|
||||
status = "disabled";
|
||||
status = "okay";
|
||||
spi_slave_mode = <0x0>;
|
||||
linux,phandle = <0x143>;
|
||||
phandle = <0x143>;
|
||||
};
|
||||
|
||||
spi-gpio@0 {
|
||||
compatible = "spi-gpio";
|
||||
#address-cells = <0x1>;
|
||||
|
||||
gpio-sck = <&pca9555 4 0>;
|
||||
gpio-miso = <&pca9555 5 0>;
|
||||
gpio-mosi = <&pca9555 6 0>;
|
||||
cs-gpios = <&pca9555 7 0>;
|
||||
num-chipselects = <1>;
|
||||
status = "disabled";
|
||||
|
||||
device_0@0 {
|
||||
compatible = "rohm,dh2228fv";
|
||||
spi-max-frequency = <500000>;
|
||||
reg = <0x0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
spi-rx-bus-width = <0x1>;
|
||||
spi-tx-bus-width = <0x1>;
|
||||
bits-per-word = <8>;
|
||||
};
|
||||
spi_board1 {
|
||||
device_type = "spi_board1";
|
||||
compatible = "rohm,dh2228fv";
|
||||
spi-max-frequency = <0x1000000>;
|
||||
reg = <0x1>;
|
||||
spi-rx-bus-width = <0x1>;
|
||||
spi-tx-bus-width = <0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie@0x05400000 {
|
||||
@@ -3334,45 +3334,11 @@
|
||||
#interrupt-cells = <0x1>;
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x0>;
|
||||
interrupt-map = <0x0 0x0 0x0 0x1 0x85 0x0 0x7f 0x4>;
|
||||
status = "disabled";
|
||||
status = "okay";
|
||||
linux,phandle = <0x144>;
|
||||
phandle = <0x144>;
|
||||
};
|
||||
|
||||
sdmmc@04020000 {
|
||||
compatible = "allwinner,sunxi-mmc-v4p1x";
|
||||
device_type = "sdc0";
|
||||
reg = <0x0 0x4020000 0x0 0x1000>;
|
||||
interrupts = <0x0 0x23 0x4>;
|
||||
clocks = <0x9 0x86 0x8d 0x8e 0x8f>;
|
||||
clock-names = "osc24m", "pll_periph", "mmc", "ahb", "rst";
|
||||
pinctrl-names = "default", "sleep", "uart_jtag";
|
||||
pinctrl-0 = <0x90>;
|
||||
pinctrl-1 = <0x91>;
|
||||
pinctrl-2 = <0x92>;
|
||||
max-frequency = <0x8f0d180>;
|
||||
bus-width = <0x4>;
|
||||
cd-gpios = <0x53 0x5 0x6 0x6 0x1 0x3 0xffffffff>;
|
||||
cap-sd-highspeed;
|
||||
cap-wait-while-busy;
|
||||
no-sdio;
|
||||
no-mmc;
|
||||
sunxi-power-save-mode;
|
||||
status = "okay";
|
||||
cd-used-24M;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-ddr50;
|
||||
sd-uhs-sdr104;
|
||||
ctl-spec-caps = <0x8>;
|
||||
vmmc-supply;
|
||||
vqmmc33sw-supply;
|
||||
vdmmc33sw-supply;
|
||||
vqmmc18sw-supply;
|
||||
vdmmc18sw-supply;
|
||||
linux,phandle = <0x146>;
|
||||
phandle = <0x146>;
|
||||
};
|
||||
|
||||
sdmmc@04022000 {
|
||||
compatible = "allwinner,sunxi-mmc-v4p6x";
|
||||
device_type = "sdc2";
|
||||
@@ -3389,12 +3355,10 @@
|
||||
mmc-cache-ctrl;
|
||||
non-removable;
|
||||
max-frequency = <0x5f5e100>;
|
||||
//max-frequency = <0x2FAF080>;
|
||||
cap-erase;
|
||||
mmc-high-capacity-erase-size;
|
||||
no-sdio;
|
||||
no-sd;
|
||||
|
||||
sdc_tm4_sm0_freq0 = <0x0>;
|
||||
sdc_tm4_sm0_freq1 = <0x0>;
|
||||
sdc_tm4_sm1_freq0 = <0x0>;
|
||||
@@ -3405,29 +3369,43 @@
|
||||
sdc_tm4_sm3_freq1 = <0x5>;
|
||||
sdc_tm4_sm4_freq0 = <0x50000>;
|
||||
sdc_tm4_sm4_freq1 = <0x4>;
|
||||
|
||||
//sdc_tm4_sm0_freq0 = <0xffffffff>;
|
||||
//sdc_tm4_sm0_freq1 = <0xffffffff>;
|
||||
//sdc_tm4_sm1_freq0 = <0xff17ffff>;
|
||||
//sdc_tm4_sm1_freq1 = <0xffffffff>;
|
||||
//sdc_tm4_sm2_freq0 = <0xff0d14ff>;
|
||||
//sdc_tm4_sm2_freq1 = <0xffffffff>;
|
||||
//sdc_tm4_sm3_freq0 = <0x1414ffff>;
|
||||
//sdc_tm4_sm3_freq1 = <0xffff1d19>;
|
||||
//sdc_tm4_sm4_freq0 = <0x0f18ffff>;
|
||||
//sdc_tm4_sm4_freq1 = <0xffffff07>;
|
||||
|
||||
status = "okay";
|
||||
status = "disabled";
|
||||
mmc-ddr-1_8v;
|
||||
mmc-hs200-1_8v;
|
||||
mmc-hs400-1_8v;
|
||||
sunxi-power-save-mode;
|
||||
sunxi-dis-signal-vol-sw;
|
||||
ctl-spec-caps = <0x8>;
|
||||
vmmc-supply;
|
||||
vqmmc-supply;
|
||||
linux,phandle = <0x145>;
|
||||
phandle = <0x145>;
|
||||
vmmc-supply = <0x69>;
|
||||
vqmmc-supply = <0x68>;
|
||||
};
|
||||
|
||||
sdmmc@04020000 {
|
||||
compatible = "allwinner,sunxi-mmc-v4p1x";
|
||||
device_type = "sdc0";
|
||||
reg = <0x0 0x4020000 0x0 0x1000>;
|
||||
interrupts = <0x0 0x23 0x4>;
|
||||
clocks = <0x9 0x86 0x8d 0x8e 0x8f>;
|
||||
clock-names = "osc24m", "pll_periph", "mmc", "ahb", "rst";
|
||||
pinctrl-names = "default", "sleep", "uart_jtag";
|
||||
pinctrl-0 = <0x90>;
|
||||
pinctrl-1 = <0x91>;
|
||||
pinctrl-2 = <0x92>;
|
||||
max-frequency = <0x8f0d180>;
|
||||
bus-width = <0x4>;
|
||||
cd-gpios = <0x53 0x5 0x6 0x6 0x1 0x3 0xffffffff>;
|
||||
//cap-sd-highspeed;
|
||||
cap-wait-while-busy;
|
||||
no-sdio;
|
||||
no-mmc;
|
||||
sunxi-power-save-mode;
|
||||
status = "okay";
|
||||
cd-used-24M;
|
||||
//sd-uhs-sdr50;
|
||||
//sd-uhs-ddr50;
|
||||
//sd-uhs-sdr104;
|
||||
ctl-spec-caps = <0x8>;
|
||||
//vdmmc-supply = <®_dcdc5>;
|
||||
};
|
||||
|
||||
sdmmc@04021000 {
|
||||
@@ -3533,7 +3511,7 @@
|
||||
lcd0@01c0c000 {
|
||||
compatible = "allwinner,sunxi-lcd0";
|
||||
pinctrl-names = "active", "sleep";
|
||||
status = "okay";
|
||||
status = "disabled";
|
||||
lcd_used = <0x0>;
|
||||
lcd_driver_name = "default_lcd";
|
||||
lcd_backlight = <0x32>;
|
||||
@@ -3606,10 +3584,6 @@
|
||||
hdmi_skip_bootedid = <0x1>;
|
||||
ddc_en_io_ctrl = <0x0>;
|
||||
power_io_ctrl = <0x0>;
|
||||
hdmi_det_io = <0x53 0x8 0x10 0x0 0x0 0x0 0x0>;
|
||||
vga_det_io = <0x53 0x6 0x13 0x0 0x0 0x0 0x0>;
|
||||
hhpd_set_io = <0x53 0x2 0x3 0x1 0x0 0x0 0x0>;
|
||||
vga_reset_io = <0x53 0x2 0x4 0x1 0x0 0x0 0x0>;
|
||||
linux,phandle = <0x14d>;
|
||||
phandle = <0x14d>;
|
||||
};
|
||||
@@ -3637,63 +3611,57 @@
|
||||
pwm@0300a000 {
|
||||
compatible = "allwinner,sunxi-pwm";
|
||||
reg = <0x0 0x300a000 0x0 0x3ff>;
|
||||
clocks = <0x9b>;
|
||||
clocks = <&clk_pwm>;
|
||||
pwm-number = <0x6>;
|
||||
pwm-base = <0x0>;
|
||||
pwms = <0x9c 0x9d 0x9e 0x9f 0xa0 0xa1>;
|
||||
linux,phandle = <0x150>;
|
||||
phandle = <0x150>;
|
||||
pwms = <&pwm0>, <&pwm1>,<&pwm2>, <&pwm3>, <&pwm4>, <&pwm5>;
|
||||
};
|
||||
|
||||
pwm0@0300a000 {
|
||||
pwm0: pwm0@0300a000 {
|
||||
compatible = "allwinner,sunxi-pwm0";
|
||||
pinctrl-names = "active", "sleep";
|
||||
reg_base = <0x300a000>;
|
||||
linux,phandle = <0x9c>;
|
||||
phandle = <0x9c>;
|
||||
};
|
||||
|
||||
pwm1@0300a000 {
|
||||
pwm1: pwm1@0300a000 {
|
||||
compatible = "allwinner,sunxi-pwm1";
|
||||
pinctrl-names = "active", "sleep";
|
||||
pinctrl-0 = <&pwm1_pin>;
|
||||
pinctrl-1 = <&pwm1_pin_sleep>;
|
||||
reg_base = <0x300a000>;
|
||||
linux,phandle = <0x9d>;
|
||||
phandle = <0x9d>;
|
||||
};
|
||||
|
||||
pwm2@0300a000 {
|
||||
pwm2: pwm2@0300a000 {
|
||||
compatible = "allwinner,sunxi-pwm2";
|
||||
pinctrl-names = "active", "sleep";
|
||||
pinctrl-0 = <&pwm2_pin>;
|
||||
pinctrl-1 = <&pwm2_pin_sleep>;
|
||||
reg_base = <0x300a000>;
|
||||
linux,phandle = <0x9e>;
|
||||
phandle = <0x9e>;
|
||||
};
|
||||
|
||||
pwm3@0300a000 {
|
||||
pwm3: pwm3@0300a000 {
|
||||
compatible = "allwinner,sunxi-pwm3";
|
||||
pinctrl-names = "active", "sleep";
|
||||
pinctrl-0 = <&pwm3_pin>;
|
||||
pinctrl-1 = <&pwm3_pin_sleep>;
|
||||
reg_base = <0x300a000>;
|
||||
linux,phandle = <0x9f>;
|
||||
phandle = <0x9f>;
|
||||
};
|
||||
|
||||
pwm4@0300a000 {
|
||||
pwm4: pwm4@0300a000 {
|
||||
compatible = "allwinner,sunxi-pwm4";
|
||||
pinctrl-names = "active", "sleep";
|
||||
pinctrl-0 = <&pwm4_pin>;
|
||||
pinctrl-1 = <&pwm4_pin_sleep>;
|
||||
reg_base = <0x300a000>;
|
||||
linux,phandle = <0xa0>;
|
||||
phandle = <0xa0>;
|
||||
};
|
||||
|
||||
pwm5@0300a000 {
|
||||
pwm5: pwm5@0300a000 {
|
||||
compatible = "allwinner,sunxi-pwm5";
|
||||
pinctrl-names = "active", "sleep";
|
||||
reg_base = <0x300a000>;
|
||||
pinctrl-0 = <0xa2>;
|
||||
pinctrl-1 = <0xa3>;
|
||||
pinctrl-0 = <&pwm5_pin>;
|
||||
pinctrl-1 = <&pwm5_pin_sleep>;
|
||||
clk_bypass_output = <0x1>;
|
||||
linux,phandle = <0xa1>;
|
||||
phandle = <0xa1>;
|
||||
};
|
||||
|
||||
ac200 {
|
||||
@@ -4180,6 +4148,8 @@
|
||||
clock-names = "bus";
|
||||
nvmem-cells = <0xc4>;
|
||||
nvmem-cell-names = "calibration";
|
||||
nvmem-names = "sid";
|
||||
nvmem = <&sunxi_sid>;
|
||||
#thermal-sensor-cells = <0x1>;
|
||||
linux,phandle = <0xc5>;
|
||||
phandle = <0xc5>;
|
||||
@@ -4295,7 +4265,7 @@
|
||||
reg = <0x0 0x5070800 0x0 0x400>;
|
||||
clocks = <0xca>;
|
||||
interrupts = <0x0 0x14 0x0>;
|
||||
status = "disabled";
|
||||
status = "okay";
|
||||
key_cnt = <0x5>;
|
||||
key0 = <0xd2 0x73>;
|
||||
key1 = <0x19a 0x72>;
|
||||
@@ -4375,7 +4345,7 @@
|
||||
clocks = <0x1b>;
|
||||
bt_power;
|
||||
bt_io_regulator;
|
||||
//bt_rst_n = <0x53 0x6 0x13 0x1 0xffffffff 0xffffffff 0x0>;
|
||||
bt_rst_n = <0x53 0x6 0x13 0x1 0xffffffff 0xffffffff 0x0>;
|
||||
status = "okay";
|
||||
linux,phandle = <0x177>;
|
||||
phandle = <0x177>;
|
||||
@@ -4403,34 +4373,25 @@
|
||||
|
||||
gpio_para {
|
||||
device_type = "gpio_para";
|
||||
status = "disabled";
|
||||
status = "okay";
|
||||
compatible = "allwinner,sunxi-init-gpio";
|
||||
gpio_num = <0x0>;
|
||||
//gpio_pin_1 = <0x53 8 16 0x1 1 0xffffffff 0xffffffff>; /* PI16 for USBC0 VBUS */
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
compatible = "gpio-leds";
|
||||
|
||||
power {
|
||||
label = "power_led";
|
||||
gpios = <0x53 0x2 0x7 0x1 0xffffffff 0xffffffff 0x0>; /* PC7 */
|
||||
default-state = "on";
|
||||
};
|
||||
power {
|
||||
label = "orangepi:red:power";
|
||||
gpios = <0x53 0x2 0xc 0x1 0xffffffff 0xffffffff 0x0>; /* PC12 */
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
capslock {
|
||||
label = "caps_led";
|
||||
gpios = <0x53 0x2 0x2 0x1 0xffffffff 0xffffffff 0x0>; // PC2
|
||||
linux,default-trigger = "kbd-capslock";
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
numlock {
|
||||
label = "num_led";
|
||||
gpios = <0x53 0x2 0xc 0x1 0xffffffff 0xffffffff 0x0>; // PC12
|
||||
linux,default-trigger = "kbd-numlock";
|
||||
default-state = "off";
|
||||
};
|
||||
status {
|
||||
label = "orangepi:green:status";
|
||||
gpios = <0x53 0x2 0xd 0x1 0xffffffff 0xffffffff 0x0>; /* PC13 */
|
||||
default-state = "on";
|
||||
};
|
||||
};
|
||||
|
||||
product {
|
||||
@@ -4459,9 +4420,6 @@
|
||||
dcdc2_vol = <0xf4628>;
|
||||
aldo1_vol = <0xf4948>;
|
||||
dldo1_vol = <0xf4f24>;
|
||||
bldo2_vol = <0xf4948>;
|
||||
cldo2_vol = <0xf4f24>;
|
||||
cldo3_vol = <0xf4948>;
|
||||
};
|
||||
|
||||
axp1530_power_sply {
|
||||
@@ -4469,19 +4427,14 @@
|
||||
dcdc2_vol = <0xf4628>;
|
||||
aldo1_vol = <0xf4948>;
|
||||
dldo1_vol = <0xf4f24>;
|
||||
bldo2_vol = <0xf4948>;
|
||||
cldo2_vol = <0xf4f24>;
|
||||
cldo3_vol = <0xf4948>;
|
||||
};
|
||||
|
||||
axp806_power_sply {
|
||||
device_type = "axp806_power_sply";
|
||||
dcdce_vol = <0xf4f24>;
|
||||
dcdcd_vol = <0xf4786>;
|
||||
aldo1_vol = <0xf4f24>;
|
||||
bldo1_vol = <0xf4948>;
|
||||
bldo2_vol = <0xf4948>;
|
||||
cldo2_vol = <0xf4f24>;
|
||||
cldo3_vol = <0xf4948>;
|
||||
};
|
||||
|
||||
card_boot {
|
||||
@@ -4493,14 +4446,13 @@
|
||||
boot_init_gpio {
|
||||
device_type = "boot_init_gpio";
|
||||
status = "okay";
|
||||
gpio0 = <0x53 0x2 12 0x1 0xffffffff 0xffffffff 0x0>;
|
||||
gpio1 = <0x53 0x2 0x2 0x1 0xffffffff 0xffffffff 0x0>;
|
||||
gpio2 = <0x53 0x2 0x7 0x1 0xffffffff 0xffffffff 0x1>;
|
||||
gpio0 = <0x53 0x2 0xc 0x1 0xffffffff 0xffffffff 0x1>;
|
||||
gpio1 = <0x53 0x2 0xd 0x1 0xffffffff 0xffffffff 0x0>;
|
||||
};
|
||||
|
||||
ir_boot_recovery {
|
||||
device_type = "ir_boot_recovery";
|
||||
status = "disabled";
|
||||
status = "okay";
|
||||
ir_work_mode = <0x1>;
|
||||
ir_press_times = <0x2>;
|
||||
ir_detect_time = <0x1>;
|
||||
@@ -5116,13 +5068,6 @@
|
||||
dram_tpr13 = <0x40>;
|
||||
};
|
||||
|
||||
//sunxi_hdmi_detect {
|
||||
// compatible = "allwinner,sun50iw9-hdmi-detect";
|
||||
// status = "okay";
|
||||
// key_io = <0x53 0x8 0x10 0x0 0x0 0x0 0x0>;
|
||||
// hhpd_io = <0x53 0x2 0x3 0x1 0x0 0x0 0x0>;
|
||||
//};
|
||||
|
||||
secure {
|
||||
device_type = "secure";
|
||||
dram_region_mbytes = <0x50>;
|
||||
@@ -5527,7 +5472,7 @@
|
||||
phandle = <0x17d>;
|
||||
};
|
||||
|
||||
sunxi-sid-ng@03006000 {
|
||||
sunxi_sid: sunxi-sid-ng@03006000 {
|
||||
compatible = "allwinner,sun50iw9p1-sid";
|
||||
reg = <0x0 0x3006000 0x0 0x1000>;
|
||||
#address-cells = <0x1>;
|
||||
@@ -5593,23 +5538,6 @@
|
||||
phandle = <0x28>;
|
||||
};
|
||||
|
||||
headphones-sound {
|
||||
status = "okay";
|
||||
compatible = "simple-audio-card";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hp_det>;
|
||||
simple-audio-card,format = "i2s";
|
||||
simple-audio-card,name = "rk-es8316-hp-sound";
|
||||
simple-audio-card,mclk-fs = <256>;
|
||||
simple-audio-card,hp-det-gpio = <0x53 7 10 0x6 1 0xffffffff 0xffffffff>;
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&ahub_daudio3>;
|
||||
};
|
||||
simple-audio-card,codec {
|
||||
sound-dai = <&es8316>;
|
||||
};
|
||||
};
|
||||
|
||||
gpu@0x01800000 {
|
||||
device_type = "gpu";
|
||||
compatible = "arm,mali-midgard";
|
||||
10
external/packages/pack-uboot/sun50iw9/bin/dts/orangepizero2-u-boot.dts
vendored
Normal file → Executable file
10
external/packages/pack-uboot/sun50iw9/bin/dts/orangepizero2-u-boot.dts
vendored
Normal file → Executable file
@@ -1476,10 +1476,10 @@
|
||||
};
|
||||
|
||||
twi1@0 {
|
||||
allwinner,pins = "PA2", "PA3";
|
||||
allwinner,pins = "PH0", "PH1";
|
||||
allwinner,pname = "twi1_scl", "twi1_sda";
|
||||
allwinner,function = "twi1";
|
||||
allwinner,muxsel = <0x4>;
|
||||
allwinner,muxsel = <0x5>;
|
||||
allwinner,drive = <0x1>;
|
||||
allwinner,pull = <0x0>;
|
||||
linux,phandle = <0x3f>;
|
||||
@@ -1487,7 +1487,7 @@
|
||||
};
|
||||
|
||||
twi1@1 {
|
||||
allwinner,pins = "PA2", "PA3";
|
||||
allwinner,pins = "PH0", "PH1";
|
||||
allwinner,function = "io_disabled";
|
||||
allwinner,muxsel = <0x7>;
|
||||
allwinner,drive = <0x1>;
|
||||
@@ -1497,7 +1497,7 @@
|
||||
};
|
||||
|
||||
twi2@0 {
|
||||
allwinner,pins = "PE20", "PE21";
|
||||
allwinner,pins = "PH2", "PH3";
|
||||
allwinner,pname = "twi2_scl", "twi2_sda";
|
||||
allwinner,function = "twi2";
|
||||
allwinner,muxsel = <0x5>;
|
||||
@@ -1508,7 +1508,7 @@
|
||||
};
|
||||
|
||||
twi2@1 {
|
||||
allwinner,pins = "PE20", "PE21";
|
||||
allwinner,pins = "PH2", "PH3";
|
||||
allwinner,function = "io_disabled";
|
||||
allwinner,muxsel = <0x7>;
|
||||
allwinner,drive = <0x1>;
|
||||
|
||||
3116
external/packages/pack-uboot/sun50iw9/bin/dts/orangepizero3-u-boot-current-pwm.dts
vendored
Normal file
3116
external/packages/pack-uboot/sun50iw9/bin/dts/orangepizero3-u-boot-current-pwm.dts
vendored
Normal file
File diff suppressed because it is too large
Load Diff
3116
external/packages/pack-uboot/sun50iw9/bin/dts/orangepizero3-u-boot-current.dts
vendored
Normal file
3116
external/packages/pack-uboot/sun50iw9/bin/dts/orangepizero3-u-boot-current.dts
vendored
Normal file
File diff suppressed because it is too large
Load Diff
5979
external/packages/pack-uboot/sun50iw9/bin/dts/orangepizero3-u-boot-legacy.dts
vendored
Executable file
5979
external/packages/pack-uboot/sun50iw9/bin/dts/orangepizero3-u-boot-legacy.dts
vendored
Executable file
File diff suppressed because it is too large
Load Diff
3040
external/packages/pack-uboot/sun50iw9/bin/dts/orangepizero3-u-boot.dts
vendored
Normal file
3040
external/packages/pack-uboot/sun50iw9/bin/dts/orangepizero3-u-boot.dts
vendored
Normal file
File diff suppressed because it is too large
Load Diff
Binary file not shown.
BIN
external/packages/pack-uboot/sun50iw9/bin/monitor.fex-linux5.4
vendored
Executable file
BIN
external/packages/pack-uboot/sun50iw9/bin/monitor.fex-linux5.4
vendored
Executable file
Binary file not shown.
BIN
external/packages/pack-uboot/sun50iw9/bin/optee.fex
vendored
Normal file
BIN
external/packages/pack-uboot/sun50iw9/bin/optee.fex
vendored
Normal file
Binary file not shown.
BIN
external/packages/pack-uboot/sun50iw9/bin/optee_sun50iw9p1.bin
vendored
Normal file
BIN
external/packages/pack-uboot/sun50iw9/bin/optee_sun50iw9p1.bin
vendored
Normal file
Binary file not shown.
@@ -6,7 +6,7 @@
|
||||
|
||||
[product]
|
||||
version = "100"
|
||||
machine = "evb"
|
||||
machine = "orangepizero3"
|
||||
|
||||
[platform]
|
||||
eraseflag = 1
|
||||
@@ -37,33 +37,26 @@ dragonboard_test= 0
|
||||
dcdc2_vol = 1001000
|
||||
aldo1_vol = 1001800
|
||||
dldo1_vol = 1003300
|
||||
cldo2_vol = 1003300
|
||||
cldo1_vol = 1001800
|
||||
|
||||
[axp1530_power_sply]
|
||||
dcdc2_vol = 1001000
|
||||
aldo1_vol = 1001800
|
||||
dldo1_vol = 1003300
|
||||
cldo2_vol = 1003300
|
||||
cldo1_vol = 1001800
|
||||
|
||||
[axp806_power_sply]
|
||||
dcdce_vol = 1003300
|
||||
;dcdcd_vol = 1001110
|
||||
aldo1_vol = 1003300
|
||||
bldo1_vol = 1001800
|
||||
cldo2_vol = 1003300
|
||||
bldo2_vol = 1001800
|
||||
cldo1_vol = 1001800
|
||||
|
||||
[card_boot]
|
||||
logical_start = 40960
|
||||
sprite_gpio0 =
|
||||
|
||||
;----------------------------------------------------------------------------------
|
||||
; GPIO init on uboot
|
||||
;----------------------------------------------------------------------------------
|
||||
[boot_init_gpio]
|
||||
boot_init_gpio_used = 1
|
||||
gpio0 = port:PC12<1><default><default><0>
|
||||
gpio1 = port:PC2<1><default><default><0>
|
||||
gpio2 = port:PC7<1><default><default><1>
|
||||
|
||||
;----------------------------------------------------------------------------------
|
||||
; ir_boot_recovery_used : 1: used this function 0: not used
|
||||
; ir_work_mode : 模式选择
|
||||
@@ -84,7 +77,7 @@ gpio2 = port:PC7<1><default><default><1>
|
||||
;----------------------------------------------------------------------------------
|
||||
|
||||
[ir_boot_recovery]
|
||||
ir_boot_recovery_used = 0
|
||||
ir_boot_recovery_used = 1
|
||||
ir_work_mode = 1
|
||||
ir_press_times = 2
|
||||
ir_detect_time = 1
|
||||
@@ -117,7 +110,7 @@ ir_addr_code3 = 0xfe01
|
||||
; recovery_key : 按键配置.
|
||||
;----------------------------------------------------------------------------------
|
||||
[key_boot_recovery]
|
||||
recovery_key_used = 0
|
||||
recovery_key_used = 1
|
||||
press_mode_enable = 0
|
||||
key_work_mode = 0
|
||||
short_press_mode = 0
|
||||
@@ -196,7 +189,6 @@ pll8 = 360
|
||||
pll9 = 297
|
||||
pll10 = 264
|
||||
|
||||
|
||||
;*****************************************************************************
|
||||
;
|
||||
;dram select configuration
|
||||
@@ -208,65 +200,63 @@ pll10 = 264
|
||||
;gpadc_channel : 选择gpadc通道 有效值(0-3)
|
||||
;select_gpio1-4 : 选择gpio pin
|
||||
;*****************************************************************************
|
||||
[dram_select_para]
|
||||
select_mode = 1
|
||||
select_gpio0 = port:PI14<0><1><default><default>
|
||||
select_gpio1 = port:PI15<0><1><default><default>
|
||||
select_gpio2 = port:PI16<0><1><default><default>
|
||||
select_gpio3 =
|
||||
|
||||
|
||||
[dram_select_para]
|
||||
select_mode = 0
|
||||
gpadc_channel = 1
|
||||
select_gpio0 =
|
||||
select_gpio1 =
|
||||
select_gpio2 =
|
||||
select_gpio3 =
|
||||
|
||||
;*****************************************************************************
|
||||
;sdram configuration
|
||||
;
|
||||
; dram_para: 无CK跨接电容参数（保留）
|
||||
; dram_para1: 有CK跨接电容参数（保留）
|
||||
; dram_para2~6: 暂时预留
|
||||
; dram_para7: 无CK跨接电容参数（保留）
|
||||
; dram_para8~15: 暂时预留
|
||||
;*****************************************************************************
|
||||
[dram_para]
|
||||
dram_clk = 648
|
||||
dram_type = 3
|
||||
dram_dx_odt = 0x03030303
|
||||
dram_dx_dri = 0x0e0e0e0e
|
||||
dram_ca_dri = 0x1c12
|
||||
dram_odt_en = 1
|
||||
dram_para1 = 0x30fb
|
||||
dram_para2 = 0x0000
|
||||
dram_mr0 = 0x840
|
||||
dram_mr1 = 0x4
|
||||
dram_mr2 = 0x8
|
||||
dram_mr3 = 0x0
|
||||
dram_mr4 = 0x0
|
||||
dram_mr5 = 0x0
|
||||
dram_mr6 = 0x0
|
||||
dram_mr11 = 0x0
|
||||
dram_mr12 = 0x0
|
||||
dram_mr13 = 0x0
|
||||
dram_mr14 = 0x0
|
||||
dram_mr16 = 0x0
|
||||
dram_mr17 = 0x0
|
||||
dram_mr22 = 0x0
|
||||
dram_tpr0 = 0xC0000C05
|
||||
dram_tpr1 = 0x0
|
||||
dram_tpr2 = 0x0
|
||||
dram_tpr3 = 0x0
|
||||
dram_tpr6 = 0x33808080
|
||||
dram_tpr10 = 0x002F0007
|
||||
dram_tpr11 = 0xffffdddd
|
||||
dram_tpr12 = 0xfedf7557
|
||||
dram_tpr13 = 0x40
|
||||
dram_clk = 792
|
||||
dram_type = 8
|
||||
dram_dx_odt = 0x07070707
|
||||
dram_dx_dri = 0x0e0e0e0e
|
||||
dram_ca_dri = 0x0e0e
|
||||
dram_odt_en = 0xaaaaeeee
|
||||
dram_para1 = 0x30fa
|
||||
dram_para2 = 0x0000
|
||||
dram_mr0 = 0x0
|
||||
dram_mr1 = 0x34
|
||||
dram_mr2 = 0x1b
|
||||
dram_mr3 = 0x33
|
||||
dram_mr4 = 0x3
|
||||
dram_mr5 = 0x0
|
||||
dram_mr6 = 0x0
|
||||
dram_mr11 = 0x4
|
||||
dram_mr12 = 0x72
|
||||
dram_mr13 = 0x0
|
||||
dram_mr14 = 0x9
|
||||
dram_mr16 = 0x0
|
||||
dram_mr17 = 0x0
|
||||
dram_mr22 = 0x24
|
||||
dram_tpr0 = 0x0
|
||||
dram_tpr1 = 0x0
|
||||
dram_tpr2 = 0x0
|
||||
dram_tpr3 = 0x0
|
||||
dram_tpr6 = 0x35808080
|
||||
dram_tpr10 = 0x402f6663
|
||||
dram_tpr11 = 0x36363535
|
||||
dram_tpr12 = 0x10101110
|
||||
dram_tpr13 = 0x2080C60
|
||||
|
||||
[dram_para1]
|
||||
dram_clk = 648
|
||||
|
||||
dram_clk = 720
|
||||
dram_type = 3
|
||||
dram_dx_odt = 0x03030303
|
||||
dram_dx_odt = 0x08080808
|
||||
dram_dx_dri = 0x0e0e0e0e
|
||||
dram_ca_dri = 0x1c1c
|
||||
dram_ca_dri = 0x0e0e
|
||||
dram_odt_en = 1
|
||||
dram_para1 = 0x30fb
|
||||
dram_para2 = 0x0000
|
||||
dram_para1 = 0x30FA
|
||||
dram_para2 = 0x1000
|
||||
dram_mr0 = 0x840
|
||||
dram_mr1 = 0x4
|
||||
dram_mr2 = 0x8
|
||||
@@ -281,25 +271,26 @@ dram_mr14 = 0x0
|
||||
dram_mr16 = 0x0
|
||||
dram_mr17 = 0x0
|
||||
dram_mr22 = 0x0
|
||||
dram_tpr0 = 0xC0001305
|
||||
dram_tpr0 = 0x0
|
||||
dram_tpr1 = 0x0
|
||||
dram_tpr2 = 0x0
|
||||
dram_tpr3 = 0x0
|
||||
dram_tpr6 = 0x33808080
|
||||
dram_tpr10 = 0x002F0006
|
||||
dram_tpr11 = 0xffffdddd
|
||||
dram_tpr12 = 0xfedf7657
|
||||
dram_tpr10 = 0x00f83438
|
||||
dram_tpr11 = 0x0
|
||||
dram_tpr12 = 0x0
|
||||
dram_tpr13 = 0x40
|
||||
|
||||
[dram_para2]
|
||||
dram_clk = 648
|
||||
|
||||
dram_clk = 720
|
||||
dram_type = 3
|
||||
dram_dx_odt = 0x03030303
|
||||
dram_dx_odt = 0x08080808
|
||||
dram_dx_dri = 0x0e0e0e0e
|
||||
dram_ca_dri = 0x1c1c
|
||||
dram_ca_dri = 0x0e0e
|
||||
dram_odt_en = 1
|
||||
dram_para1 = 0x30fb
|
||||
dram_para2 = 0x0000
|
||||
dram_para1 = 0x30FA
|
||||
dram_para2 = 0x1000
|
||||
dram_mr0 = 0x840
|
||||
dram_mr1 = 0x4
|
||||
dram_mr2 = 0x8
|
||||
@@ -314,25 +305,26 @@ dram_mr14 = 0x0
|
||||
dram_mr16 = 0x0
|
||||
dram_mr17 = 0x0
|
||||
dram_mr22 = 0x0
|
||||
dram_tpr0 = 0xC0001305
|
||||
dram_tpr0 = 0x0
|
||||
dram_tpr1 = 0x0
|
||||
dram_tpr2 = 0x0
|
||||
dram_tpr3 = 0x0
|
||||
dram_tpr6 = 0x33808080
|
||||
dram_tpr10 = 0x002F0006
|
||||
dram_tpr11 = 0xffffdddd
|
||||
dram_tpr12 = 0xfedf7657
|
||||
dram_tpr10 = 0x00f83438
|
||||
dram_tpr11 = 0x0
|
||||
dram_tpr12 = 0x0
|
||||
dram_tpr13 = 0x40
|
||||
|
||||
[dram_para3]
|
||||
dram_clk = 648
|
||||
|
||||
dram_clk = 720
|
||||
dram_type = 3
|
||||
dram_dx_odt = 0x03030303
|
||||
dram_dx_odt = 0x08080808
|
||||
dram_dx_dri = 0x0e0e0e0e
|
||||
dram_ca_dri = 0x1c1c
|
||||
dram_ca_dri = 0x0e0e
|
||||
dram_odt_en = 1
|
||||
dram_para1 = 0x30fb
|
||||
dram_para2 = 0x0000
|
||||
dram_para1 = 0x30FA
|
||||
dram_para2 = 0x1000
|
||||
dram_mr0 = 0x840
|
||||
dram_mr1 = 0x4
|
||||
dram_mr2 = 0x8
|
||||
@@ -347,25 +339,26 @@ dram_mr14 = 0x0
|
||||
dram_mr16 = 0x0
|
||||
dram_mr17 = 0x0
|
||||
dram_mr22 = 0x0
|
||||
dram_tpr0 = 0xC0001305
|
||||
dram_tpr0 = 0x0
|
||||
dram_tpr1 = 0x0
|
||||
dram_tpr2 = 0x0
|
||||
dram_tpr3 = 0x0
|
||||
dram_tpr6 = 0x33808080
|
||||
dram_tpr10 = 0x002F0006
|
||||
dram_tpr11 = 0xffffdddd
|
||||
dram_tpr12 = 0xfedf7657
|
||||
dram_tpr10 = 0x00f83438
|
||||
dram_tpr11 = 0x0
|
||||
dram_tpr12 = 0x0
|
||||
dram_tpr13 = 0x40
|
||||
|
||||
[dram_para4]
|
||||
dram_clk = 648
|
||||
|
||||
dram_clk = 720
|
||||
dram_type = 3
|
||||
dram_dx_odt = 0x03030303
|
||||
dram_dx_odt = 0x08080808
|
||||
dram_dx_dri = 0x0e0e0e0e
|
||||
dram_ca_dri = 0x1c1c
|
||||
dram_ca_dri = 0x0e0e
|
||||
dram_odt_en = 1
|
||||
dram_para1 = 0x30fb
|
||||
dram_para2 = 0x0000
|
||||
dram_para1 = 0x30FA
|
||||
dram_para2 = 0x1000
|
||||
dram_mr0 = 0x840
|
||||
dram_mr1 = 0x4
|
||||
dram_mr2 = 0x8
|
||||
@@ -380,25 +373,26 @@ dram_mr14 = 0x0
|
||||
dram_mr16 = 0x0
|
||||
dram_mr17 = 0x0
|
||||
dram_mr22 = 0x0
|
||||
dram_tpr0 = 0xC0001305
|
||||
dram_tpr0 = 0x0
|
||||
dram_tpr1 = 0x0
|
||||
dram_tpr2 = 0x0
|
||||
dram_tpr3 = 0x0
|
||||
dram_tpr6 = 0x33808080
|
||||
dram_tpr10 = 0x002F0006
|
||||
dram_tpr11 = 0xffffdddd
|
||||
dram_tpr12 = 0xfedf7657
|
||||
dram_tpr10 = 0x00f83438
|
||||
dram_tpr11 = 0x0
|
||||
dram_tpr12 = 0x0
|
||||
dram_tpr13 = 0x40
|
||||
|
||||
[dram_para5]
|
||||
dram_clk = 648
|
||||
|
||||
dram_clk = 720
|
||||
dram_type = 3
|
||||
dram_dx_odt = 0x03030303
|
||||
dram_dx_odt = 0x08080808
|
||||
dram_dx_dri = 0x0e0e0e0e
|
||||
dram_ca_dri = 0x1c1c
|
||||
dram_ca_dri = 0x0e0e
|
||||
dram_odt_en = 1
|
||||
dram_para1 = 0x30fb
|
||||
dram_para2 = 0x0000
|
||||
dram_para1 = 0x30FA
|
||||
dram_para2 = 0x1000
|
||||
dram_mr0 = 0x840
|
||||
dram_mr1 = 0x4
|
||||
dram_mr2 = 0x8
|
||||
@@ -413,25 +407,26 @@ dram_mr14 = 0x0
|
||||
dram_mr16 = 0x0
|
||||
dram_mr17 = 0x0
|
||||
dram_mr22 = 0x0
|
||||
dram_tpr0 = 0xC0001305
|
||||
dram_tpr0 = 0x0
|
||||
dram_tpr1 = 0x0
|
||||
dram_tpr2 = 0x0
|
||||
dram_tpr3 = 0x0
|
||||
dram_tpr6 = 0x33808080
|
||||
dram_tpr10 = 0x002F0006
|
||||
dram_tpr11 = 0xffffdddd
|
||||
dram_tpr12 = 0xfedf7657
|
||||
dram_tpr10 = 0x00f83438
|
||||
dram_tpr11 = 0x0
|
||||
dram_tpr12 = 0x0
|
||||
dram_tpr13 = 0x40
|
||||
|
||||
[dram_para6]
|
||||
dram_clk = 648
|
||||
|
||||
dram_clk = 720
|
||||
dram_type = 3
|
||||
dram_dx_odt = 0x03030303
|
||||
dram_dx_odt = 0x08080808
|
||||
dram_dx_dri = 0x0e0e0e0e
|
||||
dram_ca_dri = 0x1c1c
|
||||
dram_ca_dri = 0x0e0e
|
||||
dram_odt_en = 1
|
||||
dram_para1 = 0x30fb
|
||||
dram_para2 = 0x0000
|
||||
dram_para1 = 0x30FA
|
||||
dram_para2 = 0x1000
|
||||
dram_mr0 = 0x840
|
||||
dram_mr1 = 0x4
|
||||
dram_mr2 = 0x8
|
||||
@@ -446,25 +441,26 @@ dram_mr14 = 0x0
|
||||
dram_mr16 = 0x0
|
||||
dram_mr17 = 0x0
|
||||
dram_mr22 = 0x0
|
||||
dram_tpr0 = 0xC0001305
|
||||
dram_tpr0 = 0x0
|
||||
dram_tpr1 = 0x0
|
||||
dram_tpr2 = 0x0
|
||||
dram_tpr3 = 0x0
|
||||
dram_tpr6 = 0x33808080
|
||||
dram_tpr10 = 0x002F0006
|
||||
dram_tpr11 = 0xffffdddd
|
||||
dram_tpr12 = 0xfedf7657
|
||||
dram_tpr10 = 0x00f83438
|
||||
dram_tpr11 = 0x0
|
||||
dram_tpr12 = 0x0
|
||||
dram_tpr13 = 0x40
|
||||
|
||||
[dram_para7]
|
||||
dram_clk = 648
|
||||
|
||||
dram_clk = 720
|
||||
dram_type = 3
|
||||
dram_dx_odt = 0x03030303
|
||||
dram_dx_odt = 0x08080808
|
||||
dram_dx_dri = 0x0e0e0e0e
|
||||
dram_ca_dri = 0x1c12
|
||||
dram_ca_dri = 0x0e0e
|
||||
dram_odt_en = 1
|
||||
dram_para1 = 0x30fb
|
||||
dram_para2 = 0x0000
|
||||
dram_para1 = 0x30FA
|
||||
dram_para2 = 0x1000
|
||||
dram_mr0 = 0x840
|
||||
dram_mr1 = 0x4
|
||||
dram_mr2 = 0x8
|
||||
@@ -479,25 +475,26 @@ dram_mr14 = 0x0
|
||||
dram_mr16 = 0x0
|
||||
dram_mr17 = 0x0
|
||||
dram_mr22 = 0x0
|
||||
dram_tpr0 = 0xC0000C05
|
||||
dram_tpr0 = 0x0
|
||||
dram_tpr1 = 0x0
|
||||
dram_tpr2 = 0x0
|
||||
dram_tpr3 = 0x0
|
||||
dram_tpr6 = 0x33808080
|
||||
dram_tpr10 = 0x002F0007
|
||||
dram_tpr11 = 0xffffdddd
|
||||
dram_tpr12 = 0xfedf7557
|
||||
dram_tpr10 = 0x00f83438
|
||||
dram_tpr11 = 0x0
|
||||
dram_tpr12 = 0x0
|
||||
dram_tpr13 = 0x40
|
||||
|
||||
[dram_para8]
|
||||
dram_clk = 648
|
||||
|
||||
dram_clk = 720
|
||||
dram_type = 3
|
||||
dram_dx_odt = 0x03030303
|
||||
dram_dx_odt = 0x08080808
|
||||
dram_dx_dri = 0x0e0e0e0e
|
||||
dram_ca_dri = 0x1c1c
|
||||
dram_ca_dri = 0x0e0e
|
||||
dram_odt_en = 1
|
||||
dram_para1 = 0x30fb
|
||||
dram_para2 = 0x0000
|
||||
dram_para1 = 0x30FA
|
||||
dram_para2 = 0x1000
|
||||
dram_mr0 = 0x840
|
||||
dram_mr1 = 0x4
|
||||
dram_mr2 = 0x8
|
||||
@@ -512,25 +509,26 @@ dram_mr14 = 0x0
|
||||
dram_mr16 = 0x0
|
||||
dram_mr17 = 0x0
|
||||
dram_mr22 = 0x0
|
||||
dram_tpr0 = 0xC0001305
|
||||
dram_tpr0 = 0x0
|
||||
dram_tpr1 = 0x0
|
||||
dram_tpr2 = 0x0
|
||||
dram_tpr3 = 0x0
|
||||
dram_tpr6 = 0x33808080
|
||||
dram_tpr10 = 0x002F0006
|
||||
dram_tpr11 = 0xffffdddd
|
||||
dram_tpr12 = 0xfedf7657
|
||||
dram_tpr10 = 0x00f83438
|
||||
dram_tpr11 = 0x0
|
||||
dram_tpr12 = 0x0
|
||||
dram_tpr13 = 0x40
|
||||
|
||||
[dram_para9]
|
||||
dram_clk = 648
|
||||
|
||||
dram_clk = 720
|
||||
dram_type = 3
|
||||
dram_dx_odt = 0x03030303
|
||||
dram_dx_odt = 0x08080808
|
||||
dram_dx_dri = 0x0e0e0e0e
|
||||
dram_ca_dri = 0x1c1c
|
||||
dram_ca_dri = 0x0e0e
|
||||
dram_odt_en = 1
|
||||
dram_para1 = 0x30fb
|
||||
dram_para2 = 0x0000
|
||||
dram_para1 = 0x30FA
|
||||
dram_para2 = 0x1000
|
||||
dram_mr0 = 0x840
|
||||
dram_mr1 = 0x4
|
||||
dram_mr2 = 0x8
|
||||
@@ -545,25 +543,26 @@ dram_mr14 = 0x0
|
||||
dram_mr16 = 0x0
|
||||
dram_mr17 = 0x0
|
||||
dram_mr22 = 0x0
|
||||
dram_tpr0 = 0xC0001305
|
||||
dram_tpr0 = 0x0
|
||||
dram_tpr1 = 0x0
|
||||
dram_tpr2 = 0x0
|
||||
dram_tpr3 = 0x0
|
||||
dram_tpr6 = 0x33808080
|
||||
dram_tpr10 = 0x002F0006
|
||||
dram_tpr11 = 0xffffdddd
|
||||
dram_tpr12 = 0xfedf7657
|
||||
dram_tpr10 = 0x00f83438
|
||||
dram_tpr11 = 0x0
|
||||
dram_tpr12 = 0x0
|
||||
dram_tpr13 = 0x40
|
||||
|
||||
[dram_para10]
|
||||
dram_clk = 648
|
||||
|
||||
dram_clk = 720
|
||||
dram_type = 3
|
||||
dram_dx_odt = 0x03030303
|
||||
dram_dx_odt = 0x08080808
|
||||
dram_dx_dri = 0x0e0e0e0e
|
||||
dram_ca_dri = 0x1c1c
|
||||
dram_ca_dri = 0x0e0e
|
||||
dram_odt_en = 1
|
||||
dram_para1 = 0x30fb
|
||||
dram_para2 = 0x0000
|
||||
dram_para1 = 0x30FA
|
||||
dram_para2 = 0x1000
|
||||
dram_mr0 = 0x840
|
||||
dram_mr1 = 0x4
|
||||
dram_mr2 = 0x8
|
||||
@@ -578,25 +577,26 @@ dram_mr14 = 0x0
|
||||
dram_mr16 = 0x0
|
||||
dram_mr17 = 0x0
|
||||
dram_mr22 = 0x0
|
||||
dram_tpr0 = 0xC0001305
|
||||
dram_tpr0 = 0x0
|
||||
dram_tpr1 = 0x0
|
||||
dram_tpr2 = 0x0
|
||||
dram_tpr3 = 0x0
|
||||
dram_tpr6 = 0x33808080
|
||||
dram_tpr10 = 0x002F0006
|
||||
dram_tpr11 = 0xffffdddd
|
||||
dram_tpr12 = 0xfedf7657
|
||||
dram_tpr10 = 0x00f83438
|
||||
dram_tpr11 = 0x0
|
||||
dram_tpr12 = 0x0
|
||||
dram_tpr13 = 0x40
|
||||
|
||||
[dram_para11]
|
||||
dram_clk = 648
|
||||
|
||||
dram_clk = 720
|
||||
dram_type = 3
|
||||
dram_dx_odt = 0x03030303
|
||||
dram_dx_odt = 0x08080808
|
||||
dram_dx_dri = 0x0e0e0e0e
|
||||
dram_ca_dri = 0x1c1c
|
||||
dram_ca_dri = 0x0e0e
|
||||
dram_odt_en = 1
|
||||
dram_para1 = 0x30fb
|
||||
dram_para2 = 0x0000
|
||||
dram_para1 = 0x30FA
|
||||
dram_para2 = 0x1000
|
||||
dram_mr0 = 0x840
|
||||
dram_mr1 = 0x4
|
||||
dram_mr2 = 0x8
|
||||
@@ -611,25 +611,26 @@ dram_mr14 = 0x0
|
||||
dram_mr16 = 0x0
|
||||
dram_mr17 = 0x0
|
||||
dram_mr22 = 0x0
|
||||
dram_tpr0 = 0xC0001305
|
||||
dram_tpr0 = 0x0
|
||||
dram_tpr1 = 0x0
|
||||
dram_tpr2 = 0x0
|
||||
dram_tpr3 = 0x0
|
||||
dram_tpr6 = 0x33808080
|
||||
dram_tpr10 = 0x002F0006
|
||||
dram_tpr11 = 0xffffdddd
|
||||
dram_tpr12 = 0xfedf7657
|
||||
dram_tpr10 = 0x00f83438
|
||||
dram_tpr11 = 0x0
|
||||
dram_tpr12 = 0x0
|
||||
dram_tpr13 = 0x40
|
||||
|
||||
[dram_para12]
|
||||
dram_clk = 648
|
||||
|
||||
dram_clk = 720
|
||||
dram_type = 3
|
||||
dram_dx_odt = 0x03030303
|
||||
dram_dx_odt = 0x08080808
|
||||
dram_dx_dri = 0x0e0e0e0e
|
||||
dram_ca_dri = 0x1c1c
|
||||
dram_ca_dri = 0x0e0e
|
||||
dram_odt_en = 1
|
||||
dram_para1 = 0x30fb
|
||||
dram_para2 = 0x0000
|
||||
dram_para1 = 0x30FA
|
||||
dram_para2 = 0x1000
|
||||
dram_mr0 = 0x840
|
||||
dram_mr1 = 0x4
|
||||
dram_mr2 = 0x8
|
||||
@@ -644,25 +645,26 @@ dram_mr14 = 0x0
|
||||
dram_mr16 = 0x0
|
||||
dram_mr17 = 0x0
|
||||
dram_mr22 = 0x0
|
||||
dram_tpr0 = 0xC0001305
|
||||
dram_tpr0 = 0x0
|
||||
dram_tpr1 = 0x0
|
||||
dram_tpr2 = 0x0
|
||||
dram_tpr3 = 0x0
|
||||
dram_tpr6 = 0x33808080
|
||||
dram_tpr10 = 0x002F0006
|
||||
dram_tpr11 = 0xffffdddd
|
||||
dram_tpr12 = 0xfedf7657
|
||||
dram_tpr10 = 0x00f83438
|
||||
dram_tpr11 = 0x0
|
||||
dram_tpr12 = 0x0
|
||||
dram_tpr13 = 0x40
|
||||
|
||||
[dram_para13]
|
||||
dram_clk = 648
|
||||
|
||||
dram_clk = 720
|
||||
dram_type = 3
|
||||
dram_dx_odt = 0x03030303
|
||||
dram_dx_odt = 0x08080808
|
||||
dram_dx_dri = 0x0e0e0e0e
|
||||
dram_ca_dri = 0x1c1c
|
||||
dram_ca_dri = 0x0e0e
|
||||
dram_odt_en = 1
|
||||
dram_para1 = 0x30fb
|
||||
dram_para2 = 0x0000
|
||||
dram_para1 = 0x30FA
|
||||
dram_para2 = 0x1000
|
||||
dram_mr0 = 0x840
|
||||
dram_mr1 = 0x4
|
||||
dram_mr2 = 0x8
|
||||
@@ -677,25 +679,26 @@ dram_mr14 = 0x0
|
||||
dram_mr16 = 0x0
|
||||
dram_mr17 = 0x0
|
||||
dram_mr22 = 0x0
|
||||
dram_tpr0 = 0xC0001305
|
||||
dram_tpr0 = 0x0
|
||||
dram_tpr1 = 0x0
|
||||
dram_tpr2 = 0x0
|
||||
dram_tpr3 = 0x0
|
||||
dram_tpr6 = 0x33808080
|
||||
dram_tpr10 = 0x002F0006
|
||||
dram_tpr11 = 0xffffdddd
|
||||
dram_tpr12 = 0xfedf7657
|
||||
dram_tpr10 = 0x00f83438
|
||||
dram_tpr11 = 0x0
|
||||
dram_tpr12 = 0x0
|
||||
dram_tpr13 = 0x40
|
||||
|
||||
[dram_para14]
|
||||
dram_clk = 648
|
||||
|
||||
dram_clk = 720
|
||||
dram_type = 3
|
||||
dram_dx_odt = 0x03030303
|
||||
dram_dx_odt = 0x08080808
|
||||
dram_dx_dri = 0x0e0e0e0e
|
||||
dram_ca_dri = 0x1c1c
|
||||
dram_ca_dri = 0x0e0e
|
||||
dram_odt_en = 1
|
||||
dram_para1 = 0x30fb
|
||||
dram_para2 = 0x0000
|
||||
dram_para1 = 0x30FA
|
||||
dram_para2 = 0x1000
|
||||
dram_mr0 = 0x840
|
||||
dram_mr1 = 0x4
|
||||
dram_mr2 = 0x8
|
||||
@@ -710,25 +713,26 @@ dram_mr14 = 0x0
|
||||
dram_mr16 = 0x0
|
||||
dram_mr17 = 0x0
|
||||
dram_mr22 = 0x0
|
||||
dram_tpr0 = 0xC0001305
|
||||
dram_tpr0 = 0x0
|
||||
dram_tpr1 = 0x0
|
||||
dram_tpr2 = 0x0
|
||||
dram_tpr3 = 0x0
|
||||
dram_tpr6 = 0x33808080
|
||||
dram_tpr10 = 0x002F0006
|
||||
dram_tpr11 = 0xffffdddd
|
||||
dram_tpr12 = 0xfedf7657
|
||||
dram_tpr10 = 0x00f83438
|
||||
dram_tpr11 = 0x0
|
||||
dram_tpr12 = 0x0
|
||||
dram_tpr13 = 0x40
|
||||
|
||||
[dram_para15]
|
||||
dram_clk = 648
|
||||
|
||||
dram_clk = 720
|
||||
dram_type = 3
|
||||
dram_dx_odt = 0x03030303
|
||||
dram_dx_odt = 0x08080808
|
||||
dram_dx_dri = 0x0e0e0e0e
|
||||
dram_ca_dri = 0x1c1c
|
||||
dram_ca_dri = 0x0e0e
|
||||
dram_odt_en = 1
|
||||
dram_para1 = 0x30fb
|
||||
dram_para2 = 0x0000
|
||||
dram_para1 = 0x30FA
|
||||
dram_para2 = 0x1000
|
||||
dram_mr0 = 0x840
|
||||
dram_mr1 = 0x4
|
||||
dram_mr2 = 0x8
|
||||
@@ -743,16 +747,48 @@ dram_mr14 = 0x0
|
||||
dram_mr16 = 0x0
|
||||
dram_mr17 = 0x0
|
||||
dram_mr22 = 0x0
|
||||
dram_tpr0 = 0xC0001305
|
||||
dram_tpr0 = 0x0
|
||||
dram_tpr1 = 0x0
|
||||
dram_tpr2 = 0x0
|
||||
dram_tpr3 = 0x0
|
||||
dram_tpr6 = 0x33808080
|
||||
dram_tpr10 = 0x002F0006
|
||||
dram_tpr11 = 0xffffdddd
|
||||
dram_tpr12 = 0xfedf7657
|
||||
dram_tpr10 = 0x00f83438
|
||||
dram_tpr11 = 0x0
|
||||
dram_tpr12 = 0x0
|
||||
dram_tpr13 = 0x40
|
||||
|
||||
[dram_para16]
|
||||
dram_clk = 792
|
||||
dram_type = 8
|
||||
dram_dx_odt = 0x07070707
|
||||
dram_dx_dri = 0x0e0e0e0e
|
||||
dram_ca_dri = 0x0e0e
|
||||
dram_odt_en = 0xaaaaeeee
|
||||
dram_para1 = 0x30fa
|
||||
dram_para2 = 0x0000
|
||||
dram_mr0 = 0x0
|
||||
dram_mr1 = 0x34
|
||||
dram_mr2 = 0x1b
|
||||
dram_mr3 = 0x33
|
||||
dram_mr4 = 0x3
|
||||
dram_mr5 = 0x0
|
||||
dram_mr6 = 0x0
|
||||
dram_mr11 = 0x4
|
||||
dram_mr12 = 0x72
|
||||
dram_mr13 = 0x0
|
||||
dram_mr14 = 0x9
|
||||
dram_mr16 = 0x0
|
||||
dram_mr17 = 0x0
|
||||
dram_mr22 = 0x24
|
||||
dram_tpr0 = 0x0
|
||||
dram_tpr1 = 0x0
|
||||
dram_tpr2 = 0x0
|
||||
dram_tpr3 = 0x0
|
||||
dram_tpr6 = 0x35808080
|
||||
dram_tpr10 = 0x402f6663
|
||||
dram_tpr11 = 0x36363535
|
||||
dram_tpr12 = 0x10101110
|
||||
dram_tpr13 = 0x2080C60
|
||||
|
||||
;----------------------------------------------------------------------------------
|
||||
;os life cycle para configuration
|
||||
@@ -803,7 +839,6 @@ nand0_p1 = 0x55aaaa55
|
||||
nand0_p2 = 0x55aaaa55
|
||||
nand0_p3 = 0x55aaaa55
|
||||
|
||||
|
||||
[secure]
|
||||
dram_region_mbytes = 80
|
||||
drm_region_mbytes = 0
|
||||
@@ -223,39 +223,37 @@ select_gpio3 =
|
||||
;
|
||||
;*****************************************************************************
|
||||
[dram_para]
|
||||
|
||||
dram_clk = 720
|
||||
dram_type = 3
|
||||
dram_dx_odt = 0x08080808
|
||||
dram_dx_dri = 0x0e0e0e0e
|
||||
dram_ca_dri = 0x0e0e
|
||||
dram_odt_en = 1
|
||||
dram_para1 = 0x30FA
|
||||
dram_para2 = 0x1000
|
||||
dram_mr0 = 0x840
|
||||
dram_mr1 = 0x4
|
||||
dram_mr2 = 0x8
|
||||
dram_mr3 = 0x0
|
||||
dram_mr4 = 0x0
|
||||
dram_mr5 = 0x0
|
||||
dram_mr6 = 0x0
|
||||
dram_mr11 = 0x0
|
||||
dram_mr12 = 0x0
|
||||
dram_mr13 = 0x0
|
||||
dram_mr14 = 0x0
|
||||
dram_mr16 = 0x0
|
||||
dram_mr17 = 0x0
|
||||
dram_mr22 = 0x0
|
||||
dram_tpr0 = 0x0
|
||||
dram_tpr1 = 0x0
|
||||
dram_tpr2 = 0x0
|
||||
dram_tpr3 = 0x0
|
||||
dram_tpr6 = 0x33808080
|
||||
dram_tpr10 = 0x00f83438
|
||||
dram_tpr11 = 0x0
|
||||
dram_tpr12 = 0x0
|
||||
dram_tpr13 = 0x40
|
||||
|
||||
dram_clk = 672
|
||||
dram_type = 7
|
||||
dram_dx_odt = 0x06060606
|
||||
dram_dx_dri = 0x0d0d0d0d
|
||||
dram_ca_dri = 0x0d0d
|
||||
dram_odt_en = 0x9988eeee
|
||||
dram_para1 = 0x30fa
|
||||
dram_para2 = 0x1000
|
||||
dram_mr0 = 0x0
|
||||
dram_mr1 = 0xc3
|
||||
dram_mr2 = 0x6
|
||||
dram_mr3 = 0x1
|
||||
dram_mr4 = 0x0
|
||||
dram_mr5 = 0x0
|
||||
dram_mr6 = 0x0
|
||||
dram_mr11 = 0x0
|
||||
dram_mr12 = 0x0
|
||||
dram_mr13 = 0x0
|
||||
dram_mr14 = 0x0
|
||||
dram_mr16 = 0x0
|
||||
dram_mr17 = 0x0
|
||||
dram_mr22 = 0x0
|
||||
dram_tpr0 = 0x0
|
||||
dram_tpr1 = 0x0
|
||||
dram_tpr2 = 0x0
|
||||
dram_tpr3 = 0x0
|
||||
dram_tpr6 = 0x2fb28080
|
||||
dram_tpr10 = 0x402f4429
|
||||
dram_tpr11 = 0x0d0e0a09
|
||||
dram_tpr12 = 0x0c0d0a0b
|
||||
dram_tpr13 = 0xc60
|
||||
|
||||
[dram_para1]
|
||||
|
||||
|
||||
@@ -37,11 +37,13 @@ dragonboard_test= 0
|
||||
dcdc2_vol = 1001000
|
||||
aldo1_vol = 1001800
|
||||
dldo1_vol = 1003300
|
||||
cldo1_vol = 1001800
|
||||
|
||||
[axp1530_power_sply]
|
||||
dcdc2_vol = 1001000
|
||||
aldo1_vol = 1001800
|
||||
dldo1_vol = 1003300
|
||||
cldo1_vol = 1001800
|
||||
|
||||
[axp806_power_sply]
|
||||
dcdce_vol = 1003300
|
||||
@@ -49,6 +51,7 @@ dcdce_vol = 1003300
|
||||
aldo1_vol = 1003300
|
||||
bldo1_vol = 1001800
|
||||
bldo2_vol = 1001800
|
||||
cldo1_vol = 1001800
|
||||
|
||||
[card_boot]
|
||||
logical_start = 40960
|
||||
@@ -220,39 +223,37 @@ select_gpio3 =
|
||||
;
|
||||
;*****************************************************************************
|
||||
[dram_para]
|
||||
|
||||
dram_clk = 720
|
||||
dram_type = 3
|
||||
dram_dx_odt = 0x08080808
|
||||
dram_dx_dri = 0x0e0e0e0e
|
||||
dram_ca_dri = 0x0e0e
|
||||
dram_odt_en = 1
|
||||
dram_para1 = 0x30FA
|
||||
dram_para2 = 0x1000
|
||||
dram_mr0 = 0x840
|
||||
dram_mr1 = 0x4
|
||||
dram_mr2 = 0x8
|
||||
dram_mr3 = 0x0
|
||||
dram_mr4 = 0x0
|
||||
dram_mr5 = 0x0
|
||||
dram_mr6 = 0x0
|
||||
dram_mr11 = 0x0
|
||||
dram_mr12 = 0x0
|
||||
dram_mr13 = 0x0
|
||||
dram_mr14 = 0x0
|
||||
dram_mr16 = 0x0
|
||||
dram_mr17 = 0x0
|
||||
dram_mr22 = 0x0
|
||||
dram_tpr0 = 0x0
|
||||
dram_tpr1 = 0x0
|
||||
dram_tpr2 = 0x0
|
||||
dram_tpr3 = 0x0
|
||||
dram_tpr6 = 0x33808080
|
||||
dram_tpr10 = 0x00f83438
|
||||
dram_tpr11 = 0x0
|
||||
dram_tpr12 = 0x0
|
||||
dram_tpr13 = 0x40
|
||||
|
||||
dram_clk = 792
|
||||
dram_type = 8
|
||||
dram_dx_odt = 0x07070707
|
||||
dram_dx_dri = 0x0e0e0e0e
|
||||
dram_ca_dri = 0x0e0e
|
||||
dram_odt_en = 0xaaaaeeee
|
||||
dram_para1 = 0x30fa
|
||||
dram_para2 = 0x0000
|
||||
dram_mr0 = 0x0
|
||||
dram_mr1 = 0x34
|
||||
dram_mr2 = 0x1b
|
||||
dram_mr3 = 0x33
|
||||
dram_mr4 = 0x3
|
||||
dram_mr5 = 0x0
|
||||
dram_mr6 = 0x0
|
||||
dram_mr11 = 0x4
|
||||
dram_mr12 = 0x72
|
||||
dram_mr13 = 0x0
|
||||
dram_mr14 = 0x9
|
||||
dram_mr16 = 0x0
|
||||
dram_mr17 = 0x0
|
||||
dram_mr22 = 0x24
|
||||
dram_tpr0 = 0x0
|
||||
dram_tpr1 = 0x0
|
||||
dram_tpr2 = 0x0
|
||||
dram_tpr3 = 0x0
|
||||
dram_tpr6 = 0x35808080
|
||||
dram_tpr10 = 0x402f6663
|
||||
dram_tpr11 = 0x36363535
|
||||
dram_tpr12 = 0x10101110
|
||||
dram_tpr13 = 0x2080C60
|
||||
|
||||
[dram_para1]
|
||||
|
||||
|
||||
845
external/packages/pack-uboot/sun50iw9/bin/sys_config/sys_config_orangepizero3.fex
vendored
Executable file
845
external/packages/pack-uboot/sun50iw9/bin/sys_config/sys_config_orangepizero3.fex
vendored
Executable file
@@ -0,0 +1,845 @@
|
||||
;sunxi platform application
|
||||
;---------------------------------------------------------------------------------------------------------
|
||||
; 说明： 脚本中的字符串区分大小写，用户可以修改"="后面的数值，但是不要修改前面的字符串
|
||||
; 描述gpio的形式：Port:端口+组内序号<功能分配><内部电阻状态><驱动能力><输出电平状态>
|
||||
;---------------------------------------------------------------------------------------------------------
|
||||
|
||||
[product]
|
||||
version = "100"
|
||||
machine = "orangepizero3"
|
||||
|
||||
[platform]
|
||||
eraseflag = 1
|
||||
debug_mode = 3
|
||||
|
||||
;----------------------------------------------------------------------------------
|
||||
;[target] system bootup configuration
|
||||
;boot_clock = CPU boot frequency, Unit: MHz
|
||||
;storage_type = boot medium, 0-nand, 1-card0, 2-card2, -1(defualt)auto scan
|
||||
;advert_enable = 0-close advert logo 1-open advert logo (只有多核启动下有效)
|
||||
;----------------------------------------------------------------------------------
|
||||
[target]
|
||||
boot_clock = 1008
|
||||
storage_type = -1
|
||||
advert_enable = 0
|
||||
burn_key = 1
|
||||
dragonboard_test= 0
|
||||
|
||||
;----------------------------------------------------------------------------------
|
||||
; system configuration
|
||||
; ?
|
||||
;dcdc2_vol ---set dcdc2 voltage,mV,500-1200,10mV/step
|
||||
; 1220-1540,20mV/step
|
||||
;aldo1_vol ---set aldo1 voltage,mV,500-3500,100mV/step
|
||||
;dldo1_vol ---set dldo1 voltage,mV,500-3500,100mV/step
|
||||
;----------------------------------------------------------------------------------
|
||||
[power_sply]
|
||||
dcdc2_vol = 1001000
|
||||
aldo1_vol = 1001800
|
||||
dldo1_vol = 1003300
|
||||
cldo1_vol = 1001800
|
||||
|
||||
[axp1530_power_sply]
|
||||
dcdc2_vol = 1001000
|
||||
aldo1_vol = 1001800
|
||||
dldo1_vol = 1003300
|
||||
cldo1_vol = 1001800
|
||||
|
||||
[axp806_power_sply]
|
||||
dcdce_vol = 1003300
|
||||
;dcdcd_vol = 1001110
|
||||
aldo1_vol = 1003300
|
||||
bldo1_vol = 1001800
|
||||
bldo2_vol = 1001800
|
||||
cldo1_vol = 1001800
|
||||
|
||||
[card_boot]
|
||||
logical_start = 40960
|
||||
sprite_gpio0 =
|
||||
|
||||
;----------------------------------------------------------------------------------
|
||||
; ir_boot_recovery_used : 1: used this function 0: not used
|
||||
; ir_work_mode : 模式选择
|
||||
; 0: 刷机,
|
||||
; 1: 一键恢复(uboot阶段),
|
||||
; 2: 安卓recovery,
|
||||
; 3: 安卓恢复出厂设置.
|
||||
; 如果不设置，默认为安卓recovery .
|
||||
; ir_press_times : ir遥控器连续按几次才生效,如果不设置默认为按1次生效
|
||||
; ir_detect_time : ir遥控检测时间,单位:ms,如果不设置默认为3000ms
|
||||
; ir_key_no_duplicate : ir遥控按键是否可重复，0：可重复(默认)，1：不可重复；
|
||||
; 不可重复表示一个按键无论被按下几次，都只算ir_press_times的一次；
|
||||
; 不可重复的应用场景为组合按键功能，如:交替按下'菜单键'和'音量-键'进入安卓recovery.
|
||||
; ir_recovery_key_code0 : ir check key code
|
||||
; ir_addr_code0 : ir key addr
|
||||
; you can increase ir support num, like:
|
||||
; ir_recovery_key_code1, or 2, 3, but limit to 16
|
||||
;----------------------------------------------------------------------------------
|
||||
|
||||
[ir_boot_recovery]
|
||||
ir_boot_recovery_used = 1
|
||||
ir_work_mode = 1
|
||||
ir_press_times = 2
|
||||
ir_detect_time = 1
|
||||
ir_key_no_duplicate = 0
|
||||
ir_recovery_key_code0 = 0x11
|
||||
ir_addr_code0 = 0xfe01
|
||||
ir_recovery_key_code1 = 0x19
|
||||
ir_addr_code1 = 0xfe01
|
||||
ir_recovery_key_code2 = 0x4c
|
||||
ir_addr_code2 = 0xfe01
|
||||
ir_recovery_key_code3 = 0x00
|
||||
ir_addr_code3 = 0xfe01
|
||||
|
||||
|
||||
;----------------------------------------------------------------------------------
|
||||
; recovery_key_used : 模块使能端， 1：开启，0：关闭
|
||||
; press_mode_enable : 长短按模式使能，1：开启，0：关闭
|
||||
; a)如果开启了该模式，则key_work_mode失效，short_press_mode和long_press_mode生>效,
|
||||
; recovery按键可以通过长按和短按来触发两种不同的模式;
|
||||
; b)如果关闭了该模式，则key_work_mode生效，recovery按键只能触发一种模式.
|
||||
; key_work_mode : 模式选择
|
||||
; 0: 刷机,
|
||||
; 1: 一键恢复(uboot阶段),
|
||||
; 2: 安卓recovery,
|
||||
; 3: 安卓恢复出厂设置.
|
||||
; 如果不设置，模式为安卓recovery.
|
||||
; short_press_mode : 长按触发的模式，选项同上.
|
||||
; long_press_mode : 短按触发的模式，选项同上.
|
||||
; key_press_time : 定义长按的时间，单位:毫秒.
|
||||
; recovery_key : 按键配置.
|
||||
;----------------------------------------------------------------------------------
|
||||
[key_boot_recovery]
|
||||
recovery_key_used = 1
|
||||
press_mode_enable = 0
|
||||
key_work_mode = 0
|
||||
short_press_mode = 0
|
||||
long_press_mode = 1
|
||||
key_press_time = 2000
|
||||
recovery_key =
|
||||
|
||||
|
||||
;---------------------------------------------------------------------------------------------------------
|
||||
; if 1 == standby_mode, then support super standby;
|
||||
; else, support normal standby.
|
||||
;---------------------------------------------------------------------------------------------------------
|
||||
[pm_para]
|
||||
standby_mode = 1
|
||||
|
||||
[card0_boot_para]
|
||||
card_ctrl = 0
|
||||
card_high_speed = 1
|
||||
card_line = 4
|
||||
sdc_d1 = port:PF0<2><1><3><default>
|
||||
sdc_d0 = port:PF1<2><1><3><default>
|
||||
sdc_clk = port:PF2<2><1><3><default>
|
||||
sdc_cmd = port:PF3<2><1><3><default>
|
||||
sdc_d3 = port:PF4<2><1><3><default>
|
||||
sdc_d2 = port:PF5<2><1><3><default>
|
||||
;sdc_type = "tm1"
|
||||
|
||||
[card2_boot_para]
|
||||
card_ctrl = 2
|
||||
card_high_speed = 1
|
||||
card_line = 8
|
||||
sdc_clk = port:PC5<3><1><3><default>
|
||||
sdc_cmd = port:PC6<3><1><3><default>
|
||||
sdc_d0 = port:PC10<3><1><3><default>
|
||||
sdc_d1 = port:PC13<3><1><3><default>
|
||||
sdc_d2 = port:PC15<3><1><3><default>
|
||||
sdc_d3 = port:PC8<3><1><3><default>
|
||||
sdc_d4 = port:PC9<3><1><3><default>
|
||||
sdc_d5 = port:PC11<3><1><3><default>
|
||||
sdc_d6 = port:PC14<3><1><3><default>
|
||||
sdc_d7 = port:PC16<3><1><3><default>
|
||||
sdc_emmc_rst = port:PC1<3><1><3><default>
|
||||
sdc_ds = port:PC0<3><2><3><default>
|
||||
sdc_ex_dly_used = 2
|
||||
sdc_io_1v8 = 1
|
||||
;sdc_dis_host_caps = 0x100
|
||||
;sdc_type = "tm4"
|
||||
|
||||
[gpio_bias]
|
||||
pc_bias = 1800
|
||||
|
||||
[twi_para]
|
||||
twi_port = 0
|
||||
twi_scl = port:PH14<2><default><default><default>
|
||||
twi_sda = port:PH15<2><default><default><default>
|
||||
|
||||
[auto_print]
|
||||
auto_print_used = 1
|
||||
|
||||
[uart_para]
|
||||
uart_debug_port = 0
|
||||
uart_debug_tx = port:PH00<2><1><default><default>
|
||||
uart_debug_rx = port:PH01<2><1><default><default>
|
||||
|
||||
[jtag_para]
|
||||
jtag_enable = 0
|
||||
jtag_ms = port:PH9<3><default><default><default>
|
||||
jtag_ck = port:PH10<3><default><default><default>
|
||||
jtag_do = port:PH11<3><default><default><default>
|
||||
jtag_di = port:PH12<3><default><default><default>
|
||||
|
||||
[clock]
|
||||
pll4 = 300
|
||||
pll6 = 600
|
||||
pll8 = 360
|
||||
pll9 = 297
|
||||
pll10 = 264
|
||||
|
||||
;*****************************************************************************
|
||||
;
|
||||
;dram select configuration
|
||||
;
|
||||
;select_mode : dram模式选择, 0:不进行自动识别
|
||||
; 1:gpio识别模式(dram_para, dram_para1-15, 共16组有效)
|
||||
; 2:gpadc识别模式(dram_para, dram_para1-7, 共8组有效)
|
||||
; 3:1个IO+gpadc识别模式(dram_para, dram_para1-15, 共16组有效)。其中IO配置优先级按select_gpio0>select_gpio1>select_gpio2>select_gpio3
|
||||
;gpadc_channel : 选择gpadc通道 有效值(0-3)
|
||||
;select_gpio1-4 : 选择gpio pin
|
||||
;*****************************************************************************
|
||||
|
||||
|
||||
[dram_select_para]
|
||||
select_mode = 0
|
||||
gpadc_channel = 1
|
||||
select_gpio0 =
|
||||
select_gpio1 =
|
||||
select_gpio2 =
|
||||
select_gpio3 =
|
||||
|
||||
;*****************************************************************************
|
||||
;sdram configuration
|
||||
;
|
||||
;*****************************************************************************
|
||||
[dram_para]
|
||||
dram_clk = 792
|
||||
dram_type = 8
|
||||
dram_dx_odt = 0x07070707
|
||||
dram_dx_dri = 0x0e0e0e0e
|
||||
dram_ca_dri = 0x0e0e
|
||||
dram_odt_en = 0xaaaaeeee
|
||||
dram_para1 = 0x30fa
|
||||
dram_para2 = 0x0000
|
||||
dram_mr0 = 0x0
|
||||
dram_mr1 = 0x34
|
||||
dram_mr2 = 0x1b
|
||||
dram_mr3 = 0x33
|
||||
dram_mr4 = 0x3
|
||||
dram_mr5 = 0x0
|
||||
dram_mr6 = 0x0
|
||||
dram_mr11 = 0x4
|
||||
dram_mr12 = 0x72
|
||||
dram_mr13 = 0x0
|
||||
dram_mr14 = 0x9
|
||||
dram_mr16 = 0x0
|
||||
dram_mr17 = 0x0
|
||||
dram_mr22 = 0x24
|
||||
dram_tpr0 = 0x0
|
||||
dram_tpr1 = 0x0
|
||||
dram_tpr2 = 0x0
|
||||
dram_tpr3 = 0x0
|
||||
dram_tpr6 = 0x35808080
|
||||
dram_tpr10 = 0x402f6663
|
||||
dram_tpr11 = 0x36363535
|
||||
dram_tpr12 = 0x10101110
|
||||
dram_tpr13 = 0x2080C60
|
||||
|
||||
[dram_para1]
|
||||
|
||||
dram_clk = 720
|
||||
dram_type = 3
|
||||
dram_dx_odt = 0x08080808
|
||||
dram_dx_dri = 0x0e0e0e0e
|
||||
dram_ca_dri = 0x0e0e
|
||||
dram_odt_en = 1
|
||||
dram_para1 = 0x30FA
|
||||
dram_para2 = 0x1000
|
||||
dram_mr0 = 0x840
|
||||
dram_mr1 = 0x4
|
||||
dram_mr2 = 0x8
|
||||
dram_mr3 = 0x0
|
||||
dram_mr4 = 0x0
|
||||
dram_mr5 = 0x0
|
||||
dram_mr6 = 0x0
|
||||
dram_mr11 = 0x0
|
||||
dram_mr12 = 0x0
|
||||
dram_mr13 = 0x0
|
||||
dram_mr14 = 0x0
|
||||
dram_mr16 = 0x0
|
||||
dram_mr17 = 0x0
|
||||
dram_mr22 = 0x0
|
||||
dram_tpr0 = 0x0
|
||||
dram_tpr1 = 0x0
|
||||
dram_tpr2 = 0x0
|
||||
dram_tpr3 = 0x0
|
||||
dram_tpr6 = 0x33808080
|
||||
dram_tpr10 = 0x00f83438
|
||||
dram_tpr11 = 0x0
|
||||
dram_tpr12 = 0x0
|
||||
dram_tpr13 = 0x40
|
||||
|
||||
[dram_para2]
|
||||
|
||||
dram_clk = 720
|
||||
dram_type = 3
|
||||
dram_dx_odt = 0x08080808
|
||||
dram_dx_dri = 0x0e0e0e0e
|
||||
dram_ca_dri = 0x0e0e
|
||||
dram_odt_en = 1
|
||||
dram_para1 = 0x30FA
|
||||
dram_para2 = 0x1000
|
||||
dram_mr0 = 0x840
|
||||
dram_mr1 = 0x4
|
||||
dram_mr2 = 0x8
|
||||
dram_mr3 = 0x0
|
||||
dram_mr4 = 0x0
|
||||
dram_mr5 = 0x0
|
||||
dram_mr6 = 0x0
|
||||
dram_mr11 = 0x0
|
||||
dram_mr12 = 0x0
|
||||
dram_mr13 = 0x0
|
||||
dram_mr14 = 0x0
|
||||
dram_mr16 = 0x0
|
||||
dram_mr17 = 0x0
|
||||
dram_mr22 = 0x0
|
||||
dram_tpr0 = 0x0
|
||||
dram_tpr1 = 0x0
|
||||
dram_tpr2 = 0x0
|
||||
dram_tpr3 = 0x0
|
||||
dram_tpr6 = 0x33808080
|
||||
dram_tpr10 = 0x00f83438
|
||||
dram_tpr11 = 0x0
|
||||
dram_tpr12 = 0x0
|
||||
dram_tpr13 = 0x40
|
||||
|
||||
[dram_para3]
|
||||
|
||||
dram_clk = 720
|
||||
dram_type = 3
|
||||
dram_dx_odt = 0x08080808
|
||||
dram_dx_dri = 0x0e0e0e0e
|
||||
dram_ca_dri = 0x0e0e
|
||||
dram_odt_en = 1
|
||||
dram_para1 = 0x30FA
|
||||
dram_para2 = 0x1000
|
||||
dram_mr0 = 0x840
|
||||
dram_mr1 = 0x4
|
||||
dram_mr2 = 0x8
|
||||
dram_mr3 = 0x0
|
||||
dram_mr4 = 0x0
|
||||
dram_mr5 = 0x0
|
||||
dram_mr6 = 0x0
|
||||
dram_mr11 = 0x0
|
||||
dram_mr12 = 0x0
|
||||
dram_mr13 = 0x0
|
||||
dram_mr14 = 0x0
|
||||
dram_mr16 = 0x0
|
||||
dram_mr17 = 0x0
|
||||
dram_mr22 = 0x0
|
||||
dram_tpr0 = 0x0
|
||||
dram_tpr1 = 0x0
|
||||
dram_tpr2 = 0x0
|
||||
dram_tpr3 = 0x0
|
||||
dram_tpr6 = 0x33808080
|
||||
dram_tpr10 = 0x00f83438
|
||||
dram_tpr11 = 0x0
|
||||
dram_tpr12 = 0x0
|
||||
dram_tpr13 = 0x40
|
||||
|
||||
[dram_para4]
|
||||
|
||||
dram_clk = 720
|
||||
dram_type = 3
|
||||
dram_dx_odt = 0x08080808
|
||||
dram_dx_dri = 0x0e0e0e0e
|
||||
dram_ca_dri = 0x0e0e
|
||||
dram_odt_en = 1
|
||||
dram_para1 = 0x30FA
|
||||
dram_para2 = 0x1000
|
||||
dram_mr0 = 0x840
|
||||
dram_mr1 = 0x4
|
||||
dram_mr2 = 0x8
|
||||
dram_mr3 = 0x0
|
||||
dram_mr4 = 0x0
|
||||
dram_mr5 = 0x0
|
||||
dram_mr6 = 0x0
|
||||
dram_mr11 = 0x0
|
||||
dram_mr12 = 0x0
|
||||
dram_mr13 = 0x0
|
||||
dram_mr14 = 0x0
|
||||
dram_mr16 = 0x0
|
||||
dram_mr17 = 0x0
|
||||
dram_mr22 = 0x0
|
||||
dram_tpr0 = 0x0
|
||||
dram_tpr1 = 0x0
|
||||
dram_tpr2 = 0x0
|
||||
dram_tpr3 = 0x0
|
||||
dram_tpr6 = 0x33808080
|
||||
dram_tpr10 = 0x00f83438
|
||||
dram_tpr11 = 0x0
|
||||
dram_tpr12 = 0x0
|
||||
dram_tpr13 = 0x40
|
||||
|
||||
[dram_para5]
|
||||
|
||||
dram_clk = 720
|
||||
dram_type = 3
|
||||
dram_dx_odt = 0x08080808
|
||||
dram_dx_dri = 0x0e0e0e0e
|
||||
dram_ca_dri = 0x0e0e
|
||||
dram_odt_en = 1
|
||||
dram_para1 = 0x30FA
|
||||
dram_para2 = 0x1000
|
||||
dram_mr0 = 0x840
|
||||
dram_mr1 = 0x4
|
||||
dram_mr2 = 0x8
|
||||
dram_mr3 = 0x0
|
||||
dram_mr4 = 0x0
|
||||
dram_mr5 = 0x0
|
||||
dram_mr6 = 0x0
|
||||
dram_mr11 = 0x0
|
||||
dram_mr12 = 0x0
|
||||
dram_mr13 = 0x0
|
||||
dram_mr14 = 0x0
|
||||
dram_mr16 = 0x0
|
||||
dram_mr17 = 0x0
|
||||
dram_mr22 = 0x0
|
||||
dram_tpr0 = 0x0
|
||||
dram_tpr1 = 0x0
|
||||
dram_tpr2 = 0x0
|
||||
dram_tpr3 = 0x0
|
||||
dram_tpr6 = 0x33808080
|
||||
dram_tpr10 = 0x00f83438
|
||||
dram_tpr11 = 0x0
|
||||
dram_tpr12 = 0x0
|
||||
dram_tpr13 = 0x40
|
||||
|
||||
[dram_para6]
|
||||
|
||||
dram_clk = 720
|
||||
dram_type = 3
|
||||
dram_dx_odt = 0x08080808
|
||||
dram_dx_dri = 0x0e0e0e0e
|
||||
dram_ca_dri = 0x0e0e
|
||||
dram_odt_en = 1
|
||||
dram_para1 = 0x30FA
|
||||
dram_para2 = 0x1000
|
||||
dram_mr0 = 0x840
|
||||
dram_mr1 = 0x4
|
||||
dram_mr2 = 0x8
|
||||
dram_mr3 = 0x0
|
||||
dram_mr4 = 0x0
|
||||
dram_mr5 = 0x0
|
||||
dram_mr6 = 0x0
|
||||
dram_mr11 = 0x0
|
||||
dram_mr12 = 0x0
|
||||
dram_mr13 = 0x0
|
||||
dram_mr14 = 0x0
|
||||
dram_mr16 = 0x0
|
||||
dram_mr17 = 0x0
|
||||
dram_mr22 = 0x0
|
||||
dram_tpr0 = 0x0
|
||||
dram_tpr1 = 0x0
|
||||
dram_tpr2 = 0x0
|
||||
dram_tpr3 = 0x0
|
||||
dram_tpr6 = 0x33808080
|
||||
dram_tpr10 = 0x00f83438
|
||||
dram_tpr11 = 0x0
|
||||
dram_tpr12 = 0x0
|
||||
dram_tpr13 = 0x40
|
||||
|
||||
[dram_para7]
|
||||
|
||||
dram_clk = 720
|
||||
dram_type = 3
|
||||
dram_dx_odt = 0x08080808
|
||||
dram_dx_dri = 0x0e0e0e0e
|
||||
dram_ca_dri = 0x0e0e
|
||||
dram_odt_en = 1
|
||||
dram_para1 = 0x30FA
|
||||
dram_para2 = 0x1000
|
||||
dram_mr0 = 0x840
|
||||
dram_mr1 = 0x4
|
||||
dram_mr2 = 0x8
|
||||
dram_mr3 = 0x0
|
||||
dram_mr4 = 0x0
|
||||
dram_mr5 = 0x0
|
||||
dram_mr6 = 0x0
|
||||
dram_mr11 = 0x0
|
||||
dram_mr12 = 0x0
|
||||
dram_mr13 = 0x0
|
||||
dram_mr14 = 0x0
|
||||
dram_mr16 = 0x0
|
||||
dram_mr17 = 0x0
|
||||
dram_mr22 = 0x0
|
||||
dram_tpr0 = 0x0
|
||||
dram_tpr1 = 0x0
|
||||
dram_tpr2 = 0x0
|
||||
dram_tpr3 = 0x0
|
||||
dram_tpr6 = 0x33808080
|
||||
dram_tpr10 = 0x00f83438
|
||||
dram_tpr11 = 0x0
|
||||
dram_tpr12 = 0x0
|
||||
dram_tpr13 = 0x40
|
||||
|
||||
[dram_para8]
|
||||
|
||||
dram_clk = 720
|
||||
dram_type = 3
|
||||
dram_dx_odt = 0x08080808
|
||||
dram_dx_dri = 0x0e0e0e0e
|
||||
dram_ca_dri = 0x0e0e
|
||||
dram_odt_en = 1
|
||||
dram_para1 = 0x30FA
|
||||
dram_para2 = 0x1000
|
||||
dram_mr0 = 0x840
|
||||
dram_mr1 = 0x4
|
||||
dram_mr2 = 0x8
|
||||
dram_mr3 = 0x0
|
||||
dram_mr4 = 0x0
|
||||
dram_mr5 = 0x0
|
||||
dram_mr6 = 0x0
|
||||
dram_mr11 = 0x0
|
||||
dram_mr12 = 0x0
|
||||
dram_mr13 = 0x0
|
||||
dram_mr14 = 0x0
|
||||
dram_mr16 = 0x0
|
||||
dram_mr17 = 0x0
|
||||
dram_mr22 = 0x0
|
||||
dram_tpr0 = 0x0
|
||||
dram_tpr1 = 0x0
|
||||
dram_tpr2 = 0x0
|
||||
dram_tpr3 = 0x0
|
||||
dram_tpr6 = 0x33808080
|
||||
dram_tpr10 = 0x00f83438
|
||||
dram_tpr11 = 0x0
|
||||
dram_tpr12 = 0x0
|
||||
dram_tpr13 = 0x40
|
||||
|
||||
[dram_para9]
|
||||
|
||||
dram_clk = 720
|
||||
dram_type = 3
|
||||
dram_dx_odt = 0x08080808
|
||||
dram_dx_dri = 0x0e0e0e0e
|
||||
dram_ca_dri = 0x0e0e
|
||||
dram_odt_en = 1
|
||||
dram_para1 = 0x30FA
|
||||
dram_para2 = 0x1000
|
||||
dram_mr0 = 0x840
|
||||
dram_mr1 = 0x4
|
||||
dram_mr2 = 0x8
|
||||
dram_mr3 = 0x0
|
||||
dram_mr4 = 0x0
|
||||
dram_mr5 = 0x0
|
||||
dram_mr6 = 0x0
|
||||
dram_mr11 = 0x0
|
||||
dram_mr12 = 0x0
|
||||
dram_mr13 = 0x0
|
||||
dram_mr14 = 0x0
|
||||
dram_mr16 = 0x0
|
||||
dram_mr17 = 0x0
|
||||
dram_mr22 = 0x0
|
||||
dram_tpr0 = 0x0
|
||||
dram_tpr1 = 0x0
|
||||
dram_tpr2 = 0x0
|
||||
dram_tpr3 = 0x0
|
||||
dram_tpr6 = 0x33808080
|
||||
dram_tpr10 = 0x00f83438
|
||||
dram_tpr11 = 0x0
|
||||
dram_tpr12 = 0x0
|
||||
dram_tpr13 = 0x40
|
||||
|
||||
[dram_para10]
|
||||
|
||||
dram_clk = 720
|
||||
dram_type = 3
|
||||
dram_dx_odt = 0x08080808
|
||||
dram_dx_dri = 0x0e0e0e0e
|
||||
dram_ca_dri = 0x0e0e
|
||||
dram_odt_en = 1
|
||||
dram_para1 = 0x30FA
|
||||
dram_para2 = 0x1000
|
||||
dram_mr0 = 0x840
|
||||
dram_mr1 = 0x4
|
||||
dram_mr2 = 0x8
|
||||
dram_mr3 = 0x0
|
||||
dram_mr4 = 0x0
|
||||
dram_mr5 = 0x0
|
||||
dram_mr6 = 0x0
|
||||
dram_mr11 = 0x0
|
||||
dram_mr12 = 0x0
|
||||
dram_mr13 = 0x0
|
||||
dram_mr14 = 0x0
|
||||
dram_mr16 = 0x0
|
||||
dram_mr17 = 0x0
|
||||
dram_mr22 = 0x0
|
||||
dram_tpr0 = 0x0
|
||||
dram_tpr1 = 0x0
|
||||
dram_tpr2 = 0x0
|
||||
dram_tpr3 = 0x0
|
||||
dram_tpr6 = 0x33808080
|
||||
dram_tpr10 = 0x00f83438
|
||||
dram_tpr11 = 0x0
|
||||
dram_tpr12 = 0x0
|
||||
dram_tpr13 = 0x40
|
||||
|
||||
[dram_para11]
|
||||
|
||||
dram_clk = 720
|
||||
dram_type = 3
|
||||
dram_dx_odt = 0x08080808
|
||||
dram_dx_dri = 0x0e0e0e0e
|
||||
dram_ca_dri = 0x0e0e
|
||||
dram_odt_en = 1
|
||||
dram_para1 = 0x30FA
|
||||
dram_para2 = 0x1000
|
||||
dram_mr0 = 0x840
|
||||
dram_mr1 = 0x4
|
||||
dram_mr2 = 0x8
|
||||
dram_mr3 = 0x0
|
||||
dram_mr4 = 0x0
|
||||
dram_mr5 = 0x0
|
||||
dram_mr6 = 0x0
|
||||
dram_mr11 = 0x0
|
||||
dram_mr12 = 0x0
|
||||
dram_mr13 = 0x0
|
||||
dram_mr14 = 0x0
|
||||
dram_mr16 = 0x0
|
||||
dram_mr17 = 0x0
|
||||
dram_mr22 = 0x0
|
||||
dram_tpr0 = 0x0
|
||||
dram_tpr1 = 0x0
|
||||
dram_tpr2 = 0x0
|
||||
dram_tpr3 = 0x0
|
||||
dram_tpr6 = 0x33808080
|
||||
dram_tpr10 = 0x00f83438
|
||||
dram_tpr11 = 0x0
|
||||
dram_tpr12 = 0x0
|
||||
dram_tpr13 = 0x40
|
||||
|
||||
[dram_para12]
|
||||
|
||||
dram_clk = 720
|
||||
dram_type = 3
|
||||
dram_dx_odt = 0x08080808
|
||||
dram_dx_dri = 0x0e0e0e0e
|
||||
dram_ca_dri = 0x0e0e
|
||||
dram_odt_en = 1
|
||||
dram_para1 = 0x30FA
|
||||
dram_para2 = 0x1000
|
||||
dram_mr0 = 0x840
|
||||
dram_mr1 = 0x4
|
||||
dram_mr2 = 0x8
|
||||
dram_mr3 = 0x0
|
||||
dram_mr4 = 0x0
|
||||
dram_mr5 = 0x0
|
||||
dram_mr6 = 0x0
|
||||
dram_mr11 = 0x0
|
||||
dram_mr12 = 0x0
|
||||
dram_mr13 = 0x0
|
||||
dram_mr14 = 0x0
|
||||
dram_mr16 = 0x0
|
||||
dram_mr17 = 0x0
|
||||
dram_mr22 = 0x0
|
||||
dram_tpr0 = 0x0
|
||||
dram_tpr1 = 0x0
|
||||
dram_tpr2 = 0x0
|
||||
dram_tpr3 = 0x0
|
||||
dram_tpr6 = 0x33808080
|
||||
dram_tpr10 = 0x00f83438
|
||||
dram_tpr11 = 0x0
|
||||
dram_tpr12 = 0x0
|
||||
dram_tpr13 = 0x40
|
||||
|
||||
[dram_para13]
|
||||
|
||||
dram_clk = 720
|
||||
dram_type = 3
|
||||
dram_dx_odt = 0x08080808
|
||||
dram_dx_dri = 0x0e0e0e0e
|
||||
dram_ca_dri = 0x0e0e
|
||||
dram_odt_en = 1
|
||||
dram_para1 = 0x30FA
|
||||
dram_para2 = 0x1000
|
||||
dram_mr0 = 0x840
|
||||
dram_mr1 = 0x4
|
||||
dram_mr2 = 0x8
|
||||
dram_mr3 = 0x0
|
||||
dram_mr4 = 0x0
|
||||
dram_mr5 = 0x0
|
||||
dram_mr6 = 0x0
|
||||
dram_mr11 = 0x0
|
||||
dram_mr12 = 0x0
|
||||
dram_mr13 = 0x0
|
||||
dram_mr14 = 0x0
|
||||
dram_mr16 = 0x0
|
||||
dram_mr17 = 0x0
|
||||
dram_mr22 = 0x0
|
||||
dram_tpr0 = 0x0
|
||||
dram_tpr1 = 0x0
|
||||
dram_tpr2 = 0x0
|
||||
dram_tpr3 = 0x0
|
||||
dram_tpr6 = 0x33808080
|
||||
dram_tpr10 = 0x00f83438
|
||||
dram_tpr11 = 0x0
|
||||
dram_tpr12 = 0x0
|
||||
dram_tpr13 = 0x40
|
||||
|
||||
[dram_para14]
|
||||
|
||||
dram_clk = 720
|
||||
dram_type = 3
|
||||
dram_dx_odt = 0x08080808
|
||||
dram_dx_dri = 0x0e0e0e0e
|
||||
dram_ca_dri = 0x0e0e
|
||||
dram_odt_en = 1
|
||||
dram_para1 = 0x30FA
|
||||
dram_para2 = 0x1000
|
||||
dram_mr0 = 0x840
|
||||
dram_mr1 = 0x4
|
||||
dram_mr2 = 0x8
|
||||
dram_mr3 = 0x0
|
||||
dram_mr4 = 0x0
|
||||
dram_mr5 = 0x0
|
||||
dram_mr6 = 0x0
|
||||
dram_mr11 = 0x0
|
||||
dram_mr12 = 0x0
|
||||
dram_mr13 = 0x0
|
||||
dram_mr14 = 0x0
|
||||
dram_mr16 = 0x0
|
||||
dram_mr17 = 0x0
|
||||
dram_mr22 = 0x0
|
||||
dram_tpr0 = 0x0
|
||||
dram_tpr1 = 0x0
|
||||
dram_tpr2 = 0x0
|
||||
dram_tpr3 = 0x0
|
||||
dram_tpr6 = 0x33808080
|
||||
dram_tpr10 = 0x00f83438
|
||||
dram_tpr11 = 0x0
|
||||
dram_tpr12 = 0x0
|
||||
dram_tpr13 = 0x40
|
||||
|
||||
[dram_para15]
|
||||
|
||||
dram_clk = 720
|
||||
dram_type = 3
|
||||
dram_dx_odt = 0x08080808
|
||||
dram_dx_dri = 0x0e0e0e0e
|
||||
dram_ca_dri = 0x0e0e
|
||||
dram_odt_en = 1
|
||||
dram_para1 = 0x30FA
|
||||
dram_para2 = 0x1000
|
||||
dram_mr0 = 0x840
|
||||
dram_mr1 = 0x4
|
||||
dram_mr2 = 0x8
|
||||
dram_mr3 = 0x0
|
||||
dram_mr4 = 0x0
|
||||
dram_mr5 = 0x0
|
||||
dram_mr6 = 0x0
|
||||
dram_mr11 = 0x0
|
||||
dram_mr12 = 0x0
|
||||
dram_mr13 = 0x0
|
||||
dram_mr14 = 0x0
|
||||
dram_mr16 = 0x0
|
||||
dram_mr17 = 0x0
|
||||
dram_mr22 = 0x0
|
||||
dram_tpr0 = 0x0
|
||||
dram_tpr1 = 0x0
|
||||
dram_tpr2 = 0x0
|
||||
dram_tpr3 = 0x0
|
||||
dram_tpr6 = 0x33808080
|
||||
dram_tpr10 = 0x00f83438
|
||||
dram_tpr11 = 0x0
|
||||
dram_tpr12 = 0x0
|
||||
dram_tpr13 = 0x40
|
||||
|
||||
[dram_para16]
|
||||
dram_clk = 792
|
||||
dram_type = 8
|
||||
dram_dx_odt = 0x07070707
|
||||
dram_dx_dri = 0x0e0e0e0e
|
||||
dram_ca_dri = 0x0e0e
|
||||
dram_odt_en = 0xaaaaeeee
|
||||
dram_para1 = 0x30fa
|
||||
dram_para2 = 0x0000
|
||||
dram_mr0 = 0x0
|
||||
dram_mr1 = 0x34
|
||||
dram_mr2 = 0x1b
|
||||
dram_mr3 = 0x33
|
||||
dram_mr4 = 0x3
|
||||
dram_mr5 = 0x0
|
||||
dram_mr6 = 0x0
|
||||
dram_mr11 = 0x4
|
||||
dram_mr12 = 0x72
|
||||
dram_mr13 = 0x0
|
||||
dram_mr14 = 0x9
|
||||
dram_mr16 = 0x0
|
||||
dram_mr17 = 0x0
|
||||
dram_mr22 = 0x24
|
||||
dram_tpr0 = 0x0
|
||||
dram_tpr1 = 0x0
|
||||
dram_tpr2 = 0x0
|
||||
dram_tpr3 = 0x0
|
||||
dram_tpr6 = 0x35808080
|
||||
dram_tpr10 = 0x402f6663
|
||||
dram_tpr11 = 0x36363535
|
||||
dram_tpr12 = 0x10101110
|
||||
dram_tpr13 = 0x2080C60
|
||||
|
||||
;----------------------------------------------------------------------------------
|
||||
;os life cycle para configuration
|
||||
;----------------------------------------------------------------------------------
|
||||
|
||||
;----------------------------------------------------------------------------------
|
||||
;uart configuration
|
||||
;uart_type --- 2 (2 wire), 4 (4 wire), 8 (8 wire, full function)
|
||||
;----------------------------------------------------------------------------------
|
||||
[uart0]
|
||||
uart0_used = 1
|
||||
uart0_port = 0
|
||||
uart0_type = 2
|
||||
uart0_tx = port:PH00<2><1><default><default>
|
||||
uart0_rx = port:PH01<2><1><default><default>
|
||||
|
||||
[nand0_para]
|
||||
nand0_support_2ch = 0
|
||||
|
||||
nand0_used = 0
|
||||
nand0_we = port:PC00<2><0><1><default>
|
||||
nand0_ale = port:PC01<2><0><1><default>
|
||||
nand0_cle = port:PC02<2><0><1><default>
|
||||
nand0_ce0 = port:PC03<2><1><1><default>
|
||||
nand0_nre = port:PC04<2><0><1><default>
|
||||
nand0_rb0 = port:PC05<2><1><1><default>
|
||||
nand0_d0 = port:PC06<2><0><1><default>
|
||||
nand0_d1 = port:PC07<2><0><1><default>
|
||||
nand0_d2 = port:PC08<2><0><1><default>
|
||||
nand0_d3 = port:PC09<2><0><1><default>
|
||||
nand0_d4 = port:PC10<2><0><1><default>
|
||||
nand0_d5 = port:PC11<2><0><1><default>
|
||||
nand0_d6 = port:PC12<2><0><1><default>
|
||||
nand0_d7 = port:PC13<2><0><1><default>
|
||||
nand0_ndqs = port:PC14<2><0><1><default>
|
||||
nand0_ce1 = port:PC15<2><1><1><default>
|
||||
nand0_rb1 = port:PC16<2><1><1><default>
|
||||
|
||||
nand0_regulator1 = "vcc-nand"
|
||||
nand0_regulator2 = "none"
|
||||
nand0_cache_level = 0x55aaaa55
|
||||
nand0_flush_cache_num = 0x55aaaa55
|
||||
nand0_capacity_level = 0x55aaaa55
|
||||
nand0_id_number_ctl = 0x55aaaa55
|
||||
nand0_print_level = 0x55aaaa55
|
||||
nand0_p0 = 0x55aaaa55
|
||||
nand0_p1 = 0x55aaaa55
|
||||
nand0_p2 = 0x55aaaa55
|
||||
nand0_p3 = 0x55aaaa55
|
||||
|
||||
[secure]
|
||||
dram_region_mbytes = 80
|
||||
drm_region_mbytes = 0
|
||||
drm_region_start_mbytes = 0
|
||||
BIN
external/packages/pack-uboot/sun50iw9/tools/update_chip
vendored
Executable file
BIN
external/packages/pack-uboot/sun50iw9/tools/update_chip
vendored
Executable file
Binary file not shown.
Reference in New Issue
Block a user