# 1 "arch/arm64/boot/dts/sunxi/sun50iw6p1-soc.dts"
# 1 "<built-in>"
# 1 "<command-line>"
# 1 "arch/arm64/boot/dts/sunxi/sun50iw6p1-soc.dts"






/dts-v1/;

# 1 "arch/arm64/boot/dts/sunxi/sun50iw6p1.dtsi" 1







/memreserve/ 0x40020000 0x00000800;
/memreserve/ 0x48000000 0x01000000;


/memreserve/ 0x48100000 0x00004000;
/memreserve/ 0x48104000 0x00001000;
/memreserve/ 0x48105000 0x00001000;

# 1 "./arch/arm64/boot/dts/include/dt-bindings/interrupt-controller/arm-gic.h" 1







# 1 "./arch/arm64/boot/dts/include/dt-bindings/interrupt-controller/irq.h" 1
# 9 "./arch/arm64/boot/dts/include/dt-bindings/interrupt-controller/arm-gic.h" 2
# 17 "arch/arm64/boot/dts/sunxi/sun50iw6p1.dtsi" 2
# 1 "./arch/arm64/boot/dts/include/dt-bindings/gpio/gpio.h" 1
# 18 "arch/arm64/boot/dts/sunxi/sun50iw6p1.dtsi" 2
# 1 "arch/arm64/boot/dts/sunxi/sun50iw6p1-clk.dtsi" 1
/{
clocks {
 compatible = "allwinner,clk-init";
 device_type = "clocks";
 #address-cells = <2>;
 #size-cells = <2>;
 ranges;
 reg = <0x0 0x03001000 0x0 0x1000>,
       <0x0 0x07010000 0x0 0x400>,
       <0x0 0x07000000 0x0 0x4>;


  clk_losc: losc {
   #clock-cells = <0>;
   compatible = "allwinner,fixed-clock";
   clock-frequency = <32768>;
   clock-output-names = "losc";
  };
  clk_iosc: iosc {
   #clock-cells = <0>;
   compatible = "allwinner,fixed-clock";
   clock-frequency = <16000000>;
   clock-output-names = "iosc";
  };
  clk_hosc: hosc {
   #clock-cells = <0>;
   compatible = "allwinner,fixed-clock";
   clock-frequency = <24000000>;
   clock-output-names = "hosc";
  };
  clk_osc48m: osc48m {
   #clock-cells = <0>;
   compatible = "allwinner,fixed-clock";
   clock-frequency = <48000000>;
   clock-output-names = "osc48m";
  };


  clk_pll_cpu: pll_cpu {
   #clock-cells = <0>;
   compatible = "allwinner,pll-clock";
   lock-mode = "new";
   clock-output-names = "pll_cpu";
  };
  clk_pll_ddr0: pll_ddr0 {
   #clock-cells = <0>;
   compatible = "allwinner,pll-clock";
   lock-mode = "new";
   clock-output-names = "pll_ddr0";
  };
  clk_pll_periph0: pll_periph0 {
   #clock-cells = <0>;
   compatible = "allwinner,pll-clock";
   assigned-clock-rates = <600000000>;
   lock-mode = "new";
   clock-output-names = "pll_periph0";
  };
  clk_pll_periph1: pll_periph1 {
   #clock-cells = <0>;
   compatible = "allwinner,pll-clock";
   assigned-clock-rates = <600000000>;
   lock-mode = "new";
   clock-output-names = "pll_periph1";
  };
  clk_pll_gpu: pll_gpu {
   #clock-cells = <0>;
   compatible = "allwinner,pll-clock";
   lock-mode = "new";
   clock-output-names = "pll_gpu";
  };
  clk_pll_video0: pll_video0 {
   #clock-cells = <0>;
   compatible = "allwinner,pll-clock";
   lock-mode = "new";
   clock-output-names = "pll_video0";
  };
  clk_pll_video1: pll_video1 {
   #clock-cells = <0>;
   compatible = "allwinner,pll-clock";
   lock-mode = "new";
   assigned-clock-rates = <594000000>;
   clock-output-names = "pll_video1";
  };
  clk_pll_ve: pll_ve {
   #clock-cells = <0>;
   compatible = "allwinner,pll-clock";
   device_type = "clk_pll_ve";
   lock-mode = "new";

   clock-output-names = "pll_ve";
  };
  clk_pll_de: pll_de {
   #clock-cells = <0>;
   compatible = "allwinner,pll-clock";
   assigned-clock-rates = <696000000>;
   lock-mode = "new";
   clock-output-names = "pll_de";
  };
  clk_pll_hsic: pll_hsic {
   #clock-cells = <0>;
   compatible = "allwinner,pll-clock";
   lock-mode = "new";
   clock-output-names = "pll_hsic";
  };
  clk_pll_audio: pll_audio {
   #clock-cells = <0>;
   compatible = "allwinner,pll-clock";
   lock-mode = "new";
   clock-output-names = "pll_audio";
  };


  clk_pll_periph0x2: pll_periph0x2 {
   #clock-cells = <0>;
   compatible = "allwinner,fixed-factor-clock";
   clocks = <&clk_pll_periph0>;
   clock-mult = <2>;
   clock-div = <1>;
   clock-output-names = "pll_periph0x2";
  };
  clk_pll_periph0x4: pll_periph0x4 {
   #clock-cells = <0>;
   compatible = "allwinner,fixed-factor-clock";
   clocks = <&clk_pll_periph0>;
   clock-mult = <4>;
   clock-div = <1>;
   clock-output-names = "pll_periph0x4";
  };
  clk_periph32k: periph32k {
   #clock-cells = <0>;
   compatible = "allwinner,fixed-factor-clock";
   clocks = <&clk_pll_periph0>;
   clock-mult = <2>;
   clock-div = <36621>;
   clock-output-names = "periph32k";
  };
  clk_pll_periph1x2: pll_periph1x2 {
   #clock-cells = <0>;
   compatible = "allwinner,fixed-factor-clock";
   clocks = <&clk_pll_periph1>;
   clock-mult = <2>;
   clock-div = <1>;
   clock-output-names = "pll_periph1x2";
  };
  clk_pll_audiox4: pll_audiox4 {
   #clock-cells = <0>;
   compatible = "allwinner,fixed-factor-clock";
   clocks = <&clk_pll_audio>;
   clock-mult = <4>;
   clock-div = <1>;
   clock-output-names = "pll_audiox4";
  };
  clk_pll_audiox2: pll_audiox2 {
   #clock-cells = <0>;
   compatible = "allwinner,fixed-factor-clock";
   clocks = <&clk_pll_audio>;
   clock-mult = <2>;
   clock-div = <1>;
   clock-output-names = "pll_audiox2";
  };
  clk_pll_video0x4: pll_video0x4 {
   #clock-cells = <0>;
   compatible = "allwinner,fixed-factor-clock";
   clocks = <&clk_pll_video0>;
   clock-mult = <4>;
   clock-div = <1>;
   clock-output-names = "pll_video0x4";
  };
  clk_pll_video1x4: pll_video1x4 {
   #clock-cells = <0>;
   compatible = "allwinner,fixed-factor-clock";
   clocks = <&clk_pll_video1>;
   clock-mult = <4>;
   clock-div = <1>;
   clock-output-names = "pll_video1x4";
  };
  clk_hoscd2: hoscd2 {
   #clock-cells = <0>;
   compatible = "allwinner,fixed-factor-clock";
   clocks = <&clk_hosc>;
   clock-mult = <1>;
   clock-div = <2>;
   clock-output-names = "hoscd2";
  };
  clk_osc48md4: osc48md4 {
   #clock-cells = <0>;
   compatible = "allwinner,fixed-factor-clock";
   clocks = <&clk_osc48m>;
   clock-mult = <1>;
   clock-div = <4>;
   clock-output-names = "osc48md4";
  };
  clk_pll_periph0d6: pll_periph0d6 {
   #clock-cells = <0>;
   compatible = "allwinner,fixed-factor-clock";
   clocks = <&clk_pll_periph0>;
   clock-mult = <1>;
   clock-div = <6>;
   clock-output-names = "pll_periph0d6";
  };


  clk_cpu: cpu {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "cpu";
  };
  clk_axi: axi {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "axi";
  };
  clk_cpuapb: cpuapb {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "cpuapb";
  };
  clk_psi: psi {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "psi";
  };
  clk_ahb1: ahb1 {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "ahb1";
  };
  clk_ahb2: ahb2 {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "ahb2";
  };
  clk_ahb3: ahb3 {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "ahb3";
  };
  clk_apb1: apb1 {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "apb1";
  };
  clk_apb2: apb2 {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "apb2";
  };
  clk_mbus: mbus {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "mbus";
  };
  clk_de: de {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   assigned-clock-parents = <&clk_pll_de>;
   assigned-clock-rates = <696000000>;
   assigned-clocks = <&clk_de>;
   clock-output-names = "de";
  };
  clk_di: di {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "di";
  };
  clk_gpu: gpu {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "gpu";
  };
  clk_ce: ce {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "ce";
  };
  clk_ve: ve {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "ve";
  };
  clk_emce: emce {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "emce";
  };
  clk_vp9: vp9 {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "vp9";
  };
  clk_dma: dma {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "dma";
  };
  clk_msgbox: msgbox {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "msgbox";
  };
  clk_hwspinlock_rst: hwspinlock_rst {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "hwspinlock_rst";
  };
  clk_hwspinlock_bus: hwspinlock_bus {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "hwspinlock_bus";
  };
  clk_hstimer: hstimer {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "hstimer";
  };
  clk_avs: avs {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "avs";
  };
  clk_dbgsys: dbgsys {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "dbgsys";
  };
  clk_pwm: pwm {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "pwm";
  };
  clk_iommu: iommu {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "iommu";
  };
  clk_sdram: sdram {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "sdram";
  };
  clk_nand0: nand0 {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "nand0";
  };
  clk_nand1: nand1 {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "nand1";
  };
  clk_sdmmc0_mod: sdmmc0_mod {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "sdmmc0_mod";
  };
  clk_sdmmc0_bus: sdmmc0_bus {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "sdmmc0_bus";
  };
  clk_sdmmc0_rst: sdmmc0_rst {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "sdmmc0_rst";
  };
  clk_sdmmc1_mod: sdmmc1_mod {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "sdmmc1_mod";
  };
  clk_sdmmc1_bus: sdmmc1_bus {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "sdmmc1_bus";
  };
  clk_sdmmc1_rst: sdmmc1_rst {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "sdmmc1_rst";
  };
  clk_sdmmc2_mod: sdmmc2_mod {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "sdmmc2_mod";
  };
  clk_sdmmc2_bus: sdmmc2_bus {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "sdmmc2_bus";
  };
  clk_sdmmc2_rst: sdmmc2_rst {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "sdmmc2_rst";
  };
  clk_uart0: uart0 {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "uart0";
  };
  clk_uart1: uart1 {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "uart1";
  };
  clk_uart2: uart2 {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "uart2";
  };
  clk_uart3: uart3 {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "uart3";
  };
  clk_twi0: twi0 {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "twi0";
  };
  clk_twi1: twi1 {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "twi1";
  };
  clk_twi2: twi2 {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "twi2";
  };
  clk_twi3: twi3 {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "twi3";
  };
  clk_scr0: scr0 {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "scr0";
  };
  clk_scr1: scr1 {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "scr1";
  };
  clk_spi0: spi0 {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "spi0";
  };
  clk_spi1: spi1 {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "spi1";
  };
  clk_gmac: gmac {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "gmac";
  };
  clk_sata: sata {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "sata";
  };
  clk_sata_24m: sata_24m {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "sata_24m";
  };
  clk_ts: ts {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "ts";
  };
  clk_irtx: irtx {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "irtx";
  };
  clk_ths: ths {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "ths";
  };
  clk_i2s0: i2s0 {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "i2s0";
  };
  clk_i2s1: i2s1 {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "i2s1";
  };
  clk_i2s2: i2s2 {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "i2s2";
  };
  clk_i2s3: i2s3 {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "i2s3";
  };
  clk_spdif: spdif {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "spdif";
  };
  clk_dmic: dmic {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "dmic";
  };
  clk_ahub: ahub {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "ahub";
  };
  clk_usbphy0: usbphy0 {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "usbphy0";
  };
  clk_usbphy1: usbphy1 {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "usbphy1";
  };
  clk_usbphy3: usbphy3 {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "usbphy3";
  };
  clk_usbohci0: usbohci0 {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "usbohci0";
  };
  clk_usbohci0_12m: usbohci0_12m {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "usbohci0_12m";
  };
  clk_usbohci3: usbohci3 {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "usbohci3";
  };
  clk_usbohci3_12m: usbohci3_12m {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "usbohci3_12m";
  };
  clk_usbehci0: usbehci0 {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "usbehci0";
  };
  clk_usbehci3: usbehci3 {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "usbehci3";
  };
  clk_usb3_0_host: usb3_0_host {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "usb3_0_host";
  };
  clk_usbotg: usbotg {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "usbotg";
  };
  clk_usbhsic: usbhsic {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "usbhsic";
  };
  clk_pcieref: pcieref {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "pcieref";
  };
  clk_pciemaxi: pciemaxi {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   assigned-clocks = <&clk_pciemaxi>;
   assigned-clock-rates = <200000000>;
   clock-output-names = "pciemaxi";
  };
  clk_pcieaux: pcieaux {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   assigned-clock-rates = <1000000>;
   assigned-clocks = <&clk_pcieaux>;
   clock-output-names = "pcieaux";
  };
  clk_pcie_bus: pcie_bus {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "pcie_bus";
  };
  clk_pcie_power: pcie_power {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "pcie_power";
  };
  clk_pcie_rst: pcie_rst {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "pcie_rst";
  };
  clk_hdmi: hdmi {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   assigned-clock-parents = <&clk_pll_video1>;
   assigned-clocks = <&clk_hdmi>;
   clock-output-names = "hdmi";
  };
  clk_hdmi_slow: hdmi_slow {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   assigned-clocks = <&clk_hdmi_slow>;
   clock-output-names = "hdmi_slow";
  };
  clk_hdmi_cec: hdmi_cec {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   assigned-clocks = <&clk_hdmi_cec>;
   clock-output-names = "hdmi_cec";
  };
  clk_display_top: display_top {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "display_top";
  };
  clk_tcon_lcd: tcon_lcd {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "tcon_lcd";
  };
  clk_tcon_tv: tcon_tv {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   assigned-clock-parents = <&clk_pll_video1>;
   assigned-clocks = <&clk_tcon_tv>;
   clock-output-names = "tcon_tv";
  };
  clk_csi_misc: csi_misc {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "csi_misc";
  };
  clk_csi_top: csi_top {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "csi_top";
  };
  clk_csi_master0: csi_master0 {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "csi_master0";
  };
  clk_hdmi_hdcp: hdmi_hdcp {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   assigned-clock-parents = <&clk_pll_periph1>;
   assigned-clocks = <&clk_hdmi_hdcp>;
   clock-output-names = "hdmi_hdcp";
  };
  clk_pio: pio {
   #clock-cells = <0>;
   compatible = "allwinner,periph-clock";
   clock-output-names = "pio";
  };


  clk_cpurcir: cpurcir {
   #clock-cells = <0>;
   compatible = "allwinner,periph-cpus-clock";
   clock-output-names = "cpurcir";
  };
  clk_losc_out: losc_out {
   #clock-cells = <0>;
   compatible = "allwinner,periph-cpus-clock";
   clock-output-names = "losc_out";
  };

  clk_cpurcpus_pll: cpurcpus_pll {
   #clock-cells = <0>;
   compatible = "allwinner,periph-cpus-clock";
   clock-output-names = "cpurcpus_pll";
  };
  clk_cpurcpus: cpurcpus {
   #clock-cells = <0>;
   compatible = "allwinner,periph-cpus-clock";
   clock-output-names = "cpurcpus";
  };
  clk_cpurahbs: cpurahbs {
   #clock-cells = <0>;
   compatible = "allwinner,periph-cpus-clock";
   clock-output-names = "cpurahbs";
  };
  clk_cpurapbs1: cpurapbs1 {
   #clock-cells = <0>;
   compatible = "allwinner,periph-cpus-clock";
   clock-output-names = "cpurapbs1";
  };
  clk_cpurapbs2_pll: cpurapbs2_pll {
   #clock-cells = <0>;
   compatible = "allwinner,periph-cpus-clock";
   clock-output-names = "cpurapbs2_pll";
  };
  clk_cpurapbs2: cpurapbs2 {
   #clock-cells = <0>;
   compatible = "allwinner,periph-cpus-clock";
   clock-output-names = "cpurapbs2";
  };
  clk_cpurpio: cpurpio {
   #clock-cells = <0>;
   compatible = "allwinner,periph-cpus-clock";
   clock-output-names = "cpurpio";
  };
  clk_spwm: spwm {
   #clock-cells = <0>;
   compatible = "allwinner,periph-cpus-clock";
   clock-output-names = "spwm";
  };
  clk_dcxo_out: dcxo_out {
   #clock-cells = <0>;
   compatible = "allwinner,periph-cpus-clock";
   clock-output-names = "dcxo_out";
  };
 };
};
# 19 "arch/arm64/boot/dts/sunxi/sun50iw6p1.dtsi" 2
# 1 "arch/arm64/boot/dts/sunxi/sun50iw6p1-pinctrl.dtsi" 1




/ {
 soc@03000000{
  r_pio: pinctrl@07022000 {
   compatible = "allwinner,sun50iw6p1-r-pinctrl";
   reg = <0x0 0x07022000 0x0 0x400>;
   interrupts = <0 105 4>,
   <0 111 4>;
   clocks = <&clk_cpurpio>;
   device_type = "r_pio";
   gpio-controller;
   interrupt-controller;
   #interrupt-cells = <2>;
   #size-cells = <0>;
   #gpio-cells = <6>;

   s_uart0_pins_a: s_uart0@0 {
    allwinner,pins = "PL2", "PL3";
    allwinner,function = "s_uart0";
    allwinner,muxsel = <2>;
    allwinner,drive = <1>;
    allwinner,pull = <1>;
   };

   s_twi0_pins_a: s_twi0@0 {
    allwinner,pins = "PL0", "PL1";
    allwinner,function = "s_twi0";
    allwinner,muxsel = <3>;
    allwinner,drive = <0>;
    allwinner,pull = <1>;
   };

   s_jtag0_pins_a: s_jtag0@0 {
    allwinner,pins = "PL4", "PL5", "PL6", "PL7";
    allwinner,function = "s_jtag0";
    allwinner,muxsel = <2>;
    allwinner,drive = <2>;
    allwinner,pull = <1>;
   };

   s_cir0_pins_a: s_cir0@0 {
    allwinner,pins = "PL9";
    allwinner,function = "s_cir0";
    allwinner,muxsel = <2>;
    allwinner,drive = <2>;
    allwinner,pull = <1>;
   };
  };

  pio: pinctrl@0300b000 {
   compatible = "allwinner,sun50iw6p1-pinctrl";
   reg = <0x0 0x0300b000 0x0 0x400>;
   interrupts = <0 51 4>,
         <0 53 4>,
         <0 54 4>,
         <0 59 4>;
   device_type = "pio";
   clocks = <&clk_pio>;
   gpio-controller;
   interrupt-controller;
   #interrupt-cells = <2>;
   #size-cells = <0>;
   #gpio-cells = <6>;

   vdevice_pins_a: vdevice@0 {
    allwinner,pins = "PA1", "PA2";
    allwinner,function = "vdevice";
    allwinner,muxsel = <5>;
    allwinner,drive = <1>;
    allwinner,pull = <1>;
   };

   uart0_pins_a: uart0@0 {
    allwinner,pins = "PF2", "PF4";
    allwinner,pname = "uart0_tx", "uart0_rx";
    allwinner,function = "uart0";
    allwinner,muxsel = <3>;
    allwinner,drive = <1>;
    allwinner,pull = <1>;
   };

   uart0_pins_b: uart0@1 {
    allwinner,pins = "PF2", "PF4";
    allwinner,function = "io_disabled";
    allwinner,muxsel = <7>;
    allwinner,drive = <1>;
    allwinner,pull = <0>;
   };

   uart1_pins_a: uart1@0 {
    allwinner,pins = "PG6", "PG7", "PG8", "PG9";
    allwinner,pname = "uart1_tx", "uart1_rx",
        "uart1_rts", "uart1_cts";
    allwinner,function = "uart1";
    allwinner,muxsel = <2>;
    allwinner,drive = <1>;
    allwinner,pull = <1>;
   };

   uart1_pins_b: uart1@1 {
    allwinner,pins = "PG6", "PG7", "PG8", "PG9";
    allwinner,function = "io_disabled";
    allwinner,muxsel = <7>;
    allwinner,drive = <1>;
    allwinner,pull = <0>;
   };

   uart2_pins_a: uart2@0 {
    allwinner,pins = "PD19", "PD20", "PD21", "PD22";
    allwinner,pname = "uart2_tx", "uart2_rx",
        "uart2_rts", "uart2_cts";
    allwinner,function = "uart2";
    allwinner,muxsel = <4>;
    allwinner,drive = <1>;
    allwinner,pull = <1>;
   };

   uart2_pins_b: uart2@1 {
    allwinner,pins = "PD19", "PD20", "PD21", "PD22";
    allwinner,function = "io_disabled";
    allwinner,muxsel = <7>;
    allwinner,drive = <1>;
    allwinner,pull = <0>;
   };

   uart3_pins_a: uart3@0 {
    allwinner,pins = "PE0", "PE1", "PE2", "PE3";
    allwinner,pname = "uart3_tx", "uart3_rx",
        "uart3_rts", "uart3_cts";
    allwinner,function = "uart3";
    allwinner,muxsel = <3>;
    allwinner,drive = <1>;
    allwinner,pull = <1>;
   };

   uart3_pins_b: uart3@1 {
    allwinner,pins = "PE0", "PE1", "PE2", "PE3";
    allwinner,function = "io_disabled";
    allwinner,muxsel = <7>;
    allwinner,drive = <1>;
    allwinner,pull = <0>;
   };

   twi0_pins_a: twi0@0 {
    allwinner,pins = "PD25", "PD26";
    allwinner,pname = "twi0_scl", "twi0_sda";
    allwinner,function = "twi0";
    allwinner,muxsel = <2>;
    allwinner,drive = <1>;
    allwinner,pull = <0>;
   };

   twi0_pins_b: twi0@1 {
    allwinner,pins = "PD25", "PD26";
    allwinner,function = "io_disabled";
    allwinner,muxsel = <7>;
    allwinner,drive = <1>;
    allwinner,pull = <0>;
   };

   twi1_pins_a: twi1@0 {
    allwinner,pins = "PH5", "PH6";
    allwinner,pname = "twi1_scl", "twi1_sda";
    allwinner,function = "twi1";
    allwinner,muxsel = <4>;
    allwinner,drive = <1>;
    allwinner,pull = <0>;
   };

   twi1_pins_b: twi1@1 {
    allwinner,pins = "PH5", "PH6";
    allwinner,function = "io_disabled";
    allwinner,muxsel = <7>;
    allwinner,drive = <1>;
    allwinner,pull = <0>;
   };

   twi2_pins_a: twi2@0 {
    allwinner,pins = "PD23", "PD24";
    allwinner,pname = "twi2_scl", "twi2_sda";
    allwinner,function = "twi2";
    allwinner,muxsel = <2>;
    allwinner,drive = <1>;
    allwinner,pull = <0>;
   };

   twi2_pins_b: twi2@1 {
    allwinner,pins = "PD23", "PD24";
    allwinner,function = "io_disabled";
    allwinner,muxsel = <7>;
    allwinner,drive = <1>;
    allwinner,pull = <0>;
   };

   twi3_pins_a: twi3@0 {
    allwinner,pins = "PB17", "PB18";
    allwinner,pname = "twi3_scl", "twi3_sda";
    allwinner,function = "twi3";
    allwinner,muxsel = <2>;
    allwinner,drive = <1>;
    allwinner,pull = <0>;
   };

   twi3_pins_b: twi3@1 {
    allwinner,pins = "PB17", "PB18";
    allwinner,function = "io_disabled";
    allwinner,muxsel = <7>;
    allwinner,drive = <1>;
    allwinner,pull = <0>;
   };

   ts0_pins_a: ts0@0 {
    allwinner,pins = "PD0", "PD1", "PD2", "PD3",
       "PD4", "PD5", "PD6", "PD7",
       "PD8", "PD9", "PD10", "PD11";
    allwinner,pname = "ts0_clk", "ts0_err",
        "ts0_sync", "ts0_dvld",
        "ts0_d0", "ts0_d1",
        "ts0_d2", "ts0_d3",
        "ts0_d4", "ts0_d5",
        "ts0_d6", "ts0_d7";
    allwinner,function = "ts0";
    allwinner,muxsel = <3>;
    allwinner,drive = <1>;
    allwinner,pull = <0>;
   };

   ts0_pins_b: ts0_sleep@0 {
    allwinner,pins = "PD0", "PD1", "PD2", "PD3",
       "PD4", "PD5", "PD6", "PD7",
       "PD8", "PD9", "PD10", "PD11";
    allwinner,pname = "ts0_clk", "ts0_err",
        "ts0_sync", "ts0_dvld",
        "ts0_d0", "ts0_d1",
        "ts0_d2", "ts0_d3",
        "ts0_d4", "ts0_d5",
        "ts0_d6", "ts0_d7";
    allwinner,function = "io_disabled";
    allwinner,muxsel = <7>;
    allwinner,drive = <1>;
    allwinner,pull = <0>;
   };

   ts1_pins_a: ts1@0 {
    allwinner,pins = "PD12", "PD13", "PD14",
       "PD15", "PD16";
    allwinner,pname = "ts1_clk", "ts1_err",
        "ts1_sync", "ts1_dvld",
        "ts1_d0";
    allwinner,function = "ts1";
    allwinner,muxsel = <3>;
    allwinner,drive = <1>;
    allwinner,pull = <0>;
   };

   ts1_pins_b: ts1_sleep@0 {
    allwinner,pins = "PD12", "PD13", "PD14",
       "PD15", "PD16";
    allwinner,pname = "ts1_clk", "ts1_err",
        "ts1_sync", "ts1_dvld",
        "ts1_d0";
    allwinner,function = "io_disabled";
    allwinner,muxsel = <7>;
    allwinner,drive = <1>;
    allwinner,pull = <0>;
   };

   ts2_pins_a: ts2@0 {
    allwinner,pins = "PD17", "PD18", "PD19", "PD20",
       "PD21";
    allwinner,pname = "ts2_clk", "ts2_err",
        "ts2_sync", "ts2_dvld",
        "ts2_d0";
    allwinner,function = "ts2";
    allwinner,muxsel = <3>;
    allwinner,drive = <1>;
    allwinner,pull = <0>;
   };

   ts2_pins_b: ts2_sleep@0 {
    allwinner,pins = "PD17", "PD18", "PD19", "PD20",
       "PD21";
    allwinner,pname = "ts2_clk", "ts2_err",
        "ts2_sync", "ts2_dvld",
        "ts2_d0";
    allwinner,function = "io_disabled";
    allwinner,muxsel = <7>;
    allwinner,drive = <1>;
    allwinner,pull = <0>;
   };

   ts3_pins_a: ts3@0 {
    allwinner,pins = "PD22", "PD23", "PD24",
       "PD25", "PD26";
    allwinner,pname = "ts3_clk", "ts3_err",
        "ts3_sync", "ts3_dvld",
        "ts3_d0";
    allwinner,function = "ts3";
    allwinner,muxsel = <3>;
    allwinner,drive = <1>;
    allwinner,pull = <0>;
   };

   ts3_pins_b: ts3_sleep@0 {
    allwinner,pins = "PD22", "PD23", "PD24",
       "PD25", "PD26";
    allwinner,pname = "ts3_clk", "ts3_err",
        "ts3_sync", "ts3_dvld",
        "ts3_d0";
    allwinner,function = "io_disabled";
    allwinner,muxsel = <7>;
    allwinner,drive = <1>;
    allwinner,pull = <0>;
   };

   spi0_pins_a: spi0@0 {
    allwinner,pins = "PC0", "PC2", "PC3";
    allwinner,pname = "spi0_sclk", "spi0_mosi",
        "spi0_miso";
    allwinner,function = "spi0";
    allwinner,muxsel = <4>;
    allwinner,drive = <1>;
    allwinner,pull = <0>;
   };

   spi0_pins_b: spi0@1 {
    allwinner,pins = "PC5";
    allwinner,pname = "spi0_cs0";
    allwinner,function = "spi0";
    allwinner,muxsel = <4>;
    allwinner,drive = <1>;
    allwinner,pull = <1>;
   };

   spi0_pins_c: spi0@2 {
    allwinner,pins = "PC0", "PC2", "PC3", "PC5";
    allwinner,function = "io_disabled";
    allwinner,muxsel = <7>;
    allwinner,drive = <1>;
    allwinner,pull = <0>;
   };

   spi1_pins_a: spi1@0 {
    allwinner,pins = "PH4", "PH5", "PH6";
    allwinner,pname = "spi1_sclk", "spi1_mosi",
        "spi1_miso";
    allwinner,function = "spi1";
    allwinner,muxsel = <2>;
    allwinner,drive = <1>;
    allwinner,pull = <0>;
   };

   spi1_pins_b: spi1@1 {
    allwinner,pins = "PH3";
    allwinner,pname = "spi1_cs0";
    allwinner,function = "spi1";
    allwinner,muxsel = <2>;
    allwinner,drive = <1>;
    allwinner,pull = <1>;
   };

   spi1_pins_c: spi1@2 {
    allwinner,pins = "PH3", "PH4", "PH5", "PH6";
    allwinner,function = "io_disabled";
    allwinner,muxsel = <7>;
    allwinner,drive = <1>;
    allwinner,pull = <0>;
   };

   sdc0_pins_a: sdc0@0 {
    allwinner,pins = "PF0", "PF1", "PF2",
       "PF3", "PF4", "PF5";
    allwinner,function = "sdc0";
    allwinner,muxsel = <2>;
    allwinner,drive = <1>;
    allwinner,pull = <1>;
   };

   sdc0_pins_b: sdc0@1 {
    allwinner,pins = "PF0", "PF1", "PF2",
       "PF3", "PF4", "PF5";
    allwinner,function = "io_disabled";
    allwinner,muxsel = <7>;
    allwinner,drive = <1>;
    allwinner,pull = <1>;
   };

   sdc0_pins_c: sdc0@2 {
    allwinner,pins = "PF0", "PF1", "PF2",
       "PF3", "PF4", "PF5";
    allwinner,function = "uart0_jtag";
    allwinner,muxsel = <3>;
    allwinner,drive = <1>;
    allwinner,pull = <1>;
   };

   sdc1_pins_a: sdc1@0 {
    allwinner,pins = "PG0", "PG1", "PG2",
       "PG3", "PG4", "PG5";
    allwinner,function = "sdc1";
    allwinner,muxsel = <2>;
    allwinner,drive = <3>;
    allwinner,pull = <1>;
   };

   sdc1_pins_b: sdc1@1 {
    allwinner,pins = "PG0", "PG1", "PG2",
       "PG3", "PG4", "PG5";
    allwinner,function = "io_disabled";
    allwinner,muxsel = <7>;
    allwinner,drive = <1>;
    allwinner,pull = <1>;
   };

   sdc2_pins_a: sdc2@0 {
    allwinner,pins = "PC1", "PC4", "PC5", "PC6",
       "PC7", "PC8", "PC9", "PC10",
       "PC11", "PC12", "PC13", "PC14";
    allwinner,function = "sdc2";
    allwinner,muxsel = <3>;
    allwinner,drive = <2>;
    allwinner,pull = <1>;
   };

   sdc2_pins_b: sdc2@1 {
    allwinner,pins = "PC1", "PC4", "PC5", "PC6",
       "PC7", "PC8", "PC9", "PC10",
       "PC11", "PC12", "PC13", "PC14";
    allwinner,function = "io_disabled";
    allwinner,muxsel = <7>;
    allwinner,drive = <1>;
    allwinner,pull = <1>;
   };

   daudio0_pins_a: daudio0@0 {
    allwinner,pins = "PH0", "PH1", "PH2", "PH3", "PH4";
    allwinner,function = "pcm0";
    allwinner,muxsel = <3>;
    allwinner,drive = <1>;
    allwinner,pull = <0>;
   };

   daudio0_pins_b: daudio0_sleep@0 {
    allwinner,pins = "PH0", "PH1", "PH2", "PH3", "PH4";
    allwinner,function = "io_disabled";
    allwinner,muxsel = <7>;
    allwinner,drive = <1>;
    allwinner,pull = <0>;
   };

   daudio2_pins_a: daudio2@0 {
    allwinner,pins = "PG10", "PG11", "PG12", "PG13", "PG14";
    allwinner,function = "pcm2";
    allwinner,muxsel = <2>;
    allwinner,drive = <1>;
    allwinner,pull = <0>;
   };

   daudio2_pins_b: daudio2_sleep@0 {
    allwinner,pins = "PG10", "PG11", "PG12", "PG13", "PG14";
    allwinner,function = "io_disabled";
    allwinner,muxsel = <7>;
    allwinner,drive = <1>;
    allwinner,pull = <0>;
   };

   daudio3_pins_a: daudio3@0 {
     allwinner,pins = "PB12", "PB13", "PB14", "PB15", "PB16";
     allwinner,function = "pcm3";
     allwinner,muxsel = <2>;
     allwinner,driver = <1>;
     allwinner,pull = <0>;
   };

   daudio3_pins_b: daudio3_sleep@0 {
     allwinner,pins = "PB12", "PB13", "PB14", "PB15", "PB16";
     allwinner,function = "io_disabled";
     allwinner,muxsel = <7>;
     allwinner,driver = <1>;
     allwinner,pull = <0>;
   };

   spdif_pins_a: spdif@0 {
    allwinner,pins = "PH5", "PH6", "PH7";
    allwinner,function = "spdif0";
    allwinner,muxsel = <3>;
    allwinner,drive = <1>;
    allwinner,pull = <0>;
   };

   spdif_pins_b: spdif_sleep@0 {
    allwinner,pins = "PH5", "PH6", "PH7";
    allwinner,function = "io_disabled";
    allwinner,muxsel = <7>;
    allwinner,drive = <1>;
    allwinner,pull = <0>;
   };

   dmic_pins_a: dmic@0 {
    allwinner,pins = "PD14", "PD15", "PD16", "PD17", "PD18";
    allwinner,function = "dmic";
    allwinner,muxsel = <4>;
    allwinner,driver = <1>;
    allwinner,pull = <0>;
    };

    dmic_pins_b: dmic_sleep@0 {
    allwinner,pins = "PD14", "PD15", "PD16", "PD17", "PD18";
    allwinner,function = "io_disabled";
    allwinner,muxsel = <7>;
    allwinner,driver = <1>;
    allwinner,pull = <0>;
   };

   ahub_daudio0_pins_a: ahub_daudio0@0 {
     allwinner,pins = "PH0", "PH1", "PH2", "PH3", "PH4";
     allwinner,function = "h_pcm0";
     allwinner,muxsel = <4>;
     allwinner,driver = <1>;
     allwinner,pull = <0>;
   };

   ahub_daudio0_pins_b: ahub_daudio0_sleep@0 {
     allwinner,pins = "PH0", "PH1", "PH2", "PH3", "PH4";
     allwinner,function = "io_disabled";
     allwinner,muxsel = <7>;
     allwinner,driver = <1>;
     allwinner,pull = <0>;
   };

   ahub_daudio2_pins_a: ahub_daudio2@0 {
    allwinner,pins = "PG10", "PG11", "PG12", "PG13", "PG14";
    allwinner,function = "h_pcm2";
    allwinner,muxsel = <3>;
    allwinner,drive = <1>;
    allwinner,pull = <0>;
   };

   ahub_daudio2_pins_b: ahub_daudio2_sleep@0 {
    allwinner,pins = "PG10", "PG11", "PG12", "PG13", "PG14";
    allwinner,function = "io_disabled";
    allwinner,muxsel = <7>;
    allwinner,drive = <1>;
    allwinner,pull = <0>;
   };

   ahub_daudio3_pins_a: ahub_daudio3@0 {
     allwinner,pins = "PB12", "PB13", "PB14", "PB15", "PB16";
     allwinner,function = "h_pcm3";
     allwinner,muxsel = <4>;
     allwinner,driver = <1>;
     allwinner,pull = <0>;
   };

   ahub_daudio3_pins_b: ahub_daudio3_sleep@0 {
     allwinner,pins = "PB12", "PB13", "PB14", "PB15", "PB16";
     allwinner,function = "io_disabled";
     allwinner,muxsel = <7>;
     allwinner,driver = <1>;
     allwinner,pull = <0>;
   };

   csi0_pins_a: csi0@0 {
    allwinner,pins = "PD0", "PD2", "PD3", "PD4", "PD5",
       "PD6", "PD7", "PD8", "PD9", "PD10", "PD11";
    allwinner,pname = "csi0_pck", "csi0_hsync", "csi0_vsync",
        "csi0_d0", "csi0_d1", "csi0_d2", "csi0_d3",
        "csi0_d4", "csi0_d5", "csi0_d6", "csi0_d7";
    allwinner,function = "csi0";
    allwinner,muxsel = <4>;
    allwinner,drive = <1>;
    allwinner,pull = <0>;
    allwinner,data = <0>;
   };

   csi0_pins_b: csi0@1 {
    allwinner,pins = "PD0", "PD2", "PD3", "PD4", "PD5",
       "PD6", "PD7", "PD8", "PD9", "PD10", "PD11";
    allwinner,pname = "csi0_pck", "csi0_hsync", "csi0_vsync",
        "csi0_d0", "csi0_d1", "csi0_d2", "csi0_d3",
        "csi0_d4", "csi0_d5", "csi0_d6", "csi0_d7";
    allwinner,function = "io_disabled";
    allwinner,muxsel = <7>;
    allwinner,drive = <1>;
    allwinner,pull = <0>;
    allwinner,data = <0>;
   };
   csi_mclk0_pins_a: csi_mclk0@0 {
    allwinner,pins = "PD1";
    allwinner,pname = "csi_mclk0";
    allwinner,function = "csi_mclk0";
    allwinner,muxsel = <4>;
    allwinner,drive = <1>;
    allwinner,pull = <0>;
    allwinner,data = <0>;
   };
   csi_mclk0_pins_b: csi_mclk0@1 {
    allwinner,pins = "PD1";
    allwinner,pname = "csi_mclk0";
    allwinner,function = "io_disabled";
    allwinner,muxsel = <7>;
    allwinner,drive = <1>;
    allwinner,pull = <0>;
    allwinner,data = <0>;
   };
   csi_cci0_pins_a: csi_cci0@0 {
    allwinner,pins = "PD12","PD13";
    allwinner,pname = "csi_cci0_sck","csi_cci0_sda";
    allwinner,function = "csi_cci0";
    allwinner,muxsel = <4>;
    allwinner,drive = <1>;
    allwinner,pull = <0>;
    allwinner,data = <0>;
   };
   csi_cci0_pins_b: csi_cci0@1 {
    allwinner,pins = "PD12","PD13";
    allwinner,pname = "csi_cci0_sck","csi_cci0_sda";
    allwinner,function = "io_disabled";
    allwinner,muxsel = <7>;
    allwinner,drive = <1>;
    allwinner,pull = <0>;
    allwinner,data = <0>;
   };
   scr0_pins_a: scr0@0 {
    allwinner,pins = "PG13", "PG14", "PG10", "PG11", "PG12";
    allwinner,pname = "scr0_rst", "scr0_det", "scr0_vccen", "scr0_sck", "scr0_sda";
    allwinner,function = "sim0";
    allwinner,muxsel = <4>;
    allwinner,drive = <0>;
    allwinner,pull = <1>;
   };

   scr0_pins_b: scr0@1 {
    allwinner,pins = "PG8", "PG9";
    allwinner,pname = "scr0_vppen", "scr0_vppp";
    allwinner,function = "sim0";
    allwinner,muxsel = <4>;
    allwinner,drive = <0>;
    allwinner,pull = <1>;
   };

   scr0_pins_c: scr0@2 {
    allwinner,pins = "PG8", "PG9", "PG10", "PG11", "PG12", "PG13", "PG14";
    allwinner,function = "io_disabled";
    allwinner,muxsel = <7>;
    allwinner,drive = <0>;
    allwinner,pull = <0>;
   };

   scr1_pins_a: scr1@0 {
    allwinner,pins = "PH5", "PH6", "PH2",
       "PH3", "PH4";
    allwinner,pname = "scr1_rst", "scr1_det",
        "scr1_vccen", "scr1_sck",
        "scr1_sda";
    allwinner,function = "sim1";
    allwinner,muxsel = <5>;
    allwinner,drive = <1>;
    allwinner,pull = <1>;
   };

   scr1_pins_b: scr1@1 {
    allwinner,pins = "PH0", "PH1";
    allwinner,pname = "scr1_vppen", "scr1_vppp";
    allwinner,function = "sim1";
    allwinner,muxsel = <5>;
    allwinner,drive = <1>;
    allwinner,pull = <1>;
   };

   scr1_pins_c: scr1@2 {
    allwinner,pins = "PH0", "PH1", "PH2",
       "PH3", "PH4", "PH5",
       "PH6";
    allwinner,function = "io_disabled";
    allwinner,muxsel = <7>;
    allwinner,drive = <1>;
    allwinner,pull = <0>;
   };

   nand0_pins_a: nand0@0 {
    allwinner,pins = "PC0", "PC1", "PC2", "PC4",
       "PC6", "PC7", "PC8", "PC9",
       "PC10", "PC11", "PC12", "PC13",
       "PC14";
    allwinner,pname= "nand0_we", "nand0_ale","nand0_cle", "nand0_nre",
       "nand0_d0", "nand0_d1", "nand0_d2", "nand0_d3",
       "nand0_d4", "nand0_d5", "nand0_d6", "nand0_d7",
       "nand0_ndqs";
    allwinner,function = "nand0";
    allwinner,muxsel = <2>;
    allwinner,drive = <1>;
    allwinner,pull = <0>;
   };

   nand0_pins_b: nand0@1 {
    allwinner,pins = "PC3", "PC5", "PC15", "PC16";
    allwinner,pname= "nand0_ce0", "nand0_rb0", "nand0_ce1", "nand0_rb1";
    allwinner,function = "nand0";
    allwinner,muxsel = <2>;
    allwinner,drive = <1>;
    allwinner,pull = <1>;
   };

   nand0_pins_c: nand0@2 {
    allwinner,pins = "PC0", "PC1", "PC2", "PC3",
       "PC4", "PC5", "PC6", "PC7",
       "PC8", "PC9", "PC10", "PC11",
       "PC12", "PC13", "PC14", "PC15",
       "PC16";
    allwinner,function = "io_disabled";
    allwinner,muxsel = <7>;
    allwinner,drive = <1>;
    allwinner,pull = <0>;
   };

   hdmi_ddc_pin_a: hdmi@0 {
    allwinner,pins = "PH8","PH9";
    allwinner,function = "ddc";
    allwinner,muxsel = <2>;
    allwinner,drive = <1>;
    allwinner,pull = <0>;
   };

   hdmi_ddc_pin_b: hdmi@1 {
    allwinner,pins = "PH8","PH9";
    allwinner,function = "io_disabled";
    allwinner,muxsel = <7>;
    allwinner,drive = <1>;
    allwinner,pull = <0>;
   };

   hdmi_cec_pin_a: hdmi@2 {
    allwinner,pins = "PH10";
    allwinner,function = "hcec0";
    allwinner,muxsel = <2>;
    allwinner,drive = <1>;
    allwinner,pull = <0>;
   };

   hdmi_cec_pin_b: hdmi@3 {
    allwinner,pins = "PH10";
    allwinner,function = "io_disabled";
    allwinner,muxsel = <7>;
    allwinner,drive = <1>;
    allwinner,pull = <0>;
   };

   ccir_clk_pin_a: ac200@2 {
    allwinner,pins = "PB0";
    allwinner,function = "ac200";
    allwinner,muxsel = <2>;
    allwinner,drive = <0>;
    allwinner,pull = <0>;
   };

   ccir_clk_pin_b: ac200@3 {
    allwinner,pins = "PB0";
    allwinner,function = "io_disabled";
    allwinner,muxsel = <7>;
    allwinner,drive = <0>;
    allwinner,pull = <0>;
   };

   gmac_pins_a: gmac@0 {
    allwinner,pins = "PA0", "PA1", "PA2", "PA3",
      "PA4", "PA5", "PA6", "PA7",
      "PA8", "PA9";
    allwinner,function = "gmac0";
    allwinner,muxsel = <2>;
    allwinner,drive = <3>;
    allwinner,pull = <0>;
   };

   gmac_pins_b: gmac@1 {
    allwinner,pins = "PA0", "PA1", "PA2", "PA3",
      "PA4", "PA5", "PA6", "PA7",
      "PA8", "PA9";
    allwinner,function = "io_disabled";
    allwinner,muxsel = <7>;
    allwinner,drive = <3>;
    allwinner,pull = <0>;
   };
  };
 };
};
# 20 "arch/arm64/boot/dts/sunxi/sun50iw6p1.dtsi" 2
/ {
 model = "sun50iw6";
 compatible = "arm,sun50iw6p1";
 interrupt-parent = <&gic>;
 #address-cells = <2>;
 #size-cells = <2>;

 aliases {
  serial0 = &uart0;
  serial1 = &uart1;
  serial2 = &uart2;
  serial3 = &uart3;
  twi0 = &twi0;
  twi1 = &twi1;
  twi2 = &twi2;
  twi3 = &twi3;
  spi0 = &spi0;
  spi1 = &spi1;
  pcie = &pcie;
  scr0 = &scr0;
  scr1 = &scr1;
  gmac0 = &gmac0;

  global_timer0 = &soc_timer0;
  mmc0 = &sdc0;
  mmc2 = &sdc2;
  nand0 =&nand0;
  disp = &disp;
  lcd0 = &lcd0;
  lcd1 = &lcd1;
  hdmi = &hdmi;
  pwm = &pwm;
  pwm0 = &pwm0;
  pwm1 = &pwm1;
  tv0 = &tv0;
  s_pwm = &s_pwm;
  spwm0 = &spwm0;
  ac200 = &ac200;
  boot_disp = &boot_disp;
  charger0 = &charger0;
  regulator0 = &regulator0;
 };

 chosen {
  bootargs = "earlyprintk=sunxi-uart,0x05000000 loglevel=8 initcall_debug=1 console=ttyS0 init=/init";
  linux,initrd-start = <0x0 0x0>;
  linux,initrd-end = <0x0 0x0>;
 };

 firmware {
  android {
   compatible = "android,firmware";
   name = "android";
   boot_devices = "soc/sdc0,soc/sdc2,soc";
   fstab {
    compatible = "android,fstab";
    name = "fstab";
    vendor {
     compatible = "android,vendor";
     dev = "/dev/block/by-name/vendor";
     fsmgr_flags = "wait,recoveryonly";
     mnt_flags = "ro,barrier=1";
     name = "vendor";
     status = "ok";
     type = "ext4";
    };
   };
  };
  optee {
   compatible = "linaro,optee-tz";
   method = "smc";
  };
 };

 cpus {
  #address-cells = <2>;
  #size-cells = <0>;

  cpu@0 {
   device_type = "cpu";
   compatible = "arm,cortex-a53","arm,armv8";
   reg = <0x0 0x0>;
   enable-method = "psci";
   clocks = <&clk_pll_cpu>;
   clock-latency = <2000000>;
   clock-frequency = <1320000000>;
   operating-points-v2 = <&cpu_opp_l_table0 &cpu_opp_l_table1 &cpu_opp_l_table2>;
   cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0 &SYS_SLEEP_0>;
  };

  cpu@1 {
   device_type = "cpu";
   compatible = "arm,cortex-a53","arm,armv8";
   reg = <0x0 0x1>;
   enable-method = "psci";
   clocks = <&clk_pll_cpu>;
   clock-frequency = <1320000000>;
   operating-points-v2 = <&cpu_opp_l_table0 &cpu_opp_l_table1 &cpu_opp_l_table2>;
   cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0 &SYS_SLEEP_0>;
  };

  cpu@2 {
   device_type = "cpu";
   compatible = "arm,cortex-a53","arm,armv8";
   reg = <0x0 0x2>;
   enable-method = "psci";
   clocks = <&clk_pll_cpu>;
   clock-frequency = <1320000000>;
   operating-points-v2 = <&cpu_opp_l_table0 &cpu_opp_l_table1 &cpu_opp_l_table2>;
   cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0 &SYS_SLEEP_0>;
  };

  cpu@3 {
   device_type = "cpu";
   compatible = "arm,cortex-a53","arm,armv8";
   reg = <0x0 0x3>;
   enable-method = "psci";
   clocks = <&clk_pll_cpu>;
   clock-frequency = <1320000000>;
   operating-points-v2 = <&cpu_opp_l_table0 &cpu_opp_l_table1 &cpu_opp_l_table2>;
   cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0 &SYS_SLEEP_0>;
  };

  idle-states {
   entry-method = "arm,psci";

   CPU_SLEEP_0: cpu-sleep-0 {
    compatible = "arm,idle-state";
    arm,psci-suspend-param = <0x0010000>;
    entry-latency-us = <4000>;
    exit-latency-us = <10000>;
    min-residency-us = <15000>;
   };

   CLUSTER_SLEEP_0: cluster-sleep-0 {
    compatible = "arm,idle-state";
    arm,psci-suspend-param = <0x1010000>;
    entry-latency-us = <50000>;
    exit-latency-us = <100000>;
    min-residency-us = <250000>;
   };

   SYS_SLEEP_0: sys-sleep-0 {
    compatible = "arm,idle-state";
    arm,psci-suspend-param = <0x2010000>;
    entry-latency-us = <100000>;
    exit-latency-us = <2000000>;
    min-residency-us = <4500000>;
   };
  };
 };

 psci {
     compatible = "arm,psci-0.2";
     method = "smc";
     psci_version = <0x84000000>;
     cpu_suspend = <0xc4000001>;
     cpu_off = <0x84000002>;
     cpu_on = <0xc4000003>;
     affinity_info = <0xc4000004>;
     migrate = <0xc4000005>;
     migrate_info_type = <0x84000006>;
     migrate_info_up_cpu = <0xc4000007>;
     system_off = <0x84000008>;
     system_reset = <0x84000009>;

 };
 n_brom {
  compatible = "allwinner,n-brom";
  reg = <0x0 0x0 0x0 0xa000>;
 };

 s_brom {
  compatible = "allwinner,s-brom";
  reg = <0x0 0x0 0x0 0x10000>;
 };

 sram_ctrl {
  device_type = "sram_ctrl";
  compatible = "allwinner,sram_ctrl";
  reg = <0x0 0x03000000 0x0 0x100>;
 };

 sram_a1 {
  compatible = "allwinner,sram_a1";
  reg = <0x0 0x00020000 0x0 0x8000>;
 };

 sram_a2 {
  compatible = "allwinner,sram_a2";
  reg = <0x0 0x00100000 0x0 0x14000>;
 };

 prcm {
  compatible = "allwinner,prcm";
  reg = <0x0 0x01f01400 0x0 0x400>;
 };

 s_cpuscfg {
  compatible = "allwinner,s_cpuscfg";
  reg = <0x0 0x01f01c00 0x0 0x400>;
 };

 ion {
  compatible = "allwinner,sunxi-ion";
# 233 "arch/arm64/boot/dts/sunxi/sun50iw6p1.dtsi"
  heap_sys_user@0{
   compatible = "allwinner,sys_user";
   heap-name = "sys_user";
   heap-id = <0x0>;
   heap-base = <0x0>;
   heap-size = <0x0>;
   heap-type = "ion_system";
  };
  heap_sys_contig@0{
   compatible = "allwinner,sys_contig";
   heap-name = "sys_contig";
   heap-id = <0x1>;
   heap-base = <0x0>;
   heap-size = <0x0>;
   heap-type = "ion_contig";
  };
  heap_cma@0{
   compatible = "allwinner,cma";
   heap-name = "cma";
   heap-id = <0x4>;
   heap-base = <0x0>;
   heap-size = <0x0>;
   heap-type = "ion_cma";
  };
  heap_secure@0{
   compatible = "allwinner,secure";
   heap-name = "secure";
   heap-id = <0x6>;
   heap-base = <0x0>;
   heap-size = <0x0>;
   heap-type = "ion_secure";
  };
 };

 dram: dram {
  compatible = "allwinner,dram";
  clocks = <&clk_pll_ddr0>;
  clock-names = "pll_ddr";
  dram_clk = <672>;
  dram_type = <3>;
  dram_zq = <0x003F3FDD>;
  dram_odt_en = <1>;
  dram_para1 = <0x10f41000>;
  dram_para2 = <0x00001200>;
  dram_mr0 = <0x1A50>;
  dram_mr1 = <0x40>;
  dram_mr2 = <0x10>;
  dram_mr3 = <0>;
  dram_tpr0 = <0x04E214EA>;
  dram_tpr1 = <0x004214AD>;
  dram_tpr2 = <0x10A75030>;
  dram_tpr3 = <0>;
  dram_tpr4 = <0>;
  dram_tpr5 = <0>;
  dram_tpr6 = <0>;
  dram_tpr7 = <0>;
  dram_tpr8 = <0>;
  dram_tpr9 = <0>;
  dram_tpr10 = <0>;
  dram_tpr11 = <0>;
  dram_tpr12 = <168>;
  dram_tpr13 = <0x823>;
 };

 memory@40000000 {
  device_type = "memory";
  reg = <0x00000000 0x40000000 0x00000000 0x20000000>;
 };

 gic: interrupt-controller@03020000 {
  compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
  #interrupt-cells = <3>;
  #address-cells = <0>;
  device_type = "gic";
  interrupt-controller;
  reg = <0x0 0x03021000 0 0x1000>,
        <0x0 0x03022000 0 0x2000>,
        <0x0 0x03024000 0 0x2000>,
        <0x0 0x03026000 0 0x2000>;
  interrupts = <1 9 0xf04>;
 };

 sid: sunxi-sid@03006000 {
  compatible = "allwinner,sunxi-sid";
  device_type = "sid";
  reg = <0x0 0x03006000 0 0x1000>;
 };

 chipid: sunxi-chipid@03006200 {
  compatible = "allwinner,sunxi-chipid";
  device_type = "chipid";
  reg = <0x0 0x03006200 0 0x0200>;
 };

 timer_arch {
  compatible = "arm,armv8-timer";
  interrupts = <1 13 ((((1 << (4)) - 1) << 8) | 8)>,
      <1 14 ((((1 << (4)) - 1) << 8) | 8)>,
      <1 11 ((((1 << (4)) - 1) << 8) | 8)>,
      <1 10 ((((1 << (4)) - 1) << 8) | 8)>;
  clock-frequency = <24000000>;
  arm,no-tick-in-suspend;
 };

 pmu {
  compatible = "arm,armv8-pmuv3";
  interrupts = <0 140 4>,
        <0 141 4>,
        <0 142 4>,
        <0 143 4>;
 };

 opp_dvfs_table:opp_dvfs_table {
  cluster_num = <1>;
  opp_table_count = <3>;

  cpu_opp_l_table0: opp_l_table0 {
   compatible = "allwinner,opp_l_table0";
   opp_count = <8>;
   opp-shared;

   opp00 {
    opp-hz = /bits/ 64 <480000000>;
    opp-microvolt = <880000>;
    axi-bus-divide-ratio = <3>;
    clock-latency-ns = <2000000>;
    pval = <2800>;
   };
   opp01 {
    opp-hz = /bits/ 64 <720000000>;
    opp-microvolt = <880000>;
    axi-bus-divide-ratio = <3>;
    clock-latency-ns = <2000000>;
    pval = <2800>;
   };
   opp02 {
    opp-hz = /bits/ 64 <816000000>;
    opp-microvolt = <880000>;
    axi-bus-divide-ratio = <3>;
    clock-latency-ns = <2000000>;
    pval = <2800>;
   };
   opp03 {
    opp-hz = /bits/ 64 <888000000>;
    opp-microvolt = <880000>;
    axi-bus-divide-ratio = <3>;
    clock-latency-ns = <2000000>;
    pval = <2800>;
   };
   opp04 {
    opp-hz = /bits/ 64 <1080000000>;
    opp-microvolt = <940000>;
    axi-bus-divide-ratio = <3>;
    clock-latency-ns = <2000000>;
    pval = <3100>;
   };
   opp05 {
    opp-hz = /bits/ 64 <1320000000>;
    opp-microvolt = <1000000>;
    axi-bus-divide-ratio = <3>;
    clock-latency-ns = <2000000>;
    pval = <3650>;
   };
   opp06 {
    opp-hz = /bits/ 64 <1488000000>;
    opp-microvolt = <1060000>;
    axi-bus-divide-ratio = <3>;
    clock-latency-ns = <2000000>;
    pval = <3950>;
   };
  };

  cpu_opp_l_table1: opp_l_table1 {
   compatible = "allwinner,opp_l_table1";
   opp_count = <8>;
   opp-shared;

   opp00 {
    opp-hz = /bits/ 64 <480000000>;
    opp-microvolt = <820000>;
    axi-bus-divide-ratio = <3>;
    clock-latency-ns = <2000000>;
    pval = <2800>;
   };
   opp01 {
    opp-hz = /bits/ 64 <720000000>;
    opp-microvolt = <820000>;
    axi-bus-divide-ratio = <3>;
    clock-latency-ns = <2000000>;
    pval = <2800>;
   };
   opp02 {
    opp-hz = /bits/ 64 <816000000>;
    opp-microvolt = <820000>;
    axi-bus-divide-ratio = <3>;
    clock-latency-ns = <2000000>;
    pval = <2800>;
   };
   opp03 {
    opp-hz = /bits/ 64 <888000000>;
    opp-microvolt = <820000>;
    axi-bus-divide-ratio = <3>;
    clock-latency-ns = <2000000>;
    pval = <2800>;
   };
   opp04 {
    opp-hz = /bits/ 64 <1080000000>;
    opp-microvolt = <880000>;
    axi-bus-divide-ratio = <3>;
    clock-latency-ns = <2000000>;
    pval = <3100>;
   };
   opp05 {
    opp-hz = /bits/ 64 <1320000000>;
    opp-microvolt = <940000>;
    axi-bus-divide-ratio = <3>;
    clock-latency-ns = <2000000>;
    pval = <3650>;
   };
   opp06 {
    opp-hz = /bits/ 64 <1488000000>;
    opp-microvolt = <1000000>;
    axi-bus-divide-ratio = <3>;
    clock-latency-ns = <2000000>;
    pval = <3950>;
   };
  };

  cpu_opp_l_table2: opp_l_table2 {
   compatible = "allwinner,opp_l_table2";
   opp_count = <8>;
   opp-shared;

   opp00 {
    opp-hz = /bits/ 64 <480000000>;
    opp-microvolt = <800000>;
    axi-bus-divide-ratio = <3>;
    clock-latency-ns = <2000000>;
    pval = <2800>;
   };
   opp01 {
    opp-hz = /bits/ 64 <720000000>;
    opp-microvolt = <800000>;
    axi-bus-divide-ratio = <3>;
    clock-latency-ns = <2000000>;
    pval = <2800>;
   };
   opp02 {
    opp-hz = /bits/ 64 <816000000>;
    opp-microvolt = <800000>;
    axi-bus-divide-ratio = <3>;
    clock-latency-ns = <2000000>;
    pval = <2800>;
   };
   opp03 {
    opp-hz = /bits/ 64 <888000000>;
    opp-microvolt = <800000>;
    axi-bus-divide-ratio = <3>;
    clock-latency-ns = <2000000>;
    pval = <2800>;
   };
   opp04 {
    opp-hz = /bits/ 64 <1080000000>;
    opp-microvolt = <840000>;
    axi-bus-divide-ratio = <3>;
    clock-latency-ns = <2000000>;
    pval = <3100>;
   };
   opp05 {
    opp-hz = /bits/ 64 <1320000000>;
    opp-microvolt = <900000>;
    axi-bus-divide-ratio = <3>;
    clock-latency-ns = <2000000>;
    pval = <3650>;
   };
   opp06 {
    opp-hz = /bits/ 64 <1488000000>;
    opp-microvolt = <960000>;
    axi-bus-divide-ratio = <3>;
    clock-latency-ns = <2000000>;
    pval = <3950>;
   };
  };

 };

 dramfreq {
  compatible = "allwinner,sunxi-dramfreq";
  reg = <0x0 0x04002000 0x0 0x1000>,
        <0x0 0x04003000 0x0 0x3000>,
        <0x0 0x03001000 0x0 0x1000>;
  interrupts = <0 33 0x4>;
  clocks = <&clk_pll_ddr0>;
  status = "okay";
 };

 uboot: uboot {
 };

 mmu_aw: iommu@030f0000 {
  compatible = "allwinner,sunxi-iommu";
  reg = <0x0 0x030f0000 0x0 0x1000>;
  interrupts = <0 57 4>;
  interrupt-names = "iommu-irq";
  clocks = <&clk_iommu>;
  clock-names = "iommu";

  #iommu-cells = <2>;
  status = "okay";
 };

 soc: soc@03000000 {
  compatible = "simple-bus";
  #address-cells = <2>;
  #size-cells = <2>;
  ranges;
  device_type = "soc";

  dma0:dma-controller@03002000 {
   compatible = "allwinner,sun50i-dma";
   reg = <0x0 0x03002000 0x0 0x1000>;
   interrupts = <0 43 4>;
   clocks = <&clk_dma>;
   #dma-cells = <1>;
  };

  mbus0:mbus-controller@04002000 {
   compatible = "allwinner,sun50i-mbus";
   reg = <0x0 0x04002000 0x0 0x1000>;
   #mbus-cells = <1>;
  };

  arisc {
   compatible = "allwinner,sunxi-arisc";
   #address-cells = <2>;
   #size-cells = <2>;
   clocks = <&clk_losc>, <&clk_iosc>, <&clk_hosc>, <&clk_pll_periph0>;
   clock-names = "losc", "iosc", "hosc", "pll_periph0";
   powchk_used = <0x0>;
   power_reg = <0x02309621>;
   system_power = <50>;
  };

  arisc_space {
   compatible = "allwinner,arisc_space";

   space1 = <0x48040000 0x00000000 0x00014000>;
   space2 = <0x48100000 0x00018000 0x00004000>;
   space3 = <0x48104000 0x00000000 0x00001000>;
   space4 = <0x48105000 0x00000000 0x00001000>;
  };

  standby_space: standby_space@040020000 {
   compatible = "allwinner,sun50iw6-usbstandby";

   space1 = <0x40020000 0x00000000 0x00000800>;
  };

  msgbox: msgbox@03003000 {
   compatible = "allwinner,msgbox";
   clocks = <&clk_msgbox>;
   clock-names = "clk_msgbox";
   reg = <0x0 0x03003000 0x0 0x1000>;
   interrupts = <0 39 1>;
   status = "okay";
  };

  hwspinlock: hwspinlock@3004000 {
   compatible = "allwinner,sunxi-hwspinlock";
   clocks = <&clk_hwspinlock_rst>, <&clk_hwspinlock_bus>;
   clock-names = "clk_hwspinlock_rst", "clk_hwspinlock_bus";
   reg = <0x0 0x03004000 0x0 0x1000>;
   num-locks = <8>;
   status = "okay";
  };

  s_cir0: s_cir@07040000 {
   compatible = "allwinner,s_cir";
   reg = <0x0 0x07040000 0x0 0x400>;
   interrupts = <0 109 4>;
   pinctrl-names = "default";
   pinctrl-0 = <&s_cir0_pins_a>;
   clocks = <&clk_hosc>,<&clk_cpurcir>;
   supply = "vcc-pl";
   supply_vol = "3300000";
   status = "okay";
  };

  s_uart0: s_uart@7080000 {
   compatible = "allwinner,s_uart";
   reg = <0x0 0x07080000 0x0 0xd0>;
   interrupts = <0 106 4>;
   pinctrl-names = "default";
   pinctrl-0 = <&s_uart0_pins_a>;
   status = "okay";
  };

  s_twi0: s_twi@1f03400 {
   compatible = "allwinner,s_twi";
   reg = <0x0 0x01f02400 0x0 0x20>;
   interrupts = <0 44 4>;
   pinctrl-names = "default";
   pinctrl-0 = <&s_twi0_pins_a>;
   status = "okay";
  };

  s_jtag0: s_jtag0 {
   compatible = "allwinner,s_jtag";
   pinctrl-names = "default";
   pinctrl-0 = <&s_jtag0_pins_a>;
   status = "disable";
  };

  box_start_os: box_start_os0 {
   compatible = "allwinner,box_start_os";
   start_type = <0x0>;
   irkey_used = <0x0>;
   pmukey_used = <0x0>;
   pmukey_num = <0x0>;
   led_power = <0x0>;
   led_state = <0x0>;
   status = "disable";
  };

  soc_timer0: timer@03009000 {
   compatible = "allwinner,sun4i-a10-timer";
   device_type = "timer";
   reg = <0x0 0x03009000 0x0 0x400>;
   interrupts = <0 48 4>;
   clock-frequency = <24000000>;
   timer-prescale = <16>;
  };

  rtc: rtc@07000000 {
   compatible = "allwinner,sun50iw6-rtc";
   device_type = "rtc";
   reg = <0x0 0x07000000 0x0 0x200>;
   interrupts = <0 101 4>;
   gpr_offset = <0x100>;
   gpr_len = <8>;
   gpr_cur_pos = <6>;
  };

  wdt: watchdog@030090a0 {
   compatible = "allwinner,sun50i-wdt";
   reg = <0x0 0x030090a0 0x0 0x20>;
   interrupts = <0 50 4>;
  };

  ve: ve@01c0e000 {
   compatible = "allwinner,sunxi-cedar-ve";
   reg = <0x0 0x01c0e000 0x0 0x1000>,
         <0x0 0x03000000 0x0 0x10>,
         <0x0 0x03001000 0x0 0x1000>;
   interrupts = <0 89 4>;
   clocks = <&clk_pll_ve>, <&clk_ve>;
   iommus = <&mmu_aw 3 1>;
  };

  vp9: vp9@01c00000 {
   compatible = "allwinner,sunxi-google-vp9";
   reg = <0x0 0x01c00000 0x0 0x1000>,
         <0x0 0x03000000 0x0 0x10>,
         <0x0 0x03001000 0x0 0x1000>;
   interrupts = <0 90 4>;
   clocks = <&clk_pll_ve>, <&clk_vp9>;
   #clocks = <&clk_pll_periph0x2>, <&clk_vp9>;
   iommus = <&mmu_aw 5 1>;
  };

  uart0: uart@05000000 {
   compatible = "allwinner,sun50i-uart";
   device_type = "uart0";
   reg = <0x0 0x05000000 0x0 0x400>;
   interrupts = <0 0 4>;
   clocks = <&clk_uart0>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&uart0_pins_a>;
   pinctrl-1 = <&uart0_pins_b>;
   uart0_port = <0>;
   uart0_type = <2>;
   status = "disabled";
  };

  uart1: uart@05000400 {
   compatible = "allwinner,sun50i-uart";
   device_type = "uart1";
   reg = <0x0 0x05000400 0x0 0x400>;
   interrupts = <0 1 4>;
   clocks = <&clk_uart1>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&uart1_pins_a>;
   pinctrl-1 = <&uart1_pins_b>;
   uart1_port = <1>;
   uart1_type = <4>;
   status = "disabled";
  };

  uart2: uart@05000800 {
   compatible = "allwinner,sun50i-uart";
   device_type = "uart2";
   reg = <0x0 0x05000800 0x0 0x400>;
   interrupts = <0 2 4>;
   clocks = <&clk_uart2>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&uart2_pins_a>;
   pinctrl-1 = <&uart2_pins_b>;
   uart2_port = <2>;
   uart2_type = <4>;
   status = "okay";
  };

  uart3: uart@05000c00 {
   compatible = "allwinner,sun50i-uart";
   device_type = "uart3";
   reg = <0x0 0x05000c00 0x0 0x400>;
   interrupts = <0 3 4>;
   clocks = <&clk_uart3>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&uart3_pins_a>;
   pinctrl-1 = <&uart3_pins_b>;
   uart3_port = <3>;
   uart3_type = <4>;
   status = "disabled";
  };

  twi0: twi@0x05002000{
   #address-cells = <1>;
   #size-cells = <0>;
   compatible = "allwinner,sun50i-twi";
   device_type = "twi0";
   reg = <0x0 0x05002000 0x0 0x400>;
   interrupts = <0 4 4>;
   clocks = <&clk_twi0>;
   clock-frequency = <400000>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&twi0_pins_a>;
   pinctrl-1 = <&twi0_pins_b>;
   status = "disabled";
  };

  twi1: twi@0x05002400{
   #address-cells = <1>;
   #size-cells = <0>;
   compatible = "allwinner,sun50i-twi";
   device_type = "twi1";
   reg = <0x0 0x05002400 0x0 0x400>;
   interrupts = <0 5 4>;
   clocks = <&clk_twi1>;
   clock-frequency = <200000>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&twi1_pins_a>;
   pinctrl-1 = <&twi1_pins_b>;
   status = "disabled";
  };

  twi2: twi@0x05002800{
   #address-cells = <1>;
   #size-cells = <0>;
   compatible = "allwinner,sun50i-twi";
   device_type = "twi2";
   reg = <0x0 0x05002800 0x0 0x400>;
   interrupts = <0 6 4>;
   clocks = <&clk_twi2>;
   clock-frequency = <200000>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&twi2_pins_a>;
   pinctrl-1 = <&twi2_pins_b>;
   status = "disabled";
  };
  twi3: twi@0x05002c00{
   #address-cells = <1>;
   #size-cells = <0>;
   compatible = "allwinner,sun50i-twi";
   device_type = "twi3";
   reg = <0x0 0x05002c00 0x0 0x400>;
   interrupts = <0 7 4>;
   clocks = <&clk_twi3>;
   clock-frequency = <200000>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&twi3_pins_a>;
   pinctrl-1 = <&twi3_pins_b>;
   status = "disabled";
  };

  usbc0:usbc0@0 {
   device_type = "usbc0";
   compatible = "allwinner,sunxi-otg-manager";
   usb_port_type = <2>;
   usb_detect_type = <1>;
   usb_id_gpio;
   usb_det_vbus_gpio;
   usb_drv_vbus_gpio;
   usb_host_init_state = <0>;
   usb_regulator_io = "nocare";
   usb_wakeup_suspend = <0>;
   usb_luns = <3>;
   usb_serial_unique = <0>;
   usb_serial_number = "20080411";
   rndis_wceis = <1>;
   status = "okay";
  };

  udc:udc-controller@0x05100000 {
   compatible = "allwinner,sunxi-udc";
   reg = <0x0 0x05100000 0x0 0x1000>,
         <0x0 0x00000000 0x0 0x100>;
   interrupts = <0 23 4>;
   clocks = <&clk_usbphy0>, <&clk_usbotg>;
   status = "okay";
  };

  ehci0:ehci0-controller@0x05101000 {
   compatible = "allwinner,sunxi-ehci0";
   reg = <0x0 0x05101000 0x0 0xFFF>,
         <0x0 0x00000000 0x0 0x100>,
         <0x0 0x05100000 0x0 0x1000>;
   interrupts = <0 24 4>;
   clocks = <&clk_usbphy0>, <&clk_usbehci0>;
   hci_ctrl_no = <0>;
   status = "okay";
  };

  ohci0:ohci0-controller@0x05101400 {
   compatible = "allwinner,sunxi-ohci0";
   reg = <0x0 0x05101000 0x0 0xFFF>,
         <0x0 0x00000000 0x0 0x100>,
         <0x0 0x05100000 0x0 0x1000>;
   interrupts = <0 25 4>;
   clocks = <&clk_usbphy0>, <&clk_usbohci0>, <&clk_usbohci0_12m>, <&clk_osc48md4>, <&clk_hosc>, <&clk_losc>;
   hci_ctrl_no = <0>;
   status = "okay";
  };

  usbc1:usbc1@0 {
   device_type = "usbc1";
   usb_drv_vbus_gpio;
   usb_host_init_state = <1>;
   usb_regulator_io = "nocare";
   usb_wakeup_suspend = <0>;
   status = "okay";
  };

  xhci:xhci-controller@0x05200000 {
   compatible = "allwinner,sunxi-xhci";
   reg = <0x0 0x05200000 0x0 0xFFFFF>,
         <0x0 0x00000000 0x0 0x100>,
         <0x0 0x05100000 0x0 0x1000>;
   interrupts = <0 26 4>;
   clocks = <&clk_usbphy1>, <&clk_usb3_0_host>;
   hci_ctrl_no = <1>;
   status = "okay";
  };

  usbc2:usbc2@0 {
   device_type = "usbc2";
   usb_drv_vbus_gpio;
   usb_host_init_state = <1>;
   usb_regulator_io = "nocare";
   usb_wakeup_suspend = <0>;
   status = "okay";
  };

  ehci3:ehci3-controller@0x05311000 {
   compatible = "allwinner,sunxi-ehci3";
   reg = <0x0 0x05311000 0x0 0xFFF>,
         <0x0 0x00000000 0x0 0x100>,
         <0x0 0x05100000 0x0 0x1000>;
   interrupts = <0 28 4>;
   clocks = <&clk_usbphy3>, <&clk_usbehci3>, <&clk_usbhsic>, <&clk_usbhsic>, <&clk_pll_hsic>;
   hci_ctrl_no = <3>;
   status = "okay";
  };

  ohci3:ohci3-controller@0x05311400 {
   compatible = "allwinner,sunxi-ohci3";
   reg = <0x0 0x05311000 0x0 0xFFF>,
         <0x0 0x00000000 0x0 0x100>,
         <0x0 0x05100000 0x0 0x1000>;
   interrupts = <0 29 4>;
   clocks = <&clk_usbphy3>, <&clk_usbohci3>, <&clk_usbohci3_12m>, <&clk_osc48md4>, <&clk_hosc>, <&clk_losc>;
   hci_ctrl_no = <3>;
   status = "okay";
  };

  ac200_codec: ac200_codec {
   compatible = "allwinner,ac200_codec";
   status = "disabled";
  };

  daudio0:daudio@0x05090000 {
   compatible = "allwinner,sunxi-daudio";
   reg = <0x0 0x05090000 0x0 0x74>;
   clocks = <&clk_pll_audio>,<&clk_i2s0>;
   pinctrl-names = "default","sleep";
   pinctrl-0 = <&daudio0_pins_a>;
   pinctrl-1 = <&daudio0_pins_b>;
   pcm_lrck_period = <0x20>;
   slot_width_select = <0x20>;
   daudio_master = <0x04>;
   audio_format = <0x01>;
   signal_inversion = <0x01>;
   tdm_config = <0x01>;
   frametype = <0x00>;
   tdm_num = <0x00>;
   mclk_div = <0x00>;
   status = "disabled";
  };

  audiohdmi:daudio@0x05091000 {
   compatible = "allwinner,sunxi-tdmhdmi";
   reg = <0x0 0x05091000 0x0 0x74>;
   clocks = <&clk_pll_audio>,<&clk_i2s1>;
   status = "disabled";
  };

  daudio2:daudio@0x05092000 {
   compatible = "allwinner,sunxi-daudio";
   reg = <0x0 0x05092000 0x0 0x74>;
   clocks = <&clk_pll_audio>,<&clk_i2s2>;
   pinctrl-names = "default","sleep";
   pinctrl-0 = <&daudio2_pins_a>;
   pinctrl-1 = <&daudio2_pins_b>;
   pcm_lrck_period = <0x20>;
   slot_width_select = <0x20>;
   daudio_master = <0x04>;
   audio_format = <0x01>;
   signal_inversion = <0x01>;
   tdm_config = <0x01>;
   frametype = <0x00>;
   tdm_num = <0x2>;
   mclk_div = <0x0>;
   status = "disabled";
  };

  daudio3:daudio@0x0508f000{
   compatible = "allwinner,sunxi-daudio";
   reg = <0x0 0x0508f000 0x0 0x74>;
   clocks = <&clk_pll_audio>,<&clk_i2s3>;
   pinctrl-names = "default","sleep";
   pinctrl-0 = <&daudio3_pins_a>;
   pinctrl-1 = <&daudio3_pins_b>;
   pcm_lrck_period = <0x20>;
   slot_width_select = <0x20>;
   daudio_master = <0x04>;
   audio_format = <0x01>;
   signal_inversion = <0x01>;
   tdm_config = <0x01>;
   frametype = <0x00>;
   tdm_num = <0x3>;
   mclk_div = <0x0>;
   status = "disabled";
  };

  spdif:spdif-controller@0x05093000{
   compatible = "allwinner,sunxi-spdif";
   reg = <0x0 0x05093000 0x0 0x40>;
   clocks = <&clk_pll_audio>,<&clk_spdif>;
   pinctrl-names = "default","sleep";
   pinctrl-0 = <&spdif_pins_a>;
   pinctrl-1 = <&spdif_pins_b>;
   status = "disabled";
  };

  dmic:dmic-controller@0x05095000{
   compatible = "allwinner,sunxi-dmic";
   reg = <0x0 0x05095000 0x0 0x50>;
   clocks = <&clk_pll_audio>,<&clk_dmic>;
   pinctrl-names = "default","sleep";
   pinctrl-0 = <&dmic_pins_a>;
   pinctrl-1 = <&dmic_pins_b>;
   status = "disabled";
  };

  ahub_cpudai0:cpudai0-controller@0x05097000 {
   compatible = "allwinner,sunxi-ahub-cpudai";
   reg = <0x0 0x05097000 0x0 0xADF>;
   id = <0x0>;
   status = "okay";
  };

  ahub_cpudai1:cpudai1-controller@0x05097000 {
   compatible = "allwinner,sunxi-ahub-cpudai";
   reg = <0x0 0x05097000 0x0 0xADF>;
   id = <0x1>;
   status = "okay";
  };

  ahub_cpudai2:cpudai2-controller@0x05097000 {
   compatible = "allwinner,sunxi-ahub-cpudai";
   reg = <0x0 0x05097000 0x0 0xADF>;
   id = <0x2>;
   status = "okay";
  };

  ahub_codec:ahub_codec@0x05097000{
   compatible = "allwinner,sunxi-ahub";
   reg = <0x0 0x05097000 0x0 0xADF>;
   clocks = <&clk_pll_audio>,<&clk_ahub>;
   status = "okay";
  };

  ahub_daudio0:ahub_daudio0@0x05097000{
   compatible = "allwinner,sunxi-ahub-daudio";
   reg = <0x0 0x05097000 0x0 0xADF>;
   clocks = <&clk_pll_audio>,<&clk_ahub>;
   pinctrl-names = "default","sleep";
   pinctrl-0 = <&ahub_daudio0_pins_a>;
   pinctrl-1 = <&ahub_daudio0_pins_b>;
   pinconfig = <0x1>;
   frametype = <0x0>;
   pcm_lrck_period = <0x20>;
   slot_width_select = <0x20>;
   daudio_master = <0x04>;
   audio_format = <0x01>;
   signal_inversion = <0x01>;
   tdm_config = <0x01>;
   tdm_num = <0x0>;
   mclk_div = <0x0>;
   status = "disabled";
  };

  ahub_daudio1:ahub_daudio1@0x05097000{
   compatible = "allwinner,sunxi-ahub-daudio";
   reg = <0x0 0x05097000 0x0 0xADF>;
   clocks = <&clk_pll_audio>,<&clk_ahub>;
   pinconfig = <0x0>;
   frametype = <0x0>;
   pcm_lrck_period = <0x20>;
   slot_width_select = <0x20>;
   daudio_master = <0x04>;
   audio_format = <0x01>;
   signal_inversion = <0x01>;
   tdm_config = <0x01>;
   tdm_num = <0x1>;
   mclk_div = <0x0>;
   status = "okay";
  };

  ahub_daudio2:ahub_daudio2@0x05097000{
   compatible = "allwinner,sunxi-ahub-daudio";
   reg = <0x0 0x05097000 0x0 0xADF>;
   clocks = <&clk_pll_audio>,<&clk_ahub>;
   pinctrl-names = "default","sleep";
   pinctrl-0 = <&ahub_daudio2_pins_a>;
   pinctrl-1 = <&ahub_daudio2_pins_b>;
   pinconfig = <0x1>;
   frametype = <0x0>;
   pcm_lrck_period = <0x20>;
   slot_width_select = <0x20>;
   daudio_master = <0x04>;
   audio_format = <0x01>;
   signal_inversion = <0x01>;
   tdm_config = <0x01>;
   tdm_num = <0x2>;
   mclk_div = <0x0>;
   status = "okay";
  };

  ahub_daudio3:ahub_daudio3@0x05097000{
   compatible = "allwinner,sunxi-ahub-daudio";
   reg = <0x0 0x05097000 0x0 0xADF>;
   clocks = <&clk_pll_audio>,<&clk_ahub>;
   pinctrl-names = "default","sleep";
   pinctrl-0 = <&ahub_daudio3_pins_a>;
   pinctrl-1 = <&ahub_daudio3_pins_b>;
   pinconfig = <0x1>;
   frametype = <0x0>;
   pcm_lrck_period = <0x20>;
   slot_width_select = <0x20>;
   daudio_master = <0x04>;
   audio_format = <0x01>;
   signal_inversion = <0x01>;
   tdm_config = <0x01>;
   tdm_num = <0x3>;
   mclk_div = <0x4>;
   status = "okay";
  };

  snddaudio0:sound@0{
   compatible = "allwinner,sunxi-daudio0-machine";
   sunxi,daudio-controller = <&daudio0>;
   sunxi,cpudai-controller = <&ahub_daudio0>;
   status = "disable";
  };

  sndhdmi:sound@1{
   compatible = "allwinner,sunxi-hdmi-machine";
   sunxi,hdmi-controller = <&audiohdmi>;
   sunxi,cpudai-controller = <&ahub_daudio1>;
   status = "okay";
  };

  snddaudio2:sound@2{
   compatible = "allwinner,sunxi-daudio2-machine";
   sunxi,daudio-controller = <&daudio2>;
   sunxi,cpudai-controller = <&ahub_daudio2>;
   status = "okay";
  };

  snddaudio3:sound@3{
   compatible = "allwinner,sunxi-daudio3-machine";
   sunxi,daudio-controller = <&daudio3>;
   sunxi,cpudai-controller = <&ahub_daudio3>;

   sunxi,snddaudio-codec = "acx00-codec";
   sunxi,snddaudio-codec-dai = "acx00-dai";
   status = "okay";
  };

  sndspdif:sound@4{
   compatible = "allwinner,sunxi-spdif-machine";
   sunxi,spdif-controller = <&spdif>;
   status = "disabled";
  };

  snddmic:sound@5{
   compatible = "allwinner,sunxi-dmic-machine";
   sunxi,dmic-controller = <&dmic>;
   status = "disabled";
  };

  sndahub:sound@6{
   compatible = "allwinner,sunxi-ahub-machine";
   sunxi,cpudai-controller0 = <&ahub_cpudai0>;
   sunxi,cpudai-controller1 = <&ahub_cpudai1>;
   sunxi,cpudai-controller2 = <&ahub_cpudai2>;
   sunxi,audio-codec = <&ahub_codec>;
   status = "okay";
  };

  spi0: spi@05010000 {
   #address-cells = <1>;
   #size-cells = <0>;
   compatible = "allwinner,sun50i-spi";
   device_type = "spi0";
   reg = <0x0 0x05010000 0x0 0x1000>;
   interrupts = <0 10 4>;
   clocks = <&clk_pll_periph0>, <&clk_spi0>;
   clock-frequency = <100000000>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&spi0_pins_a &spi0_pins_b>;
   pinctrl-1 = <&spi0_pins_c>;
   spi0_cs_number = <1>;
   spi0_cs_bitmap = <1>;
   status = "disabled";
  };

  spi1: spi@05011000 {
   #address-cells = <1>;
   #size-cells = <0>;
   compatible = "allwinner,sun50i-spi";
   device_type = "spi1";
   reg = <0x0 0x05011000 0x0 0x1000>;
   interrupts = <0 11 4>;
   clocks = <&clk_pll_periph0>, <&clk_spi1>;
   clock-frequency = <100000000>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&spi1_pins_a &spi1_pins_b>;
   pinctrl-1 = <&spi1_pins_c>;
   spi1_cs_number = <1>;
   spi1_cs_bitmap = <1>;
   status = "disabled";

   spi_board0 {
       device_type = "spi_board0";
       compatible = "spidev";
       spi-max-frequency = <0x00124f80>;
       reg = <0x00000000>;
   };

  };
  pcie: pcie@0x05400000 {
   #address-cells = <3>;
   #size-cells = <2>;
   compatible = "allwinner,sun50i-pcie";
   reg = <0 0x05400000 0 0x2000>,
         <0 0x05410000 0 0x10000>;
   reg-names = "dbi", "config";
   device_type = "pci";
   ranges = <0x00000800 0 0x05410000 0 0x05410000 0 0x00010000
      0x81000000 0 0 0 0x05e00000 0 0x00010000
      0x82000000 0 0x05500000 0 0x05500000 0 0x00800000>;
   num-lanes = <1>;
   interrupts = <0 127 4>,
         <0 126 4>;
   interrupt-names = "msi";
   clocks = <&clk_pcieref>,
    <&clk_pciemaxi>,
    <&clk_pcieaux>,
    <&clk_pcie_bus>,
    <&clk_pcie_power>,
    <&clk_pcie_rst>;
   #interrupt-cells = <1>;
   interrupt-map-mask = <0 0 0 0>;
   interrupt-map = <0 0 0 1 &gic 0 127 4>;
   status = "okay";
  };

  sdc2: sdmmc@04022000 {
   compatible = "allwinner,sunxi-mmc-v4p6x";
   device_type = "sdc2";
   reg = <0x0 0x04022000 0x0 0x1000>;
   interrupts = <0 37 0x0104>;
   clocks = <&clk_hosc>,
     <&clk_pll_periph1x2>,
     <&clk_sdmmc2_mod>,
     <&clk_sdmmc2_bus>,
     <&clk_sdmmc2_rst>;
   clock-names = "osc24m","pll_periph","mmc","ahb","rst";
   pinctrl-names = "default","sleep";
   pinctrl-0 = <&sdc2_pins_a>;
   pinctrl-1 = <&sdc2_pins_b>;
   bus-width = <8>;





   max-frequency = <50000000>;
   cap-sd-highspeed;
   cap-mmc-highspeed;
   cap-erase;
   mmc-high-capacity-erase-size;
   no-sdio;
   no-sd;
# 1265 "arch/arm64/boot/dts/sunxi/sun50iw6p1.dtsi"
   sdc_tm4_sm0_freq0 = <0>;
   sdc_tm4_sm0_freq1 = <0>;
   sdc_tm4_sm1_freq0 = <0x00000000>;
   sdc_tm4_sm1_freq1 = <0>;
   sdc_tm4_sm2_freq0 = <0x00000000>;
   sdc_tm4_sm2_freq1 = <0>;
   sdc_tm4_sm3_freq0 = <0x05000000>;
   sdc_tm4_sm3_freq1 = <0x00000005>;
   sdc_tm4_sm4_freq0 = <0x00050000>;
   sdc_tm4_sm4_freq1 = <0x00000004>;
# 1284 "arch/arm64/boot/dts/sunxi/sun50iw6p1.dtsi"
   status = "okay";
  };

  sdc0: sdmmc@04020000 {
   compatible = "allwinner,sunxi-mmc-v4p1x";
   device_type = "sdc0";
   reg = <0x0 0x04020000 0x0 0x1000>;
   interrupts = <0 35 0x0104>;
   clocks = <&clk_hosc>,
     <&clk_pll_periph1x2>,
     <&clk_sdmmc0_mod>,
     <&clk_sdmmc0_bus>,
     <&clk_sdmmc0_rst>;
   clock-names = "osc24m","pll_periph","mmc","ahb","rst";
   pinctrl-names = "default","sleep" ,"uart_jtag";
   pinctrl-0 = <&sdc0_pins_a>;
   pinctrl-1 = <&sdc0_pins_b>;
   pinctrl-2 = <&sdc0_pins_c>;
   max-frequency = <50000000>;
   bus-width = <4>;



   cd-gpios = <&pio 5 6 0 1 2 0>;






   cap-sd-highspeed;
   cap-mmc-highspeed;
   no-sdio;
   no-mmc;
# 1334 "arch/arm64/boot/dts/sunxi/sun50iw6p1.dtsi"
   status = "okay";
  };

  sdc1: sdmmc@04021000 {
   compatible = "allwinner,sunxi-mmc-v4p1x";
   device_type = "sdc1";
   reg = <0x0 0x04021000 0x0 0x1000>;
   interrupts = <0 36 0x0104>;
   clocks = <&clk_hosc>,
     <&clk_pll_periph1x2>,
     <&clk_sdmmc1_mod>,
     <&clk_sdmmc1_bus>,
     <&clk_sdmmc1_rst>;
   clock-names = "osc24m","pll_periph","mmc","ahb","rst";
   pinctrl-names = "default","sleep";
   pinctrl-0 = <&sdc1_pins_a>;
   pinctrl-1 = <&sdc1_pins_b>;
   max-frequency = <50000000>;
   bus-width = <4>;
# 1362 "arch/arm64/boot/dts/sunxi/sun50iw6p1.dtsi"
   cap-sd-highspeed;
   cap-mmc-highspeed;
   no-mmc;
# 1375 "arch/arm64/boot/dts/sunxi/sun50iw6p1.dtsi"
   sunxi-dly-52M-ddr4 = <1 0 0 0 2>;

   sunxi-dly-104M = <1 0 0 0 1>;

   sunxi-dly-208M = <1 0 0 0 1>;



   status = "disabled";
  };

  disp: disp@01000000 {
   compatible = "allwinner,sunxi-disp";
   reg = <0x0 0x01000000 0x0 0x01400000>,
         <0x0 0x06510000 0x0 0x100>,
         <0x0 0x06511000 0x0 0x800>,
         <0x0 0x06515000 0x0 0x800>;
   interrupts = <0 65 0x0104>, <0 66 0x0104>;
   clocks = <&clk_de>,
     <&clk_display_top>,
     <&clk_tcon_lcd>,
     <&clk_tcon_tv>;
   boot_disp = <0>;
   boot_disp1 = <0>;
   boot_disp2 = <0>;
   fb_base = <0>;
   iommus = <&mmu_aw 0 0>;
   status = "okay";
  };

  lcd0: lcd0@01c0c000 {
   compatible = "allwinner,sunxi-lcd0";
   pinctrl-names = "active","sleep";

   status = "okay";
  };

  lcd1: lcd1@01c0c001 {
   compatible = "allwinner,sunxi-lcd1";
   pinctrl-names = "active","sleep";

   status = "okay";
  };

  hdmi: hdmi@06000000 {
   compatible = "allwinner,sunxi-hdmi";
   reg = <0x0 0x06000000 0x0 0x100000>;
   interrupts = <0 64 0>;
   clocks = <&clk_hdmi>,<&clk_hdmi_slow>,<&clk_hdmi_hdcp>,<&clk_hdmi_cec>;
   pinctrl-names = "ddc_active","ddc_sleep","cec_active", "cec_sleep";
   pinctrl-0 = <&hdmi_ddc_pin_a>;
   pinctrl-1 = <&hdmi_ddc_pin_b>;
   pinctrl-2 = <&hdmi_cec_pin_a>;
   pinctrl-3 = <&hdmi_cec_pin_b>;
   status = "okay";
  };

  tv0: tv0@01c94000 {
   compatible = "allwinner,sunxi-tv";
   reg = <0x0 0x01e40000 0x0 0x1000>;

   status = "disabled";
  };

  soc_tr: tr@01000000 {
   compatible = "allwinner,sun50i-tr";
   reg = <0x0 0x01000000 0x0 0x000200bc>;
   interrupts = <0 96 0x0104>;
   clocks = <&clk_de>;
   status = "okay";
  };

  pwm: pwm@0300a000 {
   compatible = "allwinner,sunxi-pwm";
   reg = <0x0 0x0300a000 0x0 0x3c>;
   clocks = <&clk_pwm>;
   pwm-number = <2>;
   pwm-base = <0x0>;
   pwms = <&pwm0>, <&pwm1>;
  };

  pwm0: pwm0@0300a000 {
   compatible = "allwinner,sunxi-pwm0";
   pinctrl-names = "active", "sleep";
   reg_base = <0x0300a000>;
   reg_busy_offset = <0x00>;
   reg_busy_shift = <28>;
   reg_enable_offset = <0x00>;
   reg_enable_shift = <4>;
   reg_clk_gating_offset = <0x00>;
   reg_clk_gating_shift = <6>;
   reg_bypass_offset = <0x00>;
   reg_bypass_shift = <9>;
   reg_pulse_start_offset = <0x00>;
   reg_pulse_start_shift = <8>;
   reg_mode_offset = <0x00>;
   reg_mode_shift = <7>;
   reg_polarity_offset = <0x00>;
   reg_polarity_shift = <5>;
   reg_period_offset = <0x04>;
   reg_period_shift = <16>;
   reg_period_width = <16>;
   reg_active_offset = <0x04>;
   reg_active_shift = <0>;
   reg_active_width = <16>;
   reg_prescal_offset = <0x00>;
   reg_prescal_shift = <0>;
   reg_prescal_width = <4>;
  };
  pwm1: pwm1@0300a000 {
   compatible = "allwinner,sunxi-pwm1";
   pinctrl-names = "active", "sleep";
   reg_base = <0x0300a000>;
   reg_busy_offset = <0x00>;
   reg_busy_shift = <29>;
   reg_enable_offset = <0x00>;
   reg_enable_shift = <19>;
   reg_clk_gating_offset = <0x00>;
   reg_clk_gating_shift = <21>;
   reg_bypass_offset = <0x00>;
   reg_bypass_shift = <24>;
   reg_pulse_start_offset = <0x00>;
   reg_pulse_start_shift = <23>;
   reg_mode_offset = <0x00>;
   reg_mode_shift = <22>;
   reg_polarity_offset = <0x00>;
   reg_polarity_shift = <20>;
   reg_period_offset = <0x08>;
   reg_period_shift = <16>;
   reg_period_width = <16>;
   reg_active_offset = <0x08>;
   reg_active_shift = <0>;
   reg_active_width = <16>;
   reg_prescal_offset = <0x00>;
   reg_prescal_shift = <15>;
   reg_prescal_width = <4>;
  };
  s_pwm: s_pwm@07020c00 {
   compatible = "allwinner,sunxi-s_pwm";
   reg = <0x0 0x07020c00 0x0 0x3c>;
   clocks = <&clk_spwm>;
   pwm-number = <1>;
   pwm-base = <0x10>;
   pwms = <&spwm0>;
  };

  spwm0: spwm0@07020c00 {
   compatible = "allwinner,sunxi-pwm16";
   pinctrl-names = "active", "sleep";
   reg_base = <0x07020c00>;
   reg_busy_offset = <0x00>;
   reg_busy_shift = <28>;
   reg_enable_offset = <0x00>;
   reg_enable_shift = <4>;
   reg_clk_gating_offset = <0x00>;
   reg_clk_gating_shift = <6>;
   reg_bypass_offset = <0x00>;
   reg_bypass_shift = <9>;
   reg_pulse_start_offset = <0x00>;
   reg_pulse_start_shift = <8>;
   reg_mode_offset = <0x00>;
   reg_mode_shift = <7>;
   reg_polarity_offset = <0x00>;
   reg_polarity_shift = <5>;
   reg_period_offset = <0x04>;
   reg_period_shift = <16>;
   reg_period_width = <16>;
   reg_active_offset = <0x04>;
   reg_active_shift = <0>;
   reg_active_width = <16>;
   reg_prescal_offset = <0x00>;
   reg_prescal_shift = <0>;
   reg_prescal_width = <4>;
  };

  boot_disp: boot_disp {
   compatible = "allwinner,boot_disp";
  };

  ac200: ac200 {
   compatible = "allwinner,sunxi-ac200";
   clocks = <&clk_tcon_lcd>;
   pinctrl-names = "active","sleep", "ccir_clk_active",
   "ccir_clk_sleep";
   pinctrl-2 = <&ccir_clk_pin_a>;
   pinctrl-3 = <&ccir_clk_pin_b>;
   status = "okay";
  };

  vind0:vind@0 {
   compatible = "allwinner,sunxi-vin-media", "simple-bus";
   #address-cells = <2>;
   #size-cells = <2>;
   ranges;
   device_id = <0>;
   reg = <0x0 0x06620000 0x0 0x1000>;
   clocks = <&clk_csi_top>, <&clk_pll_periph0>,
     <&clk_csi_master0>, <&clk_hosc>, <&clk_pll_periph0>;
   pinctrl-names = "mclk0-default","mclk0-sleep";
   pinctrl-0 = <&csi_mclk0_pins_a>;
   pinctrl-1 = <&csi_mclk0_pins_b>;
   status = "okay";

   csi_cci0:cci@0x0662e000 {
    compatible = "allwinner,sunxi-csi_cci";
    reg = <0x0 0x0662e000 0x0 0x1000>;
    interrupts = <0 72 4>;
    clocks = <&clk_csi_misc>;
    pinctrl-names = "default","sleep";
    pinctrl-0 = <&csi_cci0_pins_a>;
    pinctrl-1 = <&csi_cci0_pins_b>;
    device_id = <0>;
    status = "okay";
   };
   csi0:csi@0x06621000 {
    device_type = "csi0";
    compatible = "allwinner,sunxi-csi";
    reg = <0x0 0x06621000 0x0 0x1000>;
    interrupts = <0 70 4>;
    pinctrl-names = "default","sleep";
    pinctrl-0 = <&csi0_pins_a>;
    pinctrl-1 = <&csi0_pins_b>;
    device_id = <0>;
    iommus = <&mmu_aw 4 1>;
    status = "okay";
   };
   csi1:csi@1 {
    device_type = "csi1";
    compatible = "allwinner,sunxi-csi";
    device_id = <1>;
    iommus = <&mmu_aw 4 1>;
    status = "disabled";
   };
   mipi0:mipi@0 {
    compatible = "allwinner,sunxi-mipi";
    device_id = <0>;
    status = "disabled";
   };
   mipi1:mipi@1 {
    compatible = "allwinner,sunxi-mipi";
    device_id = <1>;
    status = "disabled";
   };
   isp0:isp@0 {
    compatible = "allwinner,sunxi-isp";
    reg = <0x0 0x02100000 0x0 0x800>;
    interrupts = <0 86 4>;
    device_id = <0>;
    iommus = <&mmu_aw 4 1>;
    status = "okay";
   };
   isp1:isp@1 {
    compatible = "allwinner,sunxi-isp";
    reg = <0x0 0x02100800 0x0 0x800>;
    device_id = <1>;
    iommus = <&mmu_aw 4 1>;
    status = "disabled";
   };
   scaler0:scaler@0x02101000 {
    compatible = "allwinner,sunxi-scaler";
    reg = <0x0 0x02101000 0x0 0x400>;
    device_id = <0>;
    iommus = <&mmu_aw 4 1>;
    status = "okay";
   };
   scaler1:scaler@0x02101400 {
    compatible = "allwinner,sunxi-scaler";
    reg = <0x0 0x02101400 0x0 0x400>;
    device_id = <1>;
    iommus = <&mmu_aw 4 1>;
    status = "okay";
   };
   scaler2:scaler@2 {
    compatible = "allwinner,sunxi-scaler";
    device_id = <2>;
    iommus = <&mmu_aw 4 1>;
    status = "disabled";
   };
   scaler3:scaler@3 {
    compatible = "allwinner,sunxi-scaler";
    device_id = <3>;
    iommus = <&mmu_aw 4 1>;
    status = "disabled";
   };
   actuator0:actuator@0 {
    device_type = "actuator0";
    compatible = "allwinner,sunxi-actuator";
    actuator0_name = "ad5820_act";
    actuator0_slave = <0x18>;
    actuator0_af_pwdn = <>;
    actuator0_afvdd = "afvcc-csi";
    actuator0_afvdd_vol = <2800000>;
    status = "disabled";
   };
   flash0:flash@0 {
    device_type = "flash0";
    compatible = "allwinner,sunxi-flash";
    flash0_type = <2>;
    flash0_en = <>;
    flash0_mode = <>;
    flash0_flvdd = "";
    flash0_flvdd_vol = <>;
    device_id = <0>;
    status = "disabled";
   };
   sensor0:sensor@0 {
    device_type = "sensor0";
    sensor0_mname = "ov5640";
    sensor0_twi_cci_id = <0>;
    sensor0_twi_addr = <0x78>;
    sensor0_pos = "rear";
    sensor0_isp_used = <0>;
    sensor0_fmt = <0>;
    sensor0_stby_mode = <0>;
    sensor0_vflip = <0>;
    sensor0_hflip = <0>;
    sensor0_iovdd = "iovdd-csi";
    sensor0_iovdd_vol = <2800000>;
    sensor0_avdd = "avdd-csi";
    sensor0_avdd_vol = <2800000>;
    sensor0_dvdd = "dvdd-csi-18";
    sensor0_dvdd_vol = <1500000>;
    sensor0_power_en = <>;
    sensor0_reset = <&pio 4 14 1 0 1 0>;
    sensor0_pwdn = <&pio 4 16 1 0 1 0>;
    flash_handle = <&flash0>;
    act_handle = <&actuator0>;
    status = "okay";
   };
   sensor1:sensor@1 {
    device_type = "sensor1";
    sensor1_mname = "ov5647";
    sensor1_twi_cci_id = <0>;
    sensor1_twi_addr = <0x6c>;
    sensor1_pos = "front";
    sensor1_isp_used = <0>;
    sensor1_fmt = <0>;
    sensor1_stby_mode = <0>;
    sensor1_vflip = <0>;
    sensor1_hflip = <0>;
    sensor1_iovdd = "iovdd-csi";
    sensor1_iovdd_vol = <2800000>;
    sensor1_avdd = "avdd-csi";
    sensor1_avdd_vol = <2800000>;
    sensor1_dvdd = "dvdd-csi-18";
    sensor1_dvdd_vol = <1500000>;
    sensor1_power_en = <>;
    sensor1_reset = <&pio 4 14 1 0 1 0>;
    sensor1_pwdn = <&pio 4 15 1 0 1 0>;
    flash_handle = <>;
    act_handle = <>;
    status = "okay";
   };
   vinc0:vinc@0x06623000 {
    device_type = "vinc0";
    compatible = "allwinner,sunxi-vin-core";
    reg = <0x0 0x06623000 0x0 0x100>;
    interrupts = <0 67 4>;
    vinc0_csi_sel = <0>;
    vinc0_mipi_sel = <0xff>;
    vinc0_isp_sel = <0>;
    vinc0_sensor_sel = <0>;
    vinc0_sensor_list = <0>;
    isp_handle = <&isp0 &isp1>;
    sensor_handle = <&sensor0 &sensor1>;
    device_id = <0>;
    iommus = <&mmu_aw 4 1>;
    status = "okay";
   };
   vinc1:vinc@0x06623100 {
    device_type = "vinc1";
    compatible = "allwinner,sunxi-vin-core";
    reg = <0x0 0x06623100 0x0 0x100>;
    interrupts = <0 68 4>;
    vinc1_csi_sel = <0>;
    vinc1_mipi_sel = <0xff>;
    vinc1_isp_sel = <0>;
    vinc1_sensor_sel = <1>;
    vinc1_sensor_list = <0>;
    isp_handle = <&isp0 &isp1>;
    sensor_handle = <&sensor0 &sensor1>;
    device_id = <1>;
    iommus = <&mmu_aw 4 1>;
    status = "okay";
   };
  };

  Vdevice: vdevice@0 {
   compatible = "allwinner,sun50i-vdevice";
   device_type = "Vdevice";
   pinctrl-names = "default";
   pinctrl-0 = <&vdevice_pins_a>;
   test-gpios = <&pio 1 0 1 2 2 1>;
   status = "disabled";
  };

  emce: emce@01905000 {
   compatible = "allwinner,sunxi-emce";
   device_name = "emce";
   reg = <0x0 0x01905000 0 0x100>;
   clock-frequency = <300000000>;
   clocks = <&clk_emce>, <&clk_pll_periph0x2>;
  };

  cryptoengine: ce@1904000 {
   compatible = "allwinner,sunxi-ce";
   device_name = "ce";
   reg = <0x0 0x01904000 0x0 0xa0>,
         <0x0 0x01904800 0x0 0xa0>;
   interrupts = <0 87 0xff01>,
         <0 88 0xff01>;
   clock-frequency = <300000000>;
   clocks = <&clk_ce>, <&clk_pll_periph0x2>;
  };

  di:deinterlace@0x01420000{
   #address-cells = <1>;
   #size-cells = <0>;
   compatible = "allwinner,sunxi-deinterlace";
   reg = <0x0 0x01420000 0x0 0x20c>;
   interrupts = <0 79 4>;
   clocks = <&clk_di> ,<&clk_pll_periph0>;
   iommus = <&mmu_aw 2 1>;
   status = "okay";
  };

  scr0:smartcard@0x05005000{
   #address-cells = <1>;
   #size-cells = <0>;
   compatible = "allwinner,sunxi-scr";
   device_type = "scr0";
   reg = <0x0 0x05005000 0x0 0x400>;
   interrupts = <0 8 4>;
   clocks = <&clk_scr0>, <&clk_apb2>;
   clock-frequency = <24000000>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&scr0_pins_a &scr0_pins_b>;
   pinctrl-1 = <&scr0_pins_c>;
   status = "disabled";
  };

  scr1:smartcard@0x05005400{
   #address-cells = <1>;
   #size-cells = <0>;
   compatible = "allwinner,sunxi-scr";
   device_type = "scr1";
   reg = <0x0 0x05005400 0x0 0x400>;
   interrupts = <0 9 4>;
   clocks = <&clk_scr1>, <&clk_apb2>;
   clock-frequency = <24000000>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&scr1_pins_a &scr1_pins_b>;
   pinctrl-1 = <&scr1_pins_c>;
   status = "disabled";
  };

  pmu0: pmu@0{
   interrupts = <0 96 4>;
   status = "okay";

   powerkey0: powerkey@0{
    status = "okay";
   };

   regulator0: regulator@0{
    status = "okay";
   };

   axp_gpio0: axp_gpio@0{
    gpio-controller;
    #size-cells = <0>;
    #gpio-cells = <6>;
    status = "okay";
    device_type = "axp_pio";
   };

   charger0: charger@0{
    status = "disabled";
   };
  };

  nmi:nmi@0x01f00c00{
   #address-cells = <1>;
   #size-cells = <0>;
   compatible = "allwinner,sunxi-nmi";
   reg = <0x0 0x01f00c00 0x0 0x50>;
   nmi_irq_ctrl = <0x0c>;
   nmi_irq_en = <0x40>;
   nmi_irq_status = <0x10>;
   nmi_irq_mask = <0x50>;
   status = "okay";
  };

  nand0:nand0@04011000 {
   compatible = "allwinner,sun50iw6-nand";
   device_type = "nand0";
   reg = <0x0 0x04011000 0x0 0x1000>;
   interrupts = <0 34 0x04>;
   clocks = <&clk_pll_periph0x2>,<&clk_nand0>,<&clk_nand1>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&nand0_pins_a &nand0_pins_b>;
   pinctrl-1 = <&nand0_pins_c>;
   nand0_regulator1 = "vcc-nand";
   nand0_regulator2 = "none";
   nand0_cache_level = <0x55aaaa55>;
   nand0_flush_cache_num = <0x55aaaa55>;
   nand0_capacity_level = <0x55aaaa55>;
   nand0_id_number_ctl = <0x55aaaa55>;
   nand0_print_level = <0x55aaaa55>;
   nand0_p0 = <0x55aaaa55>;
   nand0_p1 = <0x55aaaa55>;
   nand0_p2 = <0x55aaaa55>;
   nand0_p3 = <0x55aaaa55>;
   status = "okay";
  };

  ts0:ts0@05060000 {
   compatible = "allwinner,sun50i-tsc";
   device_type = "ts0";
   reg = <0x0 0x05060000 0x0 0x1000>;
   interrupts = <0 14 4>;
   clocks = <&clk_pll_periph0>,<&clk_ts>;
   clock-frequency = <120000000>;
   pinctrl-names = "ts0-default","ts1-default",
     "ts2-default","ts3-default",
     "ts0-sleep","ts1-sleep",
     "ts2-sleep","ts3-sleep";
   pinctrl-0 = <&ts0_pins_a>;
   pinctrl-1 = <&ts1_pins_a>;
   pinctrl-2 = <&ts2_pins_a>;
   pinctrl-3 = <&ts3_pins_a>;
   pinctrl-4 = <&ts0_pins_b>;
   pinctrl-5 = <&ts1_pins_b>;
   pinctrl-6 = <&ts2_pins_b>;
   pinctrl-7 = <&ts3_pins_b>;
   ts0config = <0x1>;
   ts1config = <0x0>;
   ts2config = <0x0>;
   ts3config = <0x0>;
   status = "okay";
  };

  sunxi_thermal_sensor:thermal_sensor{
   compatible = "allwinner,thermal_sensor";
   reg = <0x0 0x05070400 0x0 0x400>;
   interrupts = <0 15 0>;
   clocks = <&clk_hosc>,<&clk_ths>;
   sensor_num = <2>;
   combine_num = <2>;
   alarm_low_temp = <105000>;
   alarm_high_temp = <110000>;
   alarm_temp_hysteresis = <15000>;
   shut_temp= <115000>;
   status = "okay";

   ths_combine0:ths_combine0{
    compatible = "allwinner,ths_combine0";
    #thermal-sensor-cells = <1>;
    combine_sensor_num = <1>;
    combine_sensor_type = "cpu";
    combine_sensor_temp_type = "max";
    combine_sensor_id = <0>;
   };
   ths_combine1:ths_combine1{
    compatible = "allwinner,ths_combine1";
    #thermal-sensor-cells = <1>;
    combine_sensor_num = <1>;
    combine_sensor_type = "gpu";
    combine_sensor_temp_type = "max";
    combine_sensor_id = <1>;
   };
  };

  cpu_budget_cooling:cpu_budget_cool{
   device_type = "cpu_budget_cool";
   compatible = "allwinner,budget_cooling";
   #cooling-cells = <2>;
   status = "okay";
   state_cnt = <7>;
   cluster_num = <1>;
   state0 = <1800000 4>;
   state1 = <1488000 4>;
   state2 = <1320000 3>;
   state3 = <1080000 2>;
   state4 = <888000 1>;
   state5 = <720000 1>;
   state6 = <480000 1>;
  };

  gpu_cooling:gpu_cooling{
   compatible = "allwinner,gpu_cooling";
   reg = <0x0 0x0 0x0 0x0>;
   #cooling-cells = <2>;
   status = "okay";
   state_cnt = <4>;
   state0 = <0>;
   state1 = <1>;
   state2 = <2>;
   state3 = <3>;
  };

  thermal-zones{
   cpu_thermal_zone{

    polling-delay-passive = <1000>;
    polling-delay = <1000>;
    thermal-sensors = <&ths_combine0 0>;

    trips{
     cpu_trip0:t0{
      temperature = <60000>;
      type = "passive";
      hysteresis = <0>;
     };
     cpu_trip1:t1{
      temperature = <90000>;
      type = "passive";
      hysteresis = <0>;
     };
     cpu_trip2:t2{
      temperature = <95000>;
      type = "passive";
      hysteresis = <0>;
     };
     cpu_trip3:t3{
      temperature = <100000>;
      type = "passive";
      hysteresis = <0>;
     };
     cpu_trip4:t4{
      temperature = <105000>;
      type = "passive";
      hysteresis = <0>;
     };
     cpu_trip5:t5{
      temperature = <110000>;
      type = "passive";
      hysteresis = <0>;
     };
     crt_trip0:t6{
      temperature = <115000>;
      type = "critical";
      hysteresis = <0>;
     };
    };

    cooling-maps{
     bind0{
      contribution = <0>;
      trip = <&cpu_trip0>;
      cooling-device = <&cpu_budget_cooling 1 1>;
     };
     bind1{
      contribution = <0>;
      trip = <&cpu_trip1>;
      cooling-device = <&cpu_budget_cooling 2 2>;
     };
     bind2{
      contribution = <0>;
      trip = <&cpu_trip2>;
      cooling-device = <&cpu_budget_cooling 3 3>;
     };
     bind3{
      contribution = <0>;
      trip = <&cpu_trip3>;
      cooling-device =
      <&cpu_budget_cooling 4 4>;
     };
     bind4{
      contribution = <0>;
      trip = <&cpu_trip4>;
      cooling-device =
      <&cpu_budget_cooling 5 5>;
     };
     bind5{
      contribution = <0>;
      trip = <&cpu_trip5>;
      cooling-device = <&cpu_budget_cooling 6 6>;
     };
    };
   };

   gpu_thermal_zone{

    polling-delay-passive = <1000>;
    polling-delay = <2000>;
    thermal-sensors = <&ths_combine1 1>;

    trips{
     gpu_trip0:t0{
      temperature = <95000>;
      type = "passive";
      hysteresis = <0>;
     };
     gpu_trip1:t1{
      temperature = <100000>;
      type = "passive";
      hysteresis = <0>;
     };
     gpu_trip2:t2{
      temperature = <105000>;
      type = "passive";
      hysteresis = <0>;
     };
     crt_trip1:t3{
      temperature = <115000>;
      type = "critical";
      hysteresis = <0>;
     };
    };

    cooling-maps{
     bind0{
      contribution = <0>;
      trip = <&gpu_trip0>;
      cooling-device = <&gpu_cooling 1 1>;
     };
     bind1{
      contribution = <0>;
      trip = <&gpu_trip1>;
      cooling-device = <&gpu_cooling 2 2>;
     };
     bind2{
      contribution = <0>;
      trip = <&gpu_trip2>;
      cooling-device = <&gpu_cooling 3 3>;
     };
    };
   };
  };

  keyboard0:keyboard{
   compatible = "allwinner,keyboard_1200mv";
   reg = <0x0 0x05070800 0x0 0x400>;
   interrupts = <0 16 0>;
   status = "okay";
   key_cnt = <5>;
   key0 = <115 115>;
   key1 = <235 114>;
   key2 = <330 139>;
   key3 = <420 28>;
   key4 = <520 102>;
  };

  gmac0: eth@05020000 {
   compatible = "allwinner,sunxi-gmac";
   reg = <0x0 0x05020000 0x0 0x10000>,
         <0x0 0x03000030 0x0 0x4>;
   interrupts = <0 12 4>;
   interrupt-names = "gmacirq";
   clocks = <&clk_gmac>;
   clock-names = "gmac";
   pinctrl-0 = <&gmac_pins_a>;
   pinctrl-1 = <&gmac_pins_b>;
   pinctrl-names = "default", "sleep";
   phy-mode;
   tx-delay = <7>;
   rx-delay = <31>;
   phy-rst;
   gmac-power0;
   gmac-power1;
   gmac-power2;
   status = "disable";
  };
 };

 gpu: gpu@0x01800000 {
  device_type = "gpu";
  compatible = "arm,mali-t720", "arm,mali-midgard";
  reg = <0x0 0x01800000 0x0 0x4000>;
  interrupts = <0 83 4>, <0 84 4>, <0 85 4>;
  interrupt-names = "GPU", "JOB", "MMU";
  clocks = <&clk_pll_gpu>, <&clk_gpu>;
  clock-names = "clk_parent", "clk_mali";
  operating-points = <

   756000 1040000
   624000 950000
   576000 930000
   540000 910000
   504000 890000
   456000 870000
   432000 860000
   420000 850000
   408000 840000
   384000 830000
   360000 820000
   336000 810000
   312000 810000
   264000 810000
   216000 810000
  >;
  };
};
# 10 "arch/arm64/boot/dts/sunxi/sun50iw6p1-soc.dts" 2

/{

 soc@03000000 {
  wlan:wlan {
   compatible = "allwinner,sunxi-wlan";
   clocks = <&clk_losc_out>;
   status = "okay";
  };

  bt:bt {
   compatible = "allwinner,sunxi-bt";
   clocks = <&clk_losc_out>;
   bt_power = "vcc-wifi";
   bt_io_regulator = "vcc-wifi-io";
   bt_rst_n = <&r_pio 12 4 1 0 0 0>;
   status = "okay";
  };

  btlpm:btlpm {
   compatible = "allwinner,sunxi-btlpm";
   uart_index = <1>;
   bt_wake = <&r_pio 12 2 1 0 0 1>;
   bt_hostwake = <&r_pio 12 1 6 0 0 0>;
   status = "okay";
  };
 };
};
