ce7c490719
Move Andes PLICSW ipi device to fdt ipi framework, this patch is based
on Leo's modified IPI scheme on PLICSW.
Current IPI scheme uses bit 0 of pending reigster on PLICSW to send IPI
from hart 0 to hart 7, but bit 0 needs to be hardwired to 0 according
to spec. After some investigation, self-IPI seems to be seldom or never
used, so we re-order the IPI scheme to support 8 core platforms.
dts example (Quad-core AX45MP):
plicsw: interrupt-controller@e6400000 {
compatible = "andestech,plicsw";
reg = <0x00000000 0xe6400000 0x00000000 0x00400000>;
interrupts-extended = <&CPU0_intc 3
&CPU1_intc 3
&CPU2_intc 3
&CPU3_intc 3>;
interrupt-controller;
#address-cells = <2>;
#interrupt-cells = <2>;
};
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
41 lines
676 B
Makefile
41 lines
676 B
Makefile
#
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# SPDX-License-Identifier: BSD-2-Clause
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#
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# Copyright (c) 2019 Andes Technology Corporation
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#
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# Authors:
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# Zong Li <zong@andestech.com>
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# Nylon Chen <nylon7@andestech.com>
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#
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# Compiler flags
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platform-cppflags-y =
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platform-cflags-y =
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platform-asflags-y =
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platform-ldflags-y =
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# Objects to build
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platform-objs-y += cache.o platform.o
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# Blobs to build
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FW_TEXT_START=0x00000000
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FW_DYNAMIC=y
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FW_JUMP=y
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ifeq ($(PLATFORM_RISCV_XLEN), 32)
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FW_JUMP_ADDR=0x400000
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else
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FW_JUMP_ADDR=0x200000
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endif
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FW_JUMP_FDT_ADDR=0x2000000
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FW_PAYLOAD=y
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ifeq ($(PLATFORM_RISCV_XLEN), 32)
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FW_PAYLOAD_OFFSET=0x400000
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else
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FW_PAYLOAD_OFFSET=0x200000
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endif
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FW_PAYLOAD_FDT_ADDR=0x2000000
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