6eef399cfc
Add a virtual global timer device driver. It uses a global timer
register as timer counter, and it uses mtimecmp CSR of clint as
interrupt source.
Using this virtul timer resolves dual way timer sync issue.
On dual way system, we should enable this driver and on single way
system, we should use standard risc-v clint timer.
1. Add a virtual global timer device driver, it is probed by fdt
sg2042-global-mtimer@70300101c0 {
compatible = "sophgo,sg2042-global-mtimer";
reg = < 0x00000070 0x300101c0 0x00000000 0x00000008
0x00000070 0xac000000 0x00000000 0x00200000>;
clock-frequency = <50000000 50000000>;
};
Its compatible should be "sophgo,sg2042-global-mtimer".
And the first region delcared in reg prop is the address of global
timer. The second region delcared in reg prop is the base of clint
timers.
The first clock in clock-frequency is the actual frequency of global
timer, the second clock is the actual frequency of clint timer.
2. Add a quirk in platform specific code.
Add a function sbi_platform_force_emulate_time_csr, it indicates if
opensbi should skip time CSR detection and make software in
supervisor and user mode use emulated time CSR.
Signed-off-by: Chao Wei <chao.wei@sophgo.com>
136 lines
3.5 KiB
C
136 lines
3.5 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2022 Andes Technology Corporation
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*
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* Authors:
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* Yu Chien Peter Lin <peterlin@andestech.com>
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*/
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_io.h>
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#include <sbi/sbi_domain.h>
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#include <sbi/sbi_error.h>
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#include <sbi/sbi_timer.h>
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#include <sbi/sbi_console.h>
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#include <sbi_utils/timer/sg2042_gmt.h>
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struct sg2042gmt_data {
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unsigned long mtimer_base;
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unsigned long mtimecmp_base;
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unsigned long mtimecmp_size;
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unsigned long declared_freq;
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unsigned long actual_freq;
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unsigned long timecmp_freq;
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} sg2042gmt;
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#define SG2042GMT_TIMECMP_CLUSTER_SIZE 0x10000
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#define SG2042GMT_TIMECMP_CLUSTER_CORE_COUNT 4
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static void *timecmp_addr(unsigned int hart_id)
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{
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unsigned int cluster_id = hart_id / SG2042GMT_TIMECMP_CLUSTER_CORE_COUNT;
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unsigned int cluster_offset = hart_id % SG2042GMT_TIMECMP_CLUSTER_CORE_COUNT;
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return (void *)(sg2042gmt.mtimecmp_base + 0x4000 +
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cluster_id * SG2042GMT_TIMECMP_CLUSTER_SIZE +
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cluster_offset * 8);
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}
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static u64 sg2042gmt_timer_value(void)
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{
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u64 global_timer = readq_relaxed((void *)sg2042gmt.mtimer_base);
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/* convert global timer to declared frequency */
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return global_timer / (sg2042gmt.actual_freq / sg2042gmt.declared_freq);
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}
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static void sg2042gmt_timer_event_stop(void)
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{
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unsigned int hart_id = current_hartid();
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writel_relaxed(-1U, timecmp_addr(hart_id));
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writel_relaxed(-1U, timecmp_addr(hart_id) + 4);
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}
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static void sg2042gmt_timer_event_start(u64 next_event)
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{
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unsigned int hart_id = current_hartid();
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u64 global_timer = readq_relaxed((void *)sg2042gmt.mtimer_base);
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u64 clint_timer = csr_read(CSR_TIME);
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u64 delta_global_timer, delta_clint_timer;
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delta_global_timer =
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(next_event * (sg2042gmt.actual_freq / sg2042gmt.declared_freq)) - global_timer;
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delta_clint_timer = delta_global_timer * (sg2042gmt.timecmp_freq / sg2042gmt.actual_freq);
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next_event = clint_timer + delta_clint_timer;
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writel_relaxed(next_event >> 32, timecmp_addr(hart_id) + 4);
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writel_relaxed(next_event & 0xffffffff, timecmp_addr(hart_id));
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}
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static struct sbi_timer_device sg2042gmt_timer = {
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.name = "sg2042gmt",
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.timer_freq = 50000000,
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.timer_value = sg2042gmt_timer_value,
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.timer_event_start = sg2042gmt_timer_event_start,
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.timer_event_stop = sg2042gmt_timer_event_stop
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};
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int sg2042gmt_cold_timer_init(unsigned long mtimer_base,
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unsigned long mtimecmp_base,
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unsigned long mtimecmp_size,
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unsigned long declared_freq,
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unsigned long actual_freq,
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unsigned long timecmp_freq)
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{
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int err;
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/* Add SG2042 GMT timer and time compare region to the root domain */
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#if 0
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err = sbi_domain_root_add_memrange(
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mtimer_base, 4096, 4096,
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SBI_DOMAIN_MEMREGION_MMIO | SBI_DOMAIN_MEMREGION_READABLE);
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if (err) {
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sbi_printf("add timer to root domain failed\n");
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return err;
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}
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#endif
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err = sbi_domain_root_add_memrange(
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mtimecmp_base, mtimecmp_size, 4096,
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SBI_DOMAIN_MEMREGION_MMIO |
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SBI_DOMAIN_MEMREGION_READABLE |
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SBI_DOMAIN_MEMREGION_WRITEABLE);
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if (err) {
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return err;
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}
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sg2042gmt_timer.timer_freq = declared_freq;
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sg2042gmt.mtimer_base = mtimer_base;
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sg2042gmt.mtimecmp_base = mtimecmp_base;
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sg2042gmt.mtimecmp_size = mtimecmp_size;
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sg2042gmt.declared_freq = declared_freq;
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sg2042gmt.actual_freq = actual_freq;
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sg2042gmt.timecmp_freq = timecmp_freq;
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sbi_timer_set_device(&sg2042gmt_timer);
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return 0;
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}
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int sg2042gmt_warm_timer_init(void)
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{
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if (!sg2042gmt.mtimer_base)
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return SBI_ENODEV;
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sg2042gmt_timer_event_stop();
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return 0;
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}
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