105 lines
2.2 KiB
C
105 lines
2.2 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2025 Sophgo Inc.
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*
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* Authors:
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* Haijiao Liu <haijiao.liu@sophgo.com>
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*/
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#ifndef _SG2044_CLK_H_
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#define _SG2044_CLK_H_
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#include <sbi/sbi_string.h>
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#include <sbi/sbi_bitops.h>
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#define KHZ 1000UL
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#define MHZ (KHZ * KHZ)
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#define SG2044_CLK_USE_INIT_VAL BIT(0) /* use default value */
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#define SG2044_CLK_USE_REG_VAL BIT(1) /* use reg divider value */
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#define SG2044_CLK_RO BIT(2) /* use reg divider value */
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#define CLK_PLL BIT(0)
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#define CLK_MUX BIT(1)
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#define PLL_CTRL_OFFSET 0xC4
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#define PLL_STAT_LOCK_OFFSET 0x10
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#define PLL_SELECT_OFFSET 0x2020
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#define CLK_MODE 0x4
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#define CLK_MODE_MASK 0x3
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#define FBDIV_SHIFT 0
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#define FBDIV_WIDTH 12
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#define REFDIV_SHIFT 12
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#define REFDIV_WIDTH 6
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#define POSTDIV1_SHIFT 18
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#define POSTDIV1_WIDTH 3
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#define POSTDIV2_SHIFT 21
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#define POSTDIV2_WIDTH 3
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#define REFDIV_MIN 1
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#define REFDIV_MAX 63
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#define FBDIV_MIN 8
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#define FBDIV_MAX 1066
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#define PLL_FREQ_MIN (1600 * MHZ)
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#define PLL_FREQ_MAX (3200 * MHZ)
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#define div_mask(width) ((1 << (width)) - 1)
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#define TOP_PLL_CTRL(fbdiv, p1, p2, refdiv) \
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(BIT(30) | (0x2 << 27) | BIT(24) | (((p2 - 1) & 0x7) << 21) | \
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(((p1 - 1) & 0x7) << 18) | ((refdiv & 0x3f) << 12) | (fbdiv & 0xfff))
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#define MPLL0_CLK 0
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#define MPLL1_CLK 1
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#define MPLL2_CLK 2
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#define MPLL3_CLK 3
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#define MPLL4_CLK 4
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#define MPLL5_CLK 5
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#define FPLL0_CLK 6
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#define FPLL1_CLK 7
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#define DPLL0_CLK 8
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#define DPLL1_CLK 9
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#define DPLL2_CLK 10
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#define DPLL3_CLK 11
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#define DPLL4_CLK 12
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#define DPLL5_CLK 13
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#define DPLL6_CLK 14
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#define DPLL7_CLK 15
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static inline char is_power_of_2(unsigned long n)
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{
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return (n != 0 && ((n & (n - 1)) == 0));
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}
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#define do_div(n, base) ({ \
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uint32_t __base = (base); \
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uint32_t __rem; \
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__rem = (uint32_t)(n) % __base; \
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(n) = (uint32_t)(n) / __base; \
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__rem; \
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})
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struct sg2044_pll_ctrl {
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unsigned int mode;
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unsigned long freq;
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unsigned int fbdiv;
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unsigned int postdiv1;
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unsigned int postdiv2;
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unsigned int refdiv;
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};
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struct sg2044_pll_clock {
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unsigned int id;
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char *name;
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unsigned int status_offset;
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unsigned int enable_offset;
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uint64_t default_rate;
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struct sg2044_pll_ctrl pctrl_table[4];
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};
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#endif
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