porting: adapt to CV180X/CV181X.

https://github.com/T-head-Semi/opensbi commit: 89182b257c8798e15e4c685c1af0c2862d528d2a

lib/sbi/sbi_system.c

@@ -42,6 +42,7 @@ bool sbi_system_reset_supported(u32 reset_type, u32 reset_reason)
 	return FALSE;
 }
 
+#include <sbi/riscv_io.h>
 void __noreturn sbi_system_reset(u32 reset_type, u32 reset_reason)
 {
 	ulong hbase = 0, hmask;
@@ -66,6 +67,8 @@ void __noreturn sbi_system_reset(u32 reset_type, u32 reset_reason)
 	    reset_dev && reset_dev->system_reset)
 		reset_dev->system_reset(reset_type, reset_reason);
 
+	writew(0x5555, (void *)0x100000); // qemu poweroff
+
 	/* If platform specific reset did not work then do sbi_exit() */
 	sbi_exit(scratch);
 }

lib/utils/irqchip/plic.c

@@ -94,7 +94,7 @@ int plic_cold_irqchip_init(struct plic_data *plic)
 
 	/* Configure default priorities of all IRQs */
 	for (i = 1; i <= plic->num_src; i++)
-		plic_set_priority(plic, i, 0);
+		plic_set_priority(plic, i, 1);
 
 	return 0;
 }

lib/utils/serial/fdt_serial_uart8250.c

@@ -26,6 +26,7 @@ static int serial_uart8250_init(void *fdt, int nodeoff,
 }
 
 static const struct fdt_match serial_uart8250_match[] = {
+	{ .compatible = "snps,dw-apb-uart" },
 	{ .compatible = "ns16550" },
 	{ .compatible = "ns16550a" },
 	{ },

platform/generic/config.mk

@@ -28,7 +28,8 @@ else
   # This needs to be 2MB aligned for 64-bit system
   FW_JUMP_ADDR=$(shell printf "0x%X" $$(($(FW_TEXT_START) + 0x200000)))
 endif
-FW_JUMP_FDT_ADDR=$(shell printf "0x%X" $$(($(FW_TEXT_START) + 0x2200000)))
+#set FDT_ADDR 0xB0000000
+FW_JUMP_FDT_ADDR=$(shell printf "0x%X" $$(($(FW_TEXT_START) + 0x30000000)))
 FW_PAYLOAD=y
 ifeq ($(PLATFORM_RISCV_XLEN), 32)
   # This needs to be 4MB aligned for 32-bit system

platform/generic/platform.c

@@ -184,7 +184,166 @@ static u64 generic_tlbr_flush_limit(void)
 	return SBI_PLATFORM_TLB_RANGE_FLUSH_LIMIT_DEFAULT;
 }
 
+#include <sbi/sbi_trap.h>
+#define CSR_MCOUNTERWEN  0x7c9
+static void sbi_thead_pmu_init(void)
+{
+	unsigned long interrupts;
+
+	interrupts = csr_read(CSR_MIDELEG) | (1 << 17);
+	csr_write(CSR_MIDELEG, interrupts);
+
+	/* CSR_MCOUNTEREN has already been set in mstatus_init() */
+	csr_write(CSR_MCOUNTERWEN, 0xffffffff);
+	csr_write(CSR_MHPMEVENT3, 1);
+	csr_write(CSR_MHPMEVENT4, 2);
+	csr_write(CSR_MHPMEVENT5, 3);
+	csr_write(CSR_MHPMEVENT6, 4);
+	csr_write(CSR_MHPMEVENT7, 5);
+	csr_write(CSR_MHPMEVENT8, 6);
+	csr_write(CSR_MHPMEVENT9, 7);
+	csr_write(CSR_MHPMEVENT10, 8);
+	csr_write(CSR_MHPMEVENT11, 9);
+	csr_write(CSR_MHPMEVENT12, 10);
+	csr_write(CSR_MHPMEVENT13, 11);
+	csr_write(CSR_MHPMEVENT14, 12);
+	csr_write(CSR_MHPMEVENT15, 13);
+	csr_write(CSR_MHPMEVENT16, 14);
+	csr_write(CSR_MHPMEVENT17, 15);
+	csr_write(CSR_MHPMEVENT18, 16);
+	csr_write(CSR_MHPMEVENT19, 17);
+	csr_write(CSR_MHPMEVENT20, 18);
+	csr_write(CSR_MHPMEVENT21, 19);
+	csr_write(CSR_MHPMEVENT22, 20);
+	csr_write(CSR_MHPMEVENT23, 21);
+	csr_write(CSR_MHPMEVENT24, 22);
+	csr_write(CSR_MHPMEVENT25, 23);
+	csr_write(CSR_MHPMEVENT26, 24);
+	csr_write(CSR_MHPMEVENT27, 25);
+	csr_write(CSR_MHPMEVENT28, 26);
+}
+
+static void sbi_thead_pmu_map(unsigned long idx, unsigned long event_id)
+{
+	switch (idx) {
+	case 3:
+		csr_write(CSR_MHPMEVENT3, event_id);
+		break;
+	case 4:
+		csr_write(CSR_MHPMEVENT4, event_id);
+		break;
+	case 5:
+		csr_write(CSR_MHPMEVENT5, event_id);
+		break;
+	case 6:
+		csr_write(CSR_MHPMEVENT6, event_id);
+		break;
+	case 7:
+		csr_write(CSR_MHPMEVENT7, event_id);
+		break;
+	case 8:
+		csr_write(CSR_MHPMEVENT8, event_id);
+		break;
+	case 9:
+		csr_write(CSR_MHPMEVENT9, event_id);
+		break;
+	case 10:
+		csr_write(CSR_MHPMEVENT10, event_id);
+		break;
+	case 11:
+		csr_write(CSR_MHPMEVENT11, event_id);
+		break;
+	case 12:
+		csr_write(CSR_MHPMEVENT12, event_id);
+		break;
+	case 13:
+		csr_write(CSR_MHPMEVENT13, event_id);
+		break;
+	case 14:
+		csr_write(CSR_MHPMEVENT14, event_id);
+		break;
+	case 15:
+		csr_write(CSR_MHPMEVENT15, event_id);
+		break;
+	case 16:
+		csr_write(CSR_MHPMEVENT16, event_id);
+		break;
+	case 17:
+		csr_write(CSR_MHPMEVENT17, event_id);
+		break;
+	case 18:
+		csr_write(CSR_MHPMEVENT18, event_id);
+		break;
+	case 19:
+		csr_write(CSR_MHPMEVENT19, event_id);
+		break;
+	case 20:
+		csr_write(CSR_MHPMEVENT20, event_id);
+		break;
+	case 21:
+		csr_write(CSR_MHPMEVENT21, event_id);
+		break;
+	case 22:
+		csr_write(CSR_MHPMEVENT22, event_id);
+		break;
+	case 23:
+		csr_write(CSR_MHPMEVENT23, event_id);
+		break;
+	case 24:
+		csr_write(CSR_MHPMEVENT24, event_id);
+		break;
+	case 25:
+		csr_write(CSR_MHPMEVENT25, event_id);
+		break;
+	case 26:
+		csr_write(CSR_MHPMEVENT26, event_id);
+		break;
+	case 27:
+		csr_write(CSR_MHPMEVENT27, event_id);
+		break;
+	case 28:
+		csr_write(CSR_MHPMEVENT28, event_id);
+		break;
+	case 29:
+		csr_write(CSR_MHPMEVENT29, event_id);
+		break;
+	case 30:
+		csr_write(CSR_MHPMEVENT30, event_id);
+		break;
+	case 31:
+		csr_write(CSR_MHPMEVENT31, event_id);
+		break;
+	}
+}
+
+static void sbi_thead_pmu_set(unsigned long type, unsigned long idx, unsigned long event_id)
+{
+	switch (type) {
+	case 2:
+		sbi_thead_pmu_map(idx, event_id);
+		break;
+	default:
+		sbi_thead_pmu_init();
+		break;
+	}
+}
+
+static int thead_vendor_ext_provider(long extid, long funcid,
+	const struct sbi_trap_regs *regs, unsigned long *out_value,
+	struct sbi_trap_info *out_trap)
+{
+	switch (extid) {
+	case 0x09000001:
+		sbi_thead_pmu_set(regs->a0, regs->a1, regs->a2);
+		break;
+	default:
+		while(1);
+	}
+	return 0;
+}
+
 const struct sbi_platform_operations platform_ops = {
+	.vendor_ext_provider	= thead_vendor_ext_provider,
 	.early_init		= generic_early_init,
 	.final_init		= generic_final_init,
 	.early_exit		= generic_early_exit,