opensbi: weekly rls 2025.02.27

e8de21, [fix](serial): Round UART8250 baud rate divisor to nearest integer
eb7ac6, [feat](opensbi):kernel log controled by CONFIG_SKIP_UBOOT_DEBUG while open CONFIG_SKIP_UBOOT
bdf7cc, [feat](opensbi): Add debug function in fastboot

Makefile

@@ -203,6 +203,17 @@ GENFLAGS	+=	$(libsbiutils-genflags-y)
 GENFLAGS	+=	$(platform-genflags-y)
 GENFLAGS	+=	$(firmware-genflags-y)
 
+define add_define
+    GENFLAGS	+=	-D$(1)$(if $(value $(1)),=$(value $(1)),)
+endef
+
+ifeq (${CONFIG_SKIP_UBOOT},y)
+$(eval $(call add_define,CONFIG_SKIP_UBOOT))
+endif
+ifeq (${CONFIG_SKIP_UBOOT_DEBUG},y)
+$(eval $(call add_define,CONFIG_SKIP_UBOOT_DEBUG))
+endif
+
 CFLAGS		=	-g -Wall -Werror -ffreestanding -nostdlib -fno-strict-aliasing -O2
 CFLAGS		+=	-fno-omit-frame-pointer -fno-optimize-sibling-calls
 CFLAGS		+=	-mno-save-restore -mstrict-align

lib/sbi/sbi_hart.c

@@ -21,10 +21,19 @@
 #include <sbi/sbi_platform.h>
 #include <sbi/sbi_string.h>
 #include <sbi/sbi_trap.h>
+#include <sbi/sbi_timer.h>
 
 extern void __sbi_expected_trap(void);
 extern void __sbi_expected_trap_hext(void);
 
+
+// Frequency of ARM arch timer and RISC-V rdtime
+#define SYS_COUNTER_FREQ_IN_SECOND 25000000
+#define TIME_RECORDS_ADDR ( 0x0E000000 + 0x10) // 0x0E000010
+#define TIME_RECORDS_FIELD_KERNEL_START (TIME_RECORDS_ADDR + 0x16)
+
+#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
+
 void (*sbi_hart_expected_trap)(void) = &__sbi_expected_trap;
 
 struct hart_features {
@@ -469,6 +478,15 @@ void __attribute__((noreturn)) sbi_hart_hang(void)
 	__builtin_unreachable();
 }
 
+int get_time()
+{
+	unsigned long long boot_us = 0;
+
+	boot_us = sbi_timer_value() / (SYS_COUNTER_FREQ_IN_SECOND / 1000000 );
+
+	return DIV_ROUND_UP(boot_us, 1000);
+}
+
 void __attribute__((noreturn))
 sbi_hart_switch_mode(unsigned long arg0, unsigned long arg1,
 		     unsigned long next_addr, unsigned long next_mode,
@@ -531,6 +549,8 @@ sbi_hart_switch_mode(unsigned long arg0, unsigned long arg1,
 		}
 	}
 
+	*(volatile uint16_t*)TIME_RECORDS_FIELD_KERNEL_START = get_time();
+	
 	register unsigned long a0 asm("a0") = arg0;
 	register unsigned long a1 asm("a1") = arg1;
 	__asm__ __volatile__("mret" : : "r"(a0), "r"(a1));

lib/sbi/sbi_init.c

@@ -35,112 +35,6 @@
 	"        | |\n"                                     \
 	"        |_|\n\n"
 
-static void sbi_boot_print_banner(struct sbi_scratch *scratch)
-{
-	if (scratch->options & SBI_SCRATCH_NO_BOOT_PRINTS)
-		return;
-
-#ifdef OPENSBI_VERSION_GIT
-	sbi_printf("\nOpenSBI %s\n", OPENSBI_VERSION_GIT);
-#else
-	sbi_printf("\nOpenSBI v%d.%d\n", OPENSBI_VERSION_MAJOR,
-		   OPENSBI_VERSION_MINOR);
-#endif
-
-	sbi_printf(BANNER);
-}
-
-static void sbi_boot_print_general(struct sbi_scratch *scratch)
-{
-	char str[128];
-	const struct sbi_hsm_device *hdev;
-	const struct sbi_ipi_device *idev;
-	const struct sbi_timer_device *tdev;
-	const struct sbi_console_device *cdev;
-	const struct sbi_system_reset_device *srdev;
-	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
-
-	if (scratch->options & SBI_SCRATCH_NO_BOOT_PRINTS)
-		return;
-
-	/* Platform details */
-	sbi_printf("Platform Name             : %s\n",
-		   sbi_platform_name(plat));
-	sbi_platform_get_features_str(plat, str, sizeof(str));
-	sbi_printf("Platform Features         : %s\n", str);
-	sbi_printf("Platform HART Count       : %u\n",
-		   sbi_platform_hart_count(plat));
-	idev = sbi_ipi_get_device();
-	sbi_printf("Platform IPI Device       : %s\n",
-		   (idev) ? idev->name : "---");
-	tdev = sbi_timer_get_device();
-	sbi_printf("Platform Timer Device     : %s\n",
-		   (tdev) ? tdev->name : "---");
-	cdev = sbi_console_get_device();
-	sbi_printf("Platform Console Device   : %s\n",
-		   (cdev) ? cdev->name : "---");
-	hdev = sbi_hsm_get_device();
-	sbi_printf("Platform HSM Device       : %s\n",
-		   (hdev) ? hdev->name : "---");
-	srdev = sbi_system_reset_get_device();
-	sbi_printf("Platform SysReset Device  : %s\n",
-		   (srdev) ? srdev->name : "---");
-
-	/* Firmware details */
-	sbi_printf("Firmware Base             : 0x%lx\n", scratch->fw_start);
-	sbi_printf("Firmware Size             : %d KB\n",
-		   (u32)(scratch->fw_size / 1024));
-
-	/* SBI details */
-	sbi_printf("Runtime SBI Version       : %d.%d\n",
-		   sbi_ecall_version_major(), sbi_ecall_version_minor());
-	sbi_printf("\n");
-}
-
-static void sbi_boot_print_domains(struct sbi_scratch *scratch)
-{
-	if (scratch->options & SBI_SCRATCH_NO_BOOT_PRINTS)
-		return;
-
-	/* Domain details */
-	sbi_domain_dump_all("      ");
-}
-
-static void sbi_boot_print_hart(struct sbi_scratch *scratch, u32 hartid)
-{
-	int xlen;
-	char str[128];
-	const struct sbi_domain *dom = sbi_domain_thishart_ptr();
-
-	if (scratch->options & SBI_SCRATCH_NO_BOOT_PRINTS)
-		return;
-
-	/* Determine MISA XLEN and MISA string */
-	xlen = misa_xlen();
-	if (xlen < 1) {
-		sbi_printf("Error %d getting MISA XLEN\n", xlen);
-		sbi_hart_hang();
-	}
-
-	/* Boot HART details */
-	sbi_printf("Boot HART ID              : %u\n", hartid);
-	sbi_printf("Boot HART Domain          : %s\n", dom->name);
-	misa_string(xlen, str, sizeof(str));
-	sbi_printf("Boot HART ISA             : %s\n", str);
-	sbi_hart_get_features_str(scratch, str, sizeof(str));
-	sbi_printf("Boot HART Features        : %s\n", str);
-	sbi_printf("Boot HART PMP Count       : %d\n",
-		   sbi_hart_pmp_count(scratch));
-	sbi_printf("Boot HART PMP Granularity : %lu\n",
-		   sbi_hart_pmp_granularity(scratch));
-	sbi_printf("Boot HART PMP Address Bits: %d\n",
-		   sbi_hart_pmp_addrbits(scratch));
-	sbi_printf("Boot HART MHPM Count      : %d\n",
-		   sbi_hart_mhpm_count(scratch));
-	sbi_printf("Boot HART MHPM Count      : %d\n",
-		   sbi_hart_mhpm_count(scratch));
-	sbi_hart_delegation_dump(scratch, "Boot HART ", "         ");
-}
 
 static spinlock_t coldboot_lock = SPIN_LOCK_INITIALIZER;
 static struct sbi_hartmask coldboot_wait_hmask = { 0 };
@@ -217,11 +111,14 @@ static void wake_coldboot_harts(struct sbi_scratch *scratch, u32 hartid)
 
 static unsigned long init_count_offset;
 
+#ifdef CONFIG_SKIP_UBOOT
+extern void generic_fdt_fixup_chosen(void);
+#endif
 static void __noreturn init_coldboot(struct sbi_scratch *scratch, u32 hartid)
 {
 	int rc;
 	unsigned long *init_count;
-	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
+	// const struct sbi_platform *plat = sbi_platform_ptr(scratch);
 
 	/* Note: This has to be first thing in coldboot init sequence */
 	rc = sbi_scratch_init(scratch);
@@ -242,32 +139,32 @@ static void __noreturn init_coldboot(struct sbi_scratch *scratch, u32 hartid)
 	if (rc)
 		sbi_hart_hang();
 
-	rc = sbi_platform_early_init(plat, TRUE);
+	// rc = sbi_platform_early_init(plat, TRUE);
-	if (rc)
+	// if (rc)
-		sbi_hart_hang();
+	// 	sbi_hart_hang();
 
 	rc = sbi_hart_init(scratch, TRUE);
 	if (rc)
 		sbi_hart_hang();
 
+#if defined(CONFIG_SKIP_UBOOT_DEBUG)
 	rc = sbi_console_init(scratch);
 	if (rc)
 		sbi_hart_hang();
+#endif
 
-	sbi_boot_print_banner(scratch);
+	// rc = sbi_platform_irqchip_init(plat, TRUE);
+	// if (rc) {
+	// 	sbi_printf("%s: platform irqchip init failed (error %d)\n",
+	// 		   __func__, rc);
+	// 	sbi_hart_hang();
+	// }
 
-	rc = sbi_platform_irqchip_init(plat, TRUE);
+	// rc = sbi_ipi_init(scratch, TRUE);
-	if (rc) {
+	// if (rc) {
-		sbi_printf("%s: platform irqchip init failed (error %d)\n",
+	// 	sbi_printf("%s: ipi init failed (error %d)\n", __func__, rc);
-			   __func__, rc);
+	// 	sbi_hart_hang();
-		sbi_hart_hang();
+	// }
-	}
-
-	rc = sbi_ipi_init(scratch, TRUE);
-	if (rc) {
-		sbi_printf("%s: ipi init failed (error %d)\n", __func__, rc);
-		sbi_hart_hang();
-	}
 
 	rc = sbi_tlb_init(scratch, TRUE);
 	if (rc) {
@@ -287,8 +184,6 @@ static void __noreturn init_coldboot(struct sbi_scratch *scratch, u32 hartid)
 		sbi_hart_hang();
 	}
 
-	sbi_boot_print_general(scratch);
-
 	/*
 	 * Note: Finalize domains after HSM initialization so that we
 	 * can startup non-root domains.
@@ -302,8 +197,6 @@ static void __noreturn init_coldboot(struct sbi_scratch *scratch, u32 hartid)
 		sbi_hart_hang();
 	}
 
-	sbi_boot_print_domains(scratch);
-
 	rc = sbi_hart_pmp_configure(scratch);
 	if (rc) {
 		sbi_printf("%s: PMP configure failed (error %d)\n",
@@ -315,14 +208,15 @@ static void __noreturn init_coldboot(struct sbi_scratch *scratch, u32 hartid)
 	 * Note: Platform final initialization should be last so that
 	 * it sees correct domain assignment and PMP configuration.
 	 */
-	rc = sbi_platform_final_init(plat, TRUE);
+	// rc = sbi_platform_final_init(plat, TRUE);
-	if (rc) {
+	// if (rc) {
-		sbi_printf("%s: platform final init failed (error %d)\n",
+	// 	sbi_printf("%s: platform final init failed (error %d)\n",
-			   __func__, rc);
+	// 		   __func__, rc);
-		sbi_hart_hang();
+	// 	sbi_hart_hang();
-	}
+	// }
-
+#ifdef CONFIG_SKIP_UBOOT
-	sbi_boot_print_hart(scratch, hartid);
+	generic_fdt_fixup_chosen();
+#endif
 
 	wake_coldboot_harts(scratch, hartid);
 

lib/sbi/sbi_system.c

@@ -42,6 +42,7 @@ bool sbi_system_reset_supported(u32 reset_type, u32 reset_reason)
 	return FALSE;
 }
 
+#include <sbi/riscv_io.h>
 void __noreturn sbi_system_reset(u32 reset_type, u32 reset_reason)
 {
 	ulong hbase = 0, hmask;
@@ -66,6 +67,8 @@ void __noreturn sbi_system_reset(u32 reset_type, u32 reset_reason)
 	    reset_dev && reset_dev->system_reset)
 		reset_dev->system_reset(reset_type, reset_reason);
 
+	writew(0x5555, (void *)0x100000); // qemu poweroff
+
 	/* If platform specific reset did not work then do sbi_exit() */
 	sbi_exit(scratch);
 }

lib/utils/fdt/fdt_fixup.c

@@ -17,6 +17,43 @@
 #include <sbi_utils/fdt/fdt_fixup.h>
 #include <sbi_utils/fdt/fdt_helper.h>
 
+#ifdef CONFIG_SKIP_UBOOT
+#include "cvipart.h"
+
+/* config root */
+#ifdef CONFIG_NAND_SUPPORT
+	#ifdef CONFIG_SKIP_RAMDISK
+		#define ROOTARGS "ubi.mtd=ROOTFS ubi.block=0,0 root=/dev/ubiblock0_0 rootfstype=squashfs"
+
+	#else
+		#define ROOTARGS "ubi.mtd=ROOTFS ubi.block=0,0"
+	#endif /* CONFIG_SKIP_RAMDISK */
+#else
+	#define ROOTARGS "rootfstype=squashfs rootwait ro root=" ROOTFS_DEV
+#endif
+
+/* BOOTARGS */
+#define PARTS  PART_LAYOUT
+
+/* config loglevel */
+#if defined(CONFIG_BUILD_FOR_DEBUG)
+    #define CONSOLE_LOGLEVEL   " loglevel=9 \0"
+    #define EARLYCON_RELEASE   " "
+#elif defined(CONFIG_SKIP_UBOOT_DEBUG)
+    #define CONSOLE_LOGLEVEL   " loglevel=9 \0"
+    #define EARLYCON_RELEASE   " release "
+#else
+    #define CONSOLE_LOGLEVEL   " loglevel=0 \0"
+    #define EARLYCON_RELEASE   " release "
+#endif
+
+
+#define CVI_BOOTAGRS \
+        PARTS " "  \
+        ROOTARGS " " \
+	"console=ttyS0,115200 earlycon=sbi riscv.fwsz=0x80000" CONSOLE_LOGLEVEL
+#endif
+
 void fdt_cpu_fixup(void *fdt)
 {
 	struct sbi_domain *dom = sbi_domain_thishart_ptr();
@@ -265,4 +302,19 @@ void fdt_fixups(void *fdt)
 	fdt_reserved_memory_fixup(fdt);
 }
 
+#ifdef CONFIG_SKIP_UBOOT
+void generic_fdt_fixup_chosen(void)
+{
+	void *fdt;
+	int   nodeoffset;
+	char  *str;		/* used to set string properties */
 
+	fdt = sbi_scratch_thishart_arg1_ptr();
+
+	nodeoffset = fdt_path_offset(fdt, "/chosen");
+
+	// str = "mtdparts=10000000.cvi-spif:512K(fip),1792K(2nd),3072K(jump),384K(PQ),64K(PARAM),64K(PARAM_BAK),64K(ENV),64K(ENV_BAK),2048K(ROOTFS),4096K(DATA) rootwait ro root=/dev/mtdblock8  rootfstype=squashfs console=ttyS0,115200 earlycon=sbi riscv.fwsz=0x80000 loglevel=9";
+	str = CVI_BOOTAGRS;
+	fdt_setprop(fdt, nodeoffset, "bootargs", str, strlen(str) + 1);
+}
+#endif

lib/utils/irqchip/plic.c

@@ -94,7 +94,7 @@ int plic_cold_irqchip_init(struct plic_data *plic)
 
 	/* Configure default priorities of all IRQs */
 	for (i = 1; i <= plic->num_src; i++)
-		plic_set_priority(plic, i, 0);
+		plic_set_priority(plic, i, 1);
 
 	return 0;
 }

lib/utils/serial/fdt_serial_uart8250.c

@@ -26,6 +26,7 @@ static int serial_uart8250_init(void *fdt, int nodeoff,
 }
 
 static const struct fdt_match serial_uart8250_match[] = {
+	{ .compatible = "snps,dw-apb-uart" },
 	{ .compatible = "ns16550" },
 	{ .compatible = "ns16550a" },
 	{ },

lib/utils/serial/uart8250.c

@@ -101,7 +101,7 @@ int uart8250_init(unsigned long base, u32 in_freq, u32 baudrate, u32 reg_shift,
 	uart8250_in_freq   = in_freq;
 	uart8250_baudrate  = baudrate;
 
-	bdiv = uart8250_in_freq / (16 * uart8250_baudrate);
+	bdiv = (uart8250_in_freq + 8 * uart8250_baudrate) / (16 * uart8250_baudrate);
 
 	/* Disable all interrupts */
 	set_reg(UART_IER_OFFSET, 0x00);

lib/utils/timer/fdt_timer_clint.c

@@ -15,7 +15,9 @@
 #define CLINT_TIMER_MAX_NR			16
 
 static unsigned long clint_timer_count = 0;
-static struct clint_data clint_timer[CLINT_TIMER_MAX_NR];
+static struct clint_data clint_timer[CLINT_TIMER_MAX_NR] = {
+	{.addr = 0x74000000, .first_hartid = 0, .hart_count = 1, .has_64bit_mmio = 0, },
+};
 
 static int timer_clint_cold_init(void *fdt, int nodeoff,
 				  const struct fdt_match *match)
@@ -29,9 +31,11 @@ static int timer_clint_cold_init(void *fdt, int nodeoff,
 	if (1 < clint_timer_count)
 		ctmaster = &clint_timer[0];
 
-	rc = fdt_parse_clint_node(fdt, nodeoff, TRUE, ct);
+	if (clint_timer_count != 1) {
-	if (rc)
+		rc = fdt_parse_clint_node(fdt, nodeoff, TRUE, ct);
-		return rc;
+		if (rc)
+			return rc;
+	}
 
 	return clint_cold_timer_init(ct, ctmaster);
 }

platform/generic/config.mk

@@ -28,7 +28,8 @@ else
   # This needs to be 2MB aligned for 64-bit system
   FW_JUMP_ADDR=$(shell printf "0x%X" $$(($(FW_TEXT_START) + 0x200000)))
 endif
-FW_JUMP_FDT_ADDR=$(shell printf "0x%X" $$(($(FW_TEXT_START) + 0x2200000)))
+#set FDT_ADDR 0xB0000000
+FW_JUMP_FDT_ADDR=$(shell printf "0x%X" $$(($(FW_TEXT_START) + 0x80000)))
 FW_PAYLOAD=y
 ifeq ($(PLATFORM_RISCV_XLEN), 32)
   # This needs to be 4MB aligned for 32-bit system

platform/generic/platform.c

@@ -184,7 +184,166 @@ static u64 generic_tlbr_flush_limit(void)
 	return SBI_PLATFORM_TLB_RANGE_FLUSH_LIMIT_DEFAULT;
 }
 
+#include <sbi/sbi_trap.h>
+#define CSR_MCOUNTERWEN  0x7c9
+static void sbi_thead_pmu_init(void)
+{
+	unsigned long interrupts;
+
+	interrupts = csr_read(CSR_MIDELEG) | (1 << 17);
+	csr_write(CSR_MIDELEG, interrupts);
+
+	/* CSR_MCOUNTEREN has already been set in mstatus_init() */
+	csr_write(CSR_MCOUNTERWEN, 0xffffffff);
+	csr_write(CSR_MHPMEVENT3, 1);
+	csr_write(CSR_MHPMEVENT4, 2);
+	csr_write(CSR_MHPMEVENT5, 3);
+	csr_write(CSR_MHPMEVENT6, 4);
+	csr_write(CSR_MHPMEVENT7, 5);
+	csr_write(CSR_MHPMEVENT8, 6);
+	csr_write(CSR_MHPMEVENT9, 7);
+	csr_write(CSR_MHPMEVENT10, 8);
+	csr_write(CSR_MHPMEVENT11, 9);
+	csr_write(CSR_MHPMEVENT12, 10);
+	csr_write(CSR_MHPMEVENT13, 11);
+	csr_write(CSR_MHPMEVENT14, 12);
+	csr_write(CSR_MHPMEVENT15, 13);
+	csr_write(CSR_MHPMEVENT16, 14);
+	csr_write(CSR_MHPMEVENT17, 15);
+	csr_write(CSR_MHPMEVENT18, 16);
+	csr_write(CSR_MHPMEVENT19, 17);
+	csr_write(CSR_MHPMEVENT20, 18);
+	csr_write(CSR_MHPMEVENT21, 19);
+	csr_write(CSR_MHPMEVENT22, 20);
+	csr_write(CSR_MHPMEVENT23, 21);
+	csr_write(CSR_MHPMEVENT24, 22);
+	csr_write(CSR_MHPMEVENT25, 23);
+	csr_write(CSR_MHPMEVENT26, 24);
+	csr_write(CSR_MHPMEVENT27, 25);
+	csr_write(CSR_MHPMEVENT28, 26);
+}
+
+static void sbi_thead_pmu_map(unsigned long idx, unsigned long event_id)
+{
+	switch (idx) {
+	case 3:
+		csr_write(CSR_MHPMEVENT3, event_id);
+		break;
+	case 4:
+		csr_write(CSR_MHPMEVENT4, event_id);
+		break;
+	case 5:
+		csr_write(CSR_MHPMEVENT5, event_id);
+		break;
+	case 6:
+		csr_write(CSR_MHPMEVENT6, event_id);
+		break;
+	case 7:
+		csr_write(CSR_MHPMEVENT7, event_id);
+		break;
+	case 8:
+		csr_write(CSR_MHPMEVENT8, event_id);
+		break;
+	case 9:
+		csr_write(CSR_MHPMEVENT9, event_id);
+		break;
+	case 10:
+		csr_write(CSR_MHPMEVENT10, event_id);
+		break;
+	case 11:
+		csr_write(CSR_MHPMEVENT11, event_id);
+		break;
+	case 12:
+		csr_write(CSR_MHPMEVENT12, event_id);
+		break;
+	case 13:
+		csr_write(CSR_MHPMEVENT13, event_id);
+		break;
+	case 14:
+		csr_write(CSR_MHPMEVENT14, event_id);
+		break;
+	case 15:
+		csr_write(CSR_MHPMEVENT15, event_id);
+		break;
+	case 16:
+		csr_write(CSR_MHPMEVENT16, event_id);
+		break;
+	case 17:
+		csr_write(CSR_MHPMEVENT17, event_id);
+		break;
+	case 18:
+		csr_write(CSR_MHPMEVENT18, event_id);
+		break;
+	case 19:
+		csr_write(CSR_MHPMEVENT19, event_id);
+		break;
+	case 20:
+		csr_write(CSR_MHPMEVENT20, event_id);
+		break;
+	case 21:
+		csr_write(CSR_MHPMEVENT21, event_id);
+		break;
+	case 22:
+		csr_write(CSR_MHPMEVENT22, event_id);
+		break;
+	case 23:
+		csr_write(CSR_MHPMEVENT23, event_id);
+		break;
+	case 24:
+		csr_write(CSR_MHPMEVENT24, event_id);
+		break;
+	case 25:
+		csr_write(CSR_MHPMEVENT25, event_id);
+		break;
+	case 26:
+		csr_write(CSR_MHPMEVENT26, event_id);
+		break;
+	case 27:
+		csr_write(CSR_MHPMEVENT27, event_id);
+		break;
+	case 28:
+		csr_write(CSR_MHPMEVENT28, event_id);
+		break;
+	case 29:
+		csr_write(CSR_MHPMEVENT29, event_id);
+		break;
+	case 30:
+		csr_write(CSR_MHPMEVENT30, event_id);
+		break;
+	case 31:
+		csr_write(CSR_MHPMEVENT31, event_id);
+		break;
+	}
+}
+
+static void sbi_thead_pmu_set(unsigned long type, unsigned long idx, unsigned long event_id)
+{
+	switch (type) {
+	case 2:
+		sbi_thead_pmu_map(idx, event_id);
+		break;
+	default:
+		sbi_thead_pmu_init();
+		break;
+	}
+}
+
+static int thead_vendor_ext_provider(long extid, long funcid,
+	const struct sbi_trap_regs *regs, unsigned long *out_value,
+	struct sbi_trap_info *out_trap)
+{
+	switch (extid) {
+	case 0x09000001:
+		sbi_thead_pmu_set(regs->a0, regs->a1, regs->a2);
+		break;
+	default:
+		while(1);
+	}
+	return 0;
+}
+
 const struct sbi_platform_operations platform_ops = {
+	.vendor_ext_provider	= thead_vendor_ext_provider,
 	.early_init		= generic_early_init,
 	.final_init		= generic_final_init,
 	.early_exit		= generic_early_exit,