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barrier: add more stronger constraint

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xiaoguang.xing
2023-05-29 10:00:22 +08:00
parent 19622b6c93
commit e1d3b68eeb
1 changed files with 4 additions and 4 deletions
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8
include/sbi/riscv_barrier.h
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@@ -25,19 +25,19 @@
#define mb() RISCV_FENCE(iorw,iorw) #define mb() RISCV_FENCE(iorw,iorw)
/* Read Memory barrier */ /* Read Memory barrier */
#define rmb() RISCV_FENCE(ir,ir) #define rmb() RISCV_FENCE(ir,iorw)
/* Write Memory barrier */ /* Write Memory barrier */
#define wmb() RISCV_FENCE(ow,ow) #define wmb() RISCV_FENCE(iorw,ow)
/* SMP Read & Write Memory barrier */ /* SMP Read & Write Memory barrier */
#define smp_mb() RISCV_FENCE(rw,rw) #define smp_mb() RISCV_FENCE(rw,rw)
/* SMP Read Memory barrier */ /* SMP Read Memory barrier */
#define smp_rmb() RISCV_FENCE(r,r) #define smp_rmb() RISCV_FENCE(r,rw)
/* SMP Write Memory barrier */ /* SMP Write Memory barrier */
#define smp_wmb() RISCV_FENCE(w,w) #define smp_wmb() RISCV_FENCE(rw,w)
/* CPU relax for busy loop */ /* CPU relax for busy loop */
#define cpu_relax() asm volatile ("" : : : "memory") #define cpu_relax() asm volatile ("" : : : "memory")